drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 /* date: Fri Dec  4 18:49:44 2020 */
   7
   8 #ifndef ULP_TEMPLATE_DB_H_
   9 #define ULP_TEMPLATE_DB_H_
  10
  11 #define BNXT_ULP_REGFILE_MAX_SZ 32
  12 #define BNXT_ULP_MAX_NUM_DEVICES 4
  13 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2
  14 #define BNXT_ULP_GEN_TBL_MAX_SZ 6
  15 #define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 512
  16 #define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 81
  17 #define BNXT_ULP_CLASS_HID_LOW_PRIME 4049
  18 #define BNXT_ULP_CLASS_HID_HIGH_PRIME 7919
  19 #define BNXT_ULP_CLASS_HID_SHFTR 25
  20 #define BNXT_ULP_CLASS_HID_SHFTL 23
  21 #define BNXT_ULP_CLASS_HID_MASK 511
  22 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048
  23 #define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 15
  24 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919
  25 #define BNXT_ULP_ACT_HID_HIGH_PRIME 7919
  26 #define BNXT_ULP_ACT_HID_SHFTR 24
  27 #define BNXT_ULP_ACT_HID_SHFTL 23
  28 #define BNXT_ULP_ACT_HID_MASK 2047
  29 #define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 8
  30 #define BNXT_ULP_GLB_TEMPLATE_TBL_MAX_SZ 1
  31 #define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7
  32 #define BNXT_ULP_HDR_SIG_ID_SHIFT 4
  33 #define BNXT_ULP_GLB_FIELD_TBL_SIZE 3033
  34 #define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 7
  35 #define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 41
  36 #define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 257
  37 #define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 11
  38 #define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 367
  39 #define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 14
  40 #define ULP_STINGRAY_CLASS_TMPL_LIST_SIZE 7
  41 #define ULP_STINGRAY_CLASS_TBL_LIST_SIZE 38
  42 #define ULP_STINGRAY_CLASS_KEY_INFO_LIST_SIZE 192
  43 #define ULP_STINGRAY_CLASS_IDENT_LIST_SIZE 10
  44 #define ULP_STINGRAY_CLASS_RESULT_FIELD_LIST_SIZE 341
  45 #define ULP_STINGRAY_CLASS_COND_LIST_SIZE 10
  46 #define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 2
  47 #define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 4
  48 #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 0
  49 #define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 0
  50 #define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 65
  51 #define ULP_WH_PLUS_ACT_COND_LIST_SIZE 11
  52 #define ULP_STINGRAY_ACT_TMPL_LIST_SIZE 2
  53 #define ULP_STINGRAY_ACT_TBL_LIST_SIZE 4
  54 #define ULP_STINGRAY_ACT_KEY_INFO_LIST_SIZE 0
  55 #define ULP_STINGRAY_ACT_IDENT_LIST_SIZE 0
  56 #define ULP_STINGRAY_ACT_RESULT_FIELD_LIST_SIZE 65
  57 #define ULP_STINGRAY_ACT_COND_LIST_SIZE 2
  58
  59 enum bnxt_ulp_act_bit {
  60         BNXT_ULP_ACT_BIT_MARK                = 0x0000000000000001,
  61         BNXT_ULP_ACT_BIT_DROP                = 0x0000000000000002,
  62         BNXT_ULP_ACT_BIT_COUNT               = 0x0000000000000004,
  63         BNXT_ULP_ACT_BIT_RSS                 = 0x0000000000000008,
  64         BNXT_ULP_ACT_BIT_METER               = 0x0000000000000010,
  65         BNXT_ULP_ACT_BIT_VXLAN_DECAP         = 0x0000000000000020,
  66         BNXT_ULP_ACT_BIT_POP_MPLS            = 0x0000000000000040,
  67         BNXT_ULP_ACT_BIT_PUSH_MPLS           = 0x0000000000000080,
  68         BNXT_ULP_ACT_BIT_MAC_SWAP            = 0x0000000000000100,
  69         BNXT_ULP_ACT_BIT_SET_MAC_SRC         = 0x0000000000000200,
  70         BNXT_ULP_ACT_BIT_SET_MAC_DST         = 0x0000000000000400,
  71         BNXT_ULP_ACT_BIT_POP_VLAN            = 0x0000000000000800,
  72         BNXT_ULP_ACT_BIT_PUSH_VLAN           = 0x0000000000001000,
  73         BNXT_ULP_ACT_BIT_SET_VLAN_PCP        = 0x0000000000002000,
  74         BNXT_ULP_ACT_BIT_SET_VLAN_VID        = 0x0000000000004000,
  75         BNXT_ULP_ACT_BIT_SET_IPV4_SRC        = 0x0000000000008000,
  76         BNXT_ULP_ACT_BIT_SET_IPV4_DST        = 0x0000000000010000,
  77         BNXT_ULP_ACT_BIT_SET_IPV6_SRC        = 0x0000000000020000,
  78         BNXT_ULP_ACT_BIT_SET_IPV6_DST        = 0x0000000000040000,
  79         BNXT_ULP_ACT_BIT_DEC_TTL             = 0x0000000000080000,
  80         BNXT_ULP_ACT_BIT_SET_TP_SRC          = 0x0000000000100000,
  81         BNXT_ULP_ACT_BIT_SET_TP_DST          = 0x0000000000200000,
  82         BNXT_ULP_ACT_BIT_VXLAN_ENCAP         = 0x0000000000400000,
  83         BNXT_ULP_ACT_BIT_JUMP                = 0x0000000000800000,
  84         BNXT_ULP_ACT_BIT_SHARED              = 0x0000000001000000,
  85         BNXT_ULP_ACT_BIT_SAMPLE              = 0x0000000002000000,
  86         BNXT_ULP_ACT_BIT_SHARED_SAMPLE       = 0x0000000004000000,
  87         BNXT_ULP_ACT_BIT_LAST                = 0x0000000008000000
  88 };
  89
  90 enum bnxt_ulp_hdr_bit {
  91         BNXT_ULP_HDR_BIT_O_ETH               = 0x0000000000000001,
  92         BNXT_ULP_HDR_BIT_OO_VLAN             = 0x0000000000000002,
  93         BNXT_ULP_HDR_BIT_OI_VLAN             = 0x0000000000000004,
  94         BNXT_ULP_HDR_BIT_O_IPV4              = 0x0000000000000008,
  95         BNXT_ULP_HDR_BIT_O_IPV6              = 0x0000000000000010,
  96         BNXT_ULP_HDR_BIT_O_TCP               = 0x0000000000000020,
  97         BNXT_ULP_HDR_BIT_O_UDP               = 0x0000000000000040,
  98         BNXT_ULP_HDR_BIT_T_VXLAN             = 0x0000000000000080,
  99         BNXT_ULP_HDR_BIT_T_GRE               = 0x0000000000000100,
 100         BNXT_ULP_HDR_BIT_I_ETH               = 0x0000000000000200,
 101         BNXT_ULP_HDR_BIT_IO_VLAN             = 0x0000000000000400,
 102         BNXT_ULP_HDR_BIT_II_VLAN             = 0x0000000000000800,
 103         BNXT_ULP_HDR_BIT_I_IPV4              = 0x0000000000001000,
 104         BNXT_ULP_HDR_BIT_I_IPV6              = 0x0000000000002000,
 105         BNXT_ULP_HDR_BIT_I_TCP               = 0x0000000000004000,
 106         BNXT_ULP_HDR_BIT_I_UDP               = 0x0000000000008000,
 107         BNXT_ULP_HDR_BIT_F1                  = 0x0000000000010000,
 108         BNXT_ULP_HDR_BIT_LAST                = 0x0000000000020000
 109 };
 110
 111 enum bnxt_ulp_accept_opc {
 112         BNXT_ULP_ACCEPT_OPC_ALWAYS = 0,
 113         BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH = 1,
 114         BNXT_ULP_ACCEPT_OPC_LAST = 2
 115 };
 116
 117 enum bnxt_ulp_act_type {
 118         BNXT_ULP_ACT_TYPE_NOT_SUPPORTED = 0,
 119         BNXT_ULP_ACT_TYPE_SUPPORTED = 1,
 120         BNXT_ULP_ACT_TYPE_END = 2,
 121         BNXT_ULP_ACT_TYPE_LAST = 3
 122 };
 123
 124 enum bnxt_ulp_byte_order {
 125         BNXT_ULP_BYTE_ORDER_BE = 0,
 126         BNXT_ULP_BYTE_ORDER_LE = 1,
 127         BNXT_ULP_BYTE_ORDER_LAST = 2
 128 };
 129
 130 enum bnxt_ulp_cf_idx {
 131         BNXT_ULP_CF_IDX_NOT_USED = 0,
 132         BNXT_ULP_CF_IDX_MPLS_TAG_NUM = 1,
 133         BNXT_ULP_CF_IDX_O_VTAG_NUM = 2,
 134         BNXT_ULP_CF_IDX_O_NO_VTAG = 3,
 135         BNXT_ULP_CF_IDX_O_ONE_VTAG = 4,
 136         BNXT_ULP_CF_IDX_O_TWO_VTAGS = 5,
 137         BNXT_ULP_CF_IDX_I_VTAG_NUM = 6,
 138         BNXT_ULP_CF_IDX_I_NO_VTAG = 7,
 139         BNXT_ULP_CF_IDX_I_ONE_VTAG = 8,
 140         BNXT_ULP_CF_IDX_I_TWO_VTAGS = 9,
 141         BNXT_ULP_CF_IDX_INCOMING_IF = 10,
 142         BNXT_ULP_CF_IDX_DIRECTION = 11,
 143         BNXT_ULP_CF_IDX_SVIF_FLAG = 12,
 144         BNXT_ULP_CF_IDX_O_L3 = 13,
 145         BNXT_ULP_CF_IDX_I_L3 = 14,
 146         BNXT_ULP_CF_IDX_O_L4 = 15,
 147         BNXT_ULP_CF_IDX_I_L4 = 16,
 148         BNXT_ULP_CF_IDX_DEV_PORT_ID = 17,
 149         BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 18,
 150         BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 19,
 151         BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 20,
 152         BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 21,
 153         BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 22,
 154         BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 23,
 155         BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 24,
 156         BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 25,
 157         BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 26,
 158         BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 27,
 159         BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 28,
 160         BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 29,
 161         BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 30,
 162         BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG = 31,
 163         BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG = 32,
 164         BNXT_ULP_CF_IDX_ACT_DEC_TTL = 33,
 165         BNXT_ULP_CF_IDX_ACT_T_DEC_TTL = 34,
 166         BNXT_ULP_CF_IDX_ACT_PORT_IS_SET = 35,
 167         BNXT_ULP_CF_IDX_ACT_PORT_TYPE = 36,
 168         BNXT_ULP_CF_IDX_MATCH_PORT_TYPE = 37,
 169         BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP = 38,
 170         BNXT_ULP_CF_IDX_VF_TO_VF = 39,
 171         BNXT_ULP_CF_IDX_L3_HDR_CNT = 40,
 172         BNXT_ULP_CF_IDX_L4_HDR_CNT = 41,
 173         BNXT_ULP_CF_IDX_VFR_MODE = 42,
 174         BNXT_ULP_CF_IDX_L3_TUN = 43,
 175         BNXT_ULP_CF_IDX_L3_TUN_DECAP = 44,
 176         BNXT_ULP_CF_IDX_FID = 45,
 177         BNXT_ULP_CF_IDX_HDR_SIG_ID = 46,
 178         BNXT_ULP_CF_IDX_FLOW_SIG_ID = 47,
 179         BNXT_ULP_CF_IDX_LAST = 48
 180 };
 181
 182 enum bnxt_ulp_cond_list_opc {
 183         BNXT_ULP_COND_LIST_OPC_TRUE = 0,
 184         BNXT_ULP_COND_LIST_OPC_FALSE = 1,
 185         BNXT_ULP_COND_LIST_OPC_OR = 2,
 186         BNXT_ULP_COND_LIST_OPC_AND = 3,
 187         BNXT_ULP_COND_LIST_OPC_LAST = 4
 188 };
 189
 190 enum bnxt_ulp_cond_opc {
 191         BNXT_ULP_COND_OPC_CF_IS_SET = 0,
 192         BNXT_ULP_COND_OPC_CF_NOT_SET = 1,
 193         BNXT_ULP_COND_OPC_ACT_BIT_IS_SET = 2,
 194         BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET = 3,
 195         BNXT_ULP_COND_OPC_HDR_BIT_IS_SET = 4,
 196         BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET = 5,
 197         BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET = 6,
 198         BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET = 7,
 199         BNXT_ULP_COND_OPC_RF_IS_SET = 8,
 200         BNXT_ULP_COND_OPC_RF_NOT_SET = 9,
 201         BNXT_ULP_COND_OPC_LAST = 10
 202 };
 203
 204 enum bnxt_ulp_critical_resource {
 205         BNXT_ULP_CRITICAL_RESOURCE_NO = 0,
 206         BNXT_ULP_CRITICAL_RESOURCE_YES = 1,
 207         BNXT_ULP_CRITICAL_RESOURCE_LAST = 2
 208 };
 209
 210 enum bnxt_ulp_device_id {
 211         BNXT_ULP_DEVICE_ID_WH_PLUS = 0,
 212         BNXT_ULP_DEVICE_ID_THOR = 1,
 213         BNXT_ULP_DEVICE_ID_STINGRAY = 2,
 214         BNXT_ULP_DEVICE_ID_STINGRAY2 = 3,
 215         BNXT_ULP_DEVICE_ID_LAST = 4
 216 };
 217
 218 enum bnxt_ulp_df_param_type {
 219         BNXT_ULP_DF_PARAM_TYPE_DEV_PORT_ID = 0,
 220         BNXT_ULP_DF_PARAM_TYPE_LAST = 1
 221 };
 222
 223 enum bnxt_ulp_direction {
 224         BNXT_ULP_DIRECTION_INGRESS = 0,
 225         BNXT_ULP_DIRECTION_EGRESS = 1,
 226         BNXT_ULP_DIRECTION_LAST = 2
 227 };
 228
 229 enum bnxt_ulp_fdb_opc {
 230         BNXT_ULP_FDB_OPC_PUSH = 0,
 231         BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE = 1,
 232         BNXT_ULP_FDB_OPC_PUSH_REGFILE = 2,
 233         BNXT_ULP_FDB_OPC_NOP = 3,
 234         BNXT_ULP_FDB_OPC_LAST = 4
 235 };
 236
 237 enum bnxt_ulp_fdb_type {
 238         BNXT_ULP_FDB_TYPE_REGULAR = 0,
 239         BNXT_ULP_FDB_TYPE_DEFAULT = 1,
 240         BNXT_ULP_FDB_TYPE_RID = 2,
 241         BNXT_ULP_FDB_TYPE_LAST = 3
 242 };
 243
 244 enum bnxt_ulp_field_cond_src {
 245         BNXT_ULP_FIELD_COND_SRC_TRUE = 0,
 246         BNXT_ULP_FIELD_COND_SRC_CF = 1,
 247         BNXT_ULP_FIELD_COND_SRC_RF = 2,
 248         BNXT_ULP_FIELD_COND_SRC_ACT_BIT = 3,
 249         BNXT_ULP_FIELD_COND_SRC_HDR_BIT = 4,
 250         BNXT_ULP_FIELD_COND_SRC_FIELD_BIT = 5,
 251         BNXT_ULP_FIELD_COND_SRC_SRC1_PLUS_SRC2 = 6,
 252         BNXT_ULP_FIELD_COND_SRC_LAST = 7
 253 };
 254
 255 enum bnxt_ulp_field_src {
 256         BNXT_ULP_FIELD_SRC_ZERO = 0,
 257         BNXT_ULP_FIELD_SRC_CONST = 1,
 258         BNXT_ULP_FIELD_SRC_CF = 2,
 259         BNXT_ULP_FIELD_SRC_RF = 3,
 260         BNXT_ULP_FIELD_SRC_ACT_PROP = 4,
 261         BNXT_ULP_FIELD_SRC_ACT_PROP_SZ = 5,
 262         BNXT_ULP_FIELD_SRC_GLB_RF = 6,
 263         BNXT_ULP_FIELD_SRC_HF = 7,
 264         BNXT_ULP_FIELD_SRC_HDR_BIT = 8,
 265         BNXT_ULP_FIELD_SRC_ACT_BIT = 9,
 266         BNXT_ULP_FIELD_SRC_FIELD_BIT = 10,
 267         BNXT_ULP_FIELD_SRC_SKIP = 11,
 268         BNXT_ULP_FIELD_SRC_REJECT = 12,
 269         BNXT_ULP_FIELD_SRC_LAST = 13
 270 };
 271
 272 enum bnxt_ulp_generic_tbl_opc {
 273         BNXT_ULP_GENERIC_TBL_OPC_NOT_USED = 0,
 274         BNXT_ULP_GENERIC_TBL_OPC_READ = 1,
 275         BNXT_ULP_GENERIC_TBL_OPC_WRITE = 2,
 276         BNXT_ULP_GENERIC_TBL_OPC_LAST = 3
 277 };
 278
 279 enum bnxt_ulp_glb_rf_idx {
 280         BNXT_ULP_GLB_RF_IDX_NOT_USED = 0,
 281         BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID = 1,
 282         BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR = 2,
 283         BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID = 3,
 284         BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID = 4,
 285         BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR = 5,
 286         BNXT_ULP_GLB_RF_IDX_LAST = 6
 287 };
 288
 289 enum bnxt_ulp_hdr_type {
 290         BNXT_ULP_HDR_TYPE_NOT_SUPPORTED = 0,
 291         BNXT_ULP_HDR_TYPE_SUPPORTED = 1,
 292         BNXT_ULP_HDR_TYPE_END = 2,
 293         BNXT_ULP_HDR_TYPE_LAST = 3
 294 };
 295
 296 enum bnxt_ulp_if_tbl_opc {
 297         BNXT_ULP_IF_TBL_OPC_NOT_USED = 0,
 298         BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD = 1,
 299         BNXT_ULP_IF_TBL_OPC_WR_REGFILE = 2,
 300         BNXT_ULP_IF_TBL_OPC_WR_CONST = 3,
 301         BNXT_ULP_IF_TBL_OPC_RD_COMP_FIELD = 4,
 302         BNXT_ULP_IF_TBL_OPC_LAST = 5
 303 };
 304
 305 enum bnxt_ulp_index_tbl_opc {
 306         BNXT_ULP_INDEX_TBL_OPC_NOT_USED = 0,
 307         BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE = 1,
 308         BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE = 2,
 309         BNXT_ULP_INDEX_TBL_OPC_SRCH_ALLOC_WR_REGFILE = 3,
 310         BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE = 4,
 311         BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE = 5,
 312         BNXT_ULP_INDEX_TBL_OPC_RD_REGFILE = 6,
 313         BNXT_ULP_INDEX_TBL_OPC_LAST = 7
 314 };
 315
 316 enum bnxt_ulp_mark_db_opc {
 317         BNXT_ULP_MARK_DB_OPC_NOP = 0,
 318         BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION = 1,
 319         BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG = 2,
 320         BNXT_ULP_MARK_DB_OPC_LAST = 3
 321 };
 322
 323 enum bnxt_ulp_match_type {
 324         BNXT_ULP_MATCH_TYPE_EM = 0,
 325         BNXT_ULP_MATCH_TYPE_WM = 1,
 326         BNXT_ULP_MATCH_TYPE_LAST = 2
 327 };
 328
 329 enum bnxt_ulp_mem_type_opc {
 330         BNXT_ULP_MEM_TYPE_OPC_NOP = 0,
 331         BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT = 1,
 332         BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT = 2,
 333         BNXT_ULP_MEM_TYPE_OPC_LAST = 3
 334 };
 335
 336 enum bnxt_ulp_pri_opc {
 337         BNXT_ULP_PRI_OPC_NOT_USED = 0,
 338         BNXT_ULP_PRI_OPC_CONST = 1,
 339         BNXT_ULP_PRI_OPC_APP_PRI = 2,
 340         BNXT_ULP_PRI_OPC_LAST = 3
 341 };
 342
 343 enum bnxt_ulp_rf_idx {
 344         BNXT_ULP_RF_IDX_NOT_USED = 0,
 345         BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 = 1,
 346         BNXT_ULP_RF_IDX_L2_CNTXT_ID_1 = 2,
 347         BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 = 3,
 348         BNXT_ULP_RF_IDX_PROF_FUNC_ID_1 = 4,
 349         BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 = 5,
 350         BNXT_ULP_RF_IDX_EM_PROFILE_ID_1 = 6,
 351         BNXT_ULP_RF_IDX_WC_PROFILE_ID_0 = 7,
 352         BNXT_ULP_RF_IDX_WC_PROFILE_ID_1 = 8,
 353         BNXT_ULP_RF_IDX_MAIN_ACTION_PTR = 9,
 354         BNXT_ULP_RF_IDX_ACTION_PTR_0 = 10,
 355         BNXT_ULP_RF_IDX_ENCAP_PTR_0 = 11,
 356         BNXT_ULP_RF_IDX_ENCAP_PTR_1 = 12,
 357         BNXT_ULP_RF_IDX_CRITICAL_RESOURCE = 13,
 358         BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 = 14,
 359         BNXT_ULP_RF_IDX_MAIN_SP_PTR = 15,
 360         BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 = 16,
 361         BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 = 17,
 362         BNXT_ULP_RF_IDX_ACTION_REC_SIZE = 18,
 363         BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 = 19,
 364         BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_1 = 20,
 365         BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 = 21,
 366         BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_1 = 22,
 367         BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0 = 23,
 368         BNXT_ULP_RF_IDX_WC_TCAM_INDEX_1 = 24,
 369         BNXT_ULP_RF_IDX_SRC_PROPERTY_PTR = 25,
 370         BNXT_ULP_RF_IDX_GENERIC_TBL_HIT = 26,
 371         BNXT_ULP_RF_IDX_MIRROR_PTR_0 = 27,
 372         BNXT_ULP_RF_IDX_MIRROR_ID_0 = 28,
 373         BNXT_ULP_RF_IDX_HDR_SIG_ID = 29,
 374         BNXT_ULP_RF_IDX_FLOW_SIG_ID = 30,
 375         BNXT_ULP_RF_IDX_RID = 31,
 376         BNXT_ULP_RF_IDX_LAST = 32
 377 };
 378
 379 enum bnxt_ulp_tcam_tbl_opc {
 380         BNXT_ULP_TCAM_TBL_OPC_NOT_USED = 0,
 381         BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE = 1,
 382         BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE = 2,
 383         BNXT_ULP_TCAM_TBL_OPC_LAST = 3
 384 };
 385
 386 enum bnxt_ulp_template_type {
 387         BNXT_ULP_TEMPLATE_TYPE_CLASS = 0,
 388         BNXT_ULP_TEMPLATE_TYPE_ACTION = 1,
 389         BNXT_ULP_TEMPLATE_TYPE_LAST = 2
 390 };
 391
 392 enum bnxt_ulp_fdb_resource_flags {
 393         BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_INGR = 0x00,
 394         BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_EGR = 0x01
 395 };
 396
 397 enum bnxt_ulp_flow_dir_bitmask {
 398         BNXT_ULP_FLOW_DIR_BITMASK_ING = 0x0000000000000000,
 399         BNXT_ULP_FLOW_DIR_BITMASK_EGR = 0x8000000000000000
 400 };
 401
 402 enum bnxt_ulp_match_type_bitmask {
 403         BNXT_ULP_MATCH_TYPE_BITMASK_EM = 0x0000000000000000,
 404         BNXT_ULP_MATCH_TYPE_BITMASK_WM = 0x8000000000000000
 405 };
 406
 407 enum bnxt_ulp_resource_func {
 408         BNXT_ULP_RESOURCE_FUNC_INVALID = 0x00,
 409         BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE = 0x20,
 410         BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE = 0x40,
 411         BNXT_ULP_RESOURCE_FUNC_RSVD2 = 0x60,
 412         BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE = 0x80,
 413         BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE = 0x81,
 414         BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE = 0x82,
 415         BNXT_ULP_RESOURCE_FUNC_IDENTIFIER = 0x83,
 416         BNXT_ULP_RESOURCE_FUNC_IF_TABLE = 0x84,
 417         BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85,
 418         BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW = 0x86,
 419         BNXT_ULP_RESOURCE_FUNC_CHILD_FLOW = 0x87,
 420         BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE = 0x88
 421 };
 422
 423 enum bnxt_ulp_resource_sub_type {
 424         BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED = 0,
 425         BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL = 0,
 426         BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION = 1,
 427         BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT = 2,
 428         BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC = 3,
 429         BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_EXT_COUNT = 4,
 430         BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM = 0,
 431         BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM = 1,
 432         BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR = 2
 433 };
 434
 435 enum bnxt_ulp_act_prop_sz {
 436         BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN_SZ = 4,
 437         BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SZ = 4,
 438         BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_SZ = 4,
 439         BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_TYPE = 4,
 440         BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_NUM = 4,
 441         BNXT_ULP_ACT_PROP_SZ_ENCAP_L3_TYPE = 4,
 442         BNXT_ULP_ACT_PROP_SZ_MPLS_POP_NUM = 4,
 443         BNXT_ULP_ACT_PROP_SZ_MPLS_PUSH_NUM = 4,
 444         BNXT_ULP_ACT_PROP_SZ_PORT_ID = 4,
 445         BNXT_ULP_ACT_PROP_SZ_VNIC = 4,
 446         BNXT_ULP_ACT_PROP_SZ_VPORT = 4,
 447         BNXT_ULP_ACT_PROP_SZ_MARK = 4,
 448         BNXT_ULP_ACT_PROP_SZ_COUNT = 4,
 449         BNXT_ULP_ACT_PROP_SZ_METER = 4,
 450         BNXT_ULP_ACT_PROP_SZ_SET_MAC_SRC = 8,
 451         BNXT_ULP_ACT_PROP_SZ_SET_MAC_DST = 8,
 452         BNXT_ULP_ACT_PROP_SZ_PUSH_VLAN = 2,
 453         BNXT_ULP_ACT_PROP_SZ_SET_VLAN_PCP = 1,
 454         BNXT_ULP_ACT_PROP_SZ_SET_VLAN_VID = 2,
 455         BNXT_ULP_ACT_PROP_SZ_SET_IPV4_SRC = 4,
 456         BNXT_ULP_ACT_PROP_SZ_SET_IPV4_DST = 4,
 457         BNXT_ULP_ACT_PROP_SZ_SET_IPV6_SRC = 16,
 458         BNXT_ULP_ACT_PROP_SZ_SET_IPV6_DST = 16,
 459         BNXT_ULP_ACT_PROP_SZ_SET_TP_SRC = 2,
 460         BNXT_ULP_ACT_PROP_SZ_SET_TP_DST = 2,
 461         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_0 = 4,
 462         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_1 = 4,
 463         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_2 = 4,
 464         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_3 = 4,
 465         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_4 = 4,
 466         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_5 = 4,
 467         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_6 = 4,
 468         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_7 = 4,
 469         BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_DMAC = 6,
 470         BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_SMAC = 6,
 471         BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG = 8,
 472         BNXT_ULP_ACT_PROP_SZ_ENCAP_IP = 32,
 473         BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC = 16,
 474         BNXT_ULP_ACT_PROP_SZ_ENCAP_UDP = 4,
 475         BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN = 32,
 476         BNXT_ULP_ACT_PROP_SZ_JUMP = 4,
 477         BNXT_ULP_ACT_PROP_SZ_SHARED_HANDLE = 8,
 478         BNXT_ULP_ACT_PROP_SZ_LAST = 4
 479 };
 480
 481 enum bnxt_ulp_act_prop_idx {
 482         BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ = 0,
 483         BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ = 4,
 484         BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ = 8,
 485         BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE = 12,
 486         BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_NUM = 16,
 487         BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE = 20,
 488         BNXT_ULP_ACT_PROP_IDX_MPLS_POP_NUM = 24,
 489         BNXT_ULP_ACT_PROP_IDX_MPLS_PUSH_NUM = 28,
 490         BNXT_ULP_ACT_PROP_IDX_PORT_ID = 32,
 491         BNXT_ULP_ACT_PROP_IDX_VNIC = 36,
 492         BNXT_ULP_ACT_PROP_IDX_VPORT = 40,
 493         BNXT_ULP_ACT_PROP_IDX_MARK = 44,
 494         BNXT_ULP_ACT_PROP_IDX_COUNT = 48,
 495         BNXT_ULP_ACT_PROP_IDX_METER = 52,
 496         BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC = 56,
 497         BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST = 64,
 498         BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN = 72,
 499         BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP = 74,
 500         BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID = 75,
 501         BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC = 77,
 502         BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST = 81,
 503         BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC = 85,
 504         BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST = 101,
 505         BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC = 117,
 506         BNXT_ULP_ACT_PROP_IDX_SET_TP_DST = 119,
 507         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0 = 121,
 508         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1 = 125,
 509         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2 = 129,
 510         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3 = 133,
 511         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4 = 137,
 512         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5 = 141,
 513         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6 = 145,
 514         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7 = 149,
 515         BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC = 153,
 516         BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC = 159,
 517         BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG = 165,
 518         BNXT_ULP_ACT_PROP_IDX_ENCAP_IP = 173,
 519         BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC = 205,
 520         BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP = 221,
 521         BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 225,
 522         BNXT_ULP_ACT_PROP_IDX_JUMP = 257,
 523         BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE = 261,
 524         BNXT_ULP_ACT_PROP_IDX_LAST = 269
 525 };
 526
 527 enum ulp_wp_sym {
 528         ULP_WP_SYM_PKT_TYPE_IGNORE = 0,
 529         ULP_WP_SYM_PKT_TYPE_L2 = 0,
 530         ULP_WP_SYM_PKT_TYPE_0_IGNORE = 0,
 531         ULP_WP_SYM_PKT_TYPE_0_L2 = 0,
 532         ULP_WP_SYM_PKT_TYPE_1_IGNORE = 0,
 533         ULP_WP_SYM_PKT_TYPE_1_L2 = 0,
 534         ULP_WP_SYM_RECYCLE_CNT_IGNORE = 0,
 535         ULP_WP_SYM_RECYCLE_CNT_ZERO = 0,
 536         ULP_WP_SYM_RECYCLE_CNT_ONE = 1,
 537         ULP_WP_SYM_RECYCLE_CNT_TWO = 2,
 538         ULP_WP_SYM_RECYCLE_CNT_THREE = 3,
 539         ULP_WP_SYM_AGG_ERROR_IGNORE = 0,
 540         ULP_WP_SYM_AGG_ERROR_NO = 0,
 541         ULP_WP_SYM_AGG_ERROR_YES = 1,
 542         ULP_WP_SYM_RESERVED_IGNORE = 0,
 543         ULP_WP_SYM_HREC_NEXT_IGNORE = 0,
 544         ULP_WP_SYM_HREC_NEXT_NO = 0,
 545         ULP_WP_SYM_HREC_NEXT_YES = 1,
 546         ULP_WP_SYM_TL2_HDR_VALID_IGNORE = 0,
 547         ULP_WP_SYM_TL2_HDR_VALID_NO = 0,
 548         ULP_WP_SYM_TL2_HDR_VALID_YES = 1,
 549         ULP_WP_SYM_TL2_HDR_TYPE_IGNORE = 0,
 550         ULP_WP_SYM_TL2_HDR_TYPE_DIX = 0,
 551         ULP_WP_SYM_TL2_UC_MC_BC_IGNORE = 0,
 552         ULP_WP_SYM_TL2_UC_MC_BC_UC = 0,
 553         ULP_WP_SYM_TL2_UC_MC_BC_MC = 2,
 554         ULP_WP_SYM_TL2_UC_MC_BC_BC = 3,
 555         ULP_WP_SYM_TL2_VTAG_PRESENT_IGNORE = 0,
 556         ULP_WP_SYM_TL2_VTAG_PRESENT_NO = 0,
 557         ULP_WP_SYM_TL2_VTAG_PRESENT_YES = 1,
 558         ULP_WP_SYM_TL2_TWO_VTAGS_IGNORE = 0,
 559         ULP_WP_SYM_TL2_TWO_VTAGS_NO = 0,
 560         ULP_WP_SYM_TL2_TWO_VTAGS_YES = 1,
 561         ULP_WP_SYM_TL3_HDR_VALID_IGNORE = 0,
 562         ULP_WP_SYM_TL3_HDR_VALID_NO = 0,
 563         ULP_WP_SYM_TL3_HDR_VALID_YES = 1,
 564         ULP_WP_SYM_TL3_HDR_ERROR_IGNORE = 0,
 565         ULP_WP_SYM_TL3_HDR_ERROR_NO = 0,
 566         ULP_WP_SYM_TL3_HDR_ERROR_YES = 1,
 567         ULP_WP_SYM_TL3_HDR_TYPE_IGNORE = 0,
 568         ULP_WP_SYM_TL3_HDR_TYPE_IPV4 = 0,
 569         ULP_WP_SYM_TL3_HDR_TYPE_IPV6 = 1,
 570         ULP_WP_SYM_TL3_HDR_ISIP_IGNORE = 0,
 571         ULP_WP_SYM_TL3_HDR_ISIP_NO = 0,
 572         ULP_WP_SYM_TL3_HDR_ISIP_YES = 1,
 573         ULP_WP_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0,
 574         ULP_WP_SYM_TL3_IPV6_CMP_SRC_NO = 0,
 575         ULP_WP_SYM_TL3_IPV6_CMP_SRC_YES = 1,
 576         ULP_WP_SYM_TL3_IPV6_CMP_DST_IGNORE = 0,
 577         ULP_WP_SYM_TL3_IPV6_CMP_DST_NO = 0,
 578         ULP_WP_SYM_TL3_IPV6_CMP_DST_YES = 1,
 579         ULP_WP_SYM_TL4_HDR_VALID_IGNORE = 0,
 580         ULP_WP_SYM_TL4_HDR_VALID_NO = 0,
 581         ULP_WP_SYM_TL4_HDR_VALID_YES = 1,
 582         ULP_WP_SYM_TL4_HDR_ERROR_IGNORE = 0,
 583         ULP_WP_SYM_TL4_HDR_ERROR_NO = 0,
 584         ULP_WP_SYM_TL4_HDR_ERROR_YES = 1,
 585         ULP_WP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0,
 586         ULP_WP_SYM_TL4_HDR_IS_UDP_TCP_NO = 0,
 587         ULP_WP_SYM_TL4_HDR_IS_UDP_TCP_YES = 1,
 588         ULP_WP_SYM_TL4_HDR_TYPE_IGNORE = 0,
 589         ULP_WP_SYM_TL4_HDR_TYPE_TCP = 0,
 590         ULP_WP_SYM_TL4_HDR_TYPE_UDP = 1,
 591         ULP_WP_SYM_TUN_HDR_VALID_IGNORE = 0,
 592         ULP_WP_SYM_TUN_HDR_VALID_NO = 0,
 593         ULP_WP_SYM_TUN_HDR_VALID_YES = 1,
 594         ULP_WP_SYM_TUN_HDR_ERROR_IGNORE = 0,
 595         ULP_WP_SYM_TUN_HDR_ERROR_NO = 0,
 596         ULP_WP_SYM_TUN_HDR_ERROR_YES = 1,
 597         ULP_WP_SYM_TUN_HDR_TYPE_IGNORE = 0,
 598         ULP_WP_SYM_TUN_HDR_TYPE_VXLAN = 0,
 599         ULP_WP_SYM_TUN_HDR_TYPE_GENEVE = 1,
 600         ULP_WP_SYM_TUN_HDR_TYPE_NVGRE = 2,
 601         ULP_WP_SYM_TUN_HDR_TYPE_GRE = 3,
 602         ULP_WP_SYM_TUN_HDR_TYPE_IPV4 = 4,
 603         ULP_WP_SYM_TUN_HDR_TYPE_IPV6 = 5,
 604         ULP_WP_SYM_TUN_HDR_TYPE_PPPOE = 6,
 605         ULP_WP_SYM_TUN_HDR_TYPE_MPLS = 7,
 606         ULP_WP_SYM_TUN_HDR_TYPE_UPAR1 = 8,
 607         ULP_WP_SYM_TUN_HDR_TYPE_UPAR2 = 9,
 608         ULP_WP_SYM_TUN_HDR_TYPE_NONE = 15,
 609         ULP_WP_SYM_TUN_HDR_FLAGS_IGNORE = 0,
 610         ULP_WP_SYM_L2_HDR_VALID_IGNORE = 0,
 611         ULP_WP_SYM_L2_HDR_VALID_NO = 0,
 612         ULP_WP_SYM_L2_HDR_VALID_YES = 1,
 613         ULP_WP_SYM_L2_HDR_ERROR_IGNORE = 0,
 614         ULP_WP_SYM_L2_HDR_ERROR_NO = 0,
 615         ULP_WP_SYM_L2_HDR_ERROR_YES = 1,
 616         ULP_WP_SYM_L2_HDR_TYPE_IGNORE = 0,
 617         ULP_WP_SYM_L2_HDR_TYPE_DIX = 0,
 618         ULP_WP_SYM_L2_HDR_TYPE_LLC_SNAP = 1,
 619         ULP_WP_SYM_L2_HDR_TYPE_LLC = 2,
 620         ULP_WP_SYM_L2_UC_MC_BC_IGNORE = 0,
 621         ULP_WP_SYM_L2_UC_MC_BC_UC = 0,
 622         ULP_WP_SYM_L2_UC_MC_BC_MC = 2,
 623         ULP_WP_SYM_L2_UC_MC_BC_BC = 3,
 624         ULP_WP_SYM_L2_VTAG_PRESENT_IGNORE = 0,
 625         ULP_WP_SYM_L2_VTAG_PRESENT_NO = 0,
 626         ULP_WP_SYM_L2_VTAG_PRESENT_YES = 1,
 627         ULP_WP_SYM_L2_TWO_VTAGS_IGNORE = 0,
 628         ULP_WP_SYM_L2_TWO_VTAGS_NO = 0,
 629         ULP_WP_SYM_L2_TWO_VTAGS_YES = 1,
 630         ULP_WP_SYM_L3_HDR_VALID_IGNORE = 0,
 631         ULP_WP_SYM_L3_HDR_VALID_NO = 0,
 632         ULP_WP_SYM_L3_HDR_VALID_YES = 1,
 633         ULP_WP_SYM_L3_HDR_ERROR_IGNORE = 0,
 634         ULP_WP_SYM_L3_HDR_ERROR_NO = 0,
 635         ULP_WP_SYM_L3_HDR_ERROR_YES = 1,
 636         ULP_WP_SYM_L3_HDR_TYPE_IGNORE = 0,
 637         ULP_WP_SYM_L3_HDR_TYPE_IPV4 = 0,
 638         ULP_WP_SYM_L3_HDR_TYPE_IPV6 = 1,
 639         ULP_WP_SYM_L3_HDR_TYPE_ARP = 2,
 640         ULP_WP_SYM_L3_HDR_TYPE_PTP = 3,
 641         ULP_WP_SYM_L3_HDR_TYPE_EAPOL = 4,
 642         ULP_WP_SYM_L3_HDR_TYPE_ROCE = 5,
 643         ULP_WP_SYM_L3_HDR_TYPE_FCOE = 6,
 644         ULP_WP_SYM_L3_HDR_TYPE_UPAR1 = 7,
 645         ULP_WP_SYM_L3_HDR_TYPE_UPAR2 = 8,
 646         ULP_WP_SYM_L3_HDR_ISIP_IGNORE = 0,
 647         ULP_WP_SYM_L3_HDR_ISIP_NO = 0,
 648         ULP_WP_SYM_L3_HDR_ISIP_YES = 1,
 649         ULP_WP_SYM_L3_IPV6_CMP_SRC_IGNORE = 0,
 650         ULP_WP_SYM_L3_IPV6_CMP_SRC_NO = 0,
 651         ULP_WP_SYM_L3_IPV6_CMP_SRC_YES = 1,
 652         ULP_WP_SYM_L3_IPV6_CMP_DST_IGNORE = 0,
 653         ULP_WP_SYM_L3_IPV6_CMP_DST_NO = 0,
 654         ULP_WP_SYM_L3_IPV6_CMP_DST_YES = 1,
 655         ULP_WP_SYM_L4_HDR_VALID_IGNORE = 0,
 656         ULP_WP_SYM_L4_HDR_VALID_NO = 0,
 657         ULP_WP_SYM_L4_HDR_VALID_YES = 1,
 658         ULP_WP_SYM_L4_HDR_ERROR_IGNORE = 0,
 659         ULP_WP_SYM_L4_HDR_ERROR_NO = 0,
 660         ULP_WP_SYM_L4_HDR_ERROR_YES = 1,
 661         ULP_WP_SYM_L4_HDR_TYPE_IGNORE = 0,
 662         ULP_WP_SYM_L4_HDR_TYPE_TCP = 0,
 663         ULP_WP_SYM_L4_HDR_TYPE_UDP = 1,
 664         ULP_WP_SYM_L4_HDR_TYPE_ICMP = 2,
 665         ULP_WP_SYM_L4_HDR_TYPE_UPAR1 = 3,
 666         ULP_WP_SYM_L4_HDR_TYPE_UPAR2 = 4,
 667         ULP_WP_SYM_L4_HDR_TYPE_BTH_V1 = 5,
 668         ULP_WP_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0,
 669         ULP_WP_SYM_L4_HDR_IS_UDP_TCP_NO = 0,
 670         ULP_WP_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
 671         ULP_WP_SYM_POP_VLAN_NO = 0,
 672         ULP_WP_SYM_POP_VLAN_YES = 1,
 673         ULP_WP_SYM_DECAP_FUNC_NONE = 0,
 674         ULP_WP_SYM_DECAP_FUNC_THRU_TL2 = 3,
 675         ULP_WP_SYM_DECAP_FUNC_THRU_TL3 = 8,
 676         ULP_WP_SYM_DECAP_FUNC_THRU_TL4 = 9,
 677         ULP_WP_SYM_DECAP_FUNC_THRU_TUN = 10,
 678         ULP_WP_SYM_DECAP_FUNC_THRU_L2 = 11,
 679         ULP_WP_SYM_DECAP_FUNC_THRU_L3 = 12,
 680         ULP_WP_SYM_DECAP_FUNC_THRU_L4 = 13,
 681         ULP_WP_SYM_ECV_VALID_NO = 0,
 682         ULP_WP_SYM_ECV_VALID_YES = 1,
 683         ULP_WP_SYM_ECV_CUSTOM_EN_NO = 0,
 684         ULP_WP_SYM_ECV_CUSTOM_EN_YES = 1,
 685         ULP_WP_SYM_ECV_L2_EN_NO = 0,
 686         ULP_WP_SYM_ECV_L2_EN_YES = 1,
 687         ULP_WP_SYM_ECV_VTAG_TYPE_NOP = 0,
 688         ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1,
 689         ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2,
 690         ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3,
 691         ULP_WP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4,
 692         ULP_WP_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5,
 693         ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6,
 694         ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7,
 695         ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8,
 696         ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8,
 697         ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8,
 698         ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8,
 699         ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8,
 700         ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8,
 701         ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8,
 702         ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8,
 703         ULP_WP_SYM_ECV_L3_TYPE_NONE = 0,
 704         ULP_WP_SYM_ECV_L3_TYPE_IPV4 = 4,
 705         ULP_WP_SYM_ECV_L3_TYPE_IPV6 = 5,
 706         ULP_WP_SYM_ECV_L3_TYPE_MPLS_8847 = 6,
 707         ULP_WP_SYM_ECV_L3_TYPE_MPLS_8848 = 7,
 708         ULP_WP_SYM_ECV_L4_TYPE_NONE = 0,
 709         ULP_WP_SYM_ECV_L4_TYPE_UDP = 4,
 710         ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM = 5,
 711         ULP_WP_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6,
 712         ULP_WP_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7,
 713         ULP_WP_SYM_ECV_TUN_TYPE_NONE = 0,
 714         ULP_WP_SYM_ECV_TUN_TYPE_GENERIC = 1,
 715         ULP_WP_SYM_ECV_TUN_TYPE_VXLAN = 2,
 716         ULP_WP_SYM_ECV_TUN_TYPE_NGE = 3,
 717         ULP_WP_SYM_ECV_TUN_TYPE_NVGRE = 4,
 718         ULP_WP_SYM_ECV_TUN_TYPE_GRE = 5,
 719         ULP_WP_SYM_EEM_ACT_REC_INT = 1,
 720         ULP_WP_SYM_EEM_EXT_FLOW_CNTR = 0,
 721         ULP_WP_SYM_UC_ACT_REC = 0,
 722         ULP_WP_SYM_MC_ACT_REC = 1,
 723         ULP_WP_SYM_ACT_REC_DROP_YES = 1,
 724         ULP_WP_SYM_ACT_REC_DROP_NO = 0,
 725         ULP_WP_SYM_ACT_REC_POP_VLAN_YES = 1,
 726         ULP_WP_SYM_ACT_REC_POP_VLAN_NO = 0,
 727         ULP_WP_SYM_ACT_REC_METER_EN_YES = 1,
 728         ULP_WP_SYM_ACT_REC_METER_EN_NO = 0,
 729         ULP_WP_SYM_LOOPBACK_PORT = 4,
 730         ULP_WP_SYM_LOOPBACK_PARIF = 15,
 731         ULP_WP_SYM_EXT_EM_MAX_KEY_SIZE = 448,
 732         ULP_WP_SYM_MATCH_TYPE_EM = 0,
 733         ULP_WP_SYM_MATCH_TYPE_WM = 1,
 734         ULP_WP_SYM_IP_PROTO_ICMP = 1,
 735         ULP_WP_SYM_IP_PROTO_IGMP = 2,
 736         ULP_WP_SYM_IP_PROTO_IP_IN_IP = 4,
 737         ULP_WP_SYM_IP_PROTO_TCP = 6,
 738         ULP_WP_SYM_IP_PROTO_UDP = 17,
 739         ULP_WP_SYM_VF_FUNC_PARIF = 15,
 740         ULP_WP_SYM_NO = 0,
 741         ULP_WP_SYM_YES = 1,
 742         ULP_WP_SYM_RECYCLE_DST = 0x800
 743 };
 744
 745 enum ulp_sr_sym {
 746         ULP_SR_SYM_PKT_TYPE_IGNORE = 0,
 747         ULP_SR_SYM_PKT_TYPE_L2 = 0,
 748         ULP_SR_SYM_PKT_TYPE_0_IGNORE = 0,
 749         ULP_SR_SYM_PKT_TYPE_0_L2 = 0,
 750         ULP_SR_SYM_PKT_TYPE_1_IGNORE = 0,
 751         ULP_SR_SYM_PKT_TYPE_1_L2 = 0,
 752         ULP_SR_SYM_RECYCLE_CNT_IGNORE = 0,
 753         ULP_SR_SYM_RECYCLE_CNT_ZERO = 0,
 754         ULP_SR_SYM_RECYCLE_CNT_ONE = 1,
 755         ULP_SR_SYM_RECYCLE_CNT_TWO = 2,
 756         ULP_SR_SYM_RECYCLE_CNT_THREE = 3,
 757         ULP_SR_SYM_AGG_ERROR_IGNORE = 0,
 758         ULP_SR_SYM_AGG_ERROR_NO = 0,
 759         ULP_SR_SYM_AGG_ERROR_YES = 1,
 760         ULP_SR_SYM_RESERVED_IGNORE = 0,
 761         ULP_SR_SYM_HREC_NEXT_IGNORE = 0,
 762         ULP_SR_SYM_HREC_NEXT_NO = 0,
 763         ULP_SR_SYM_HREC_NEXT_YES = 1,
 764         ULP_SR_SYM_TL2_HDR_VALID_IGNORE = 0,
 765         ULP_SR_SYM_TL2_HDR_VALID_NO = 0,
 766         ULP_SR_SYM_TL2_HDR_VALID_YES = 1,
 767         ULP_SR_SYM_TL2_HDR_TYPE_IGNORE = 0,
 768         ULP_SR_SYM_TL2_HDR_TYPE_DIX = 0,
 769         ULP_SR_SYM_TL2_UC_MC_BC_IGNORE = 0,
 770         ULP_SR_SYM_TL2_UC_MC_BC_UC = 0,
 771         ULP_SR_SYM_TL2_UC_MC_BC_MC = 2,
 772         ULP_SR_SYM_TL2_UC_MC_BC_BC = 3,
 773         ULP_SR_SYM_TL2_VTAG_PRESENT_IGNORE = 0,
 774         ULP_SR_SYM_TL2_VTAG_PRESENT_NO = 0,
 775         ULP_SR_SYM_TL2_VTAG_PRESENT_YES = 1,
 776         ULP_SR_SYM_TL2_TWO_VTAGS_IGNORE = 0,
 777         ULP_SR_SYM_TL2_TWO_VTAGS_NO = 0,
 778         ULP_SR_SYM_TL2_TWO_VTAGS_YES = 1,
 779         ULP_SR_SYM_TL3_HDR_VALID_IGNORE = 0,
 780         ULP_SR_SYM_TL3_HDR_VALID_NO = 0,
 781         ULP_SR_SYM_TL3_HDR_VALID_YES = 1,
 782         ULP_SR_SYM_TL3_HDR_ERROR_IGNORE = 0,
 783         ULP_SR_SYM_TL3_HDR_ERROR_NO = 0,
 784         ULP_SR_SYM_TL3_HDR_ERROR_YES = 1,
 785         ULP_SR_SYM_TL3_HDR_TYPE_IGNORE = 0,
 786         ULP_SR_SYM_TL3_HDR_TYPE_IPV4 = 0,
 787         ULP_SR_SYM_TL3_HDR_TYPE_IPV6 = 1,
 788         ULP_SR_SYM_TL3_HDR_ISIP_IGNORE = 0,
 789         ULP_SR_SYM_TL3_HDR_ISIP_NO = 0,
 790         ULP_SR_SYM_TL3_HDR_ISIP_YES = 1,
 791         ULP_SR_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0,
 792         ULP_SR_SYM_TL3_IPV6_CMP_SRC_NO = 0,
 793         ULP_SR_SYM_TL3_IPV6_CMP_SRC_YES = 1,
 794         ULP_SR_SYM_TL3_IPV6_CMP_DST_IGNORE = 0,
 795         ULP_SR_SYM_TL3_IPV6_CMP_DST_NO = 0,
 796         ULP_SR_SYM_TL3_IPV6_CMP_DST_YES = 1,
 797         ULP_SR_SYM_TL4_HDR_VALID_IGNORE = 0,
 798         ULP_SR_SYM_TL4_HDR_VALID_NO = 0,
 799         ULP_SR_SYM_TL4_HDR_VALID_YES = 1,
 800         ULP_SR_SYM_TL4_HDR_ERROR_IGNORE = 0,
 801         ULP_SR_SYM_TL4_HDR_ERROR_NO = 0,
 802         ULP_SR_SYM_TL4_HDR_ERROR_YES = 1,
 803         ULP_SR_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0,
 804         ULP_SR_SYM_TL4_HDR_IS_UDP_TCP_NO = 0,
 805         ULP_SR_SYM_TL4_HDR_IS_UDP_TCP_YES = 1,
 806         ULP_SR_SYM_TL4_HDR_TYPE_IGNORE = 0,
 807         ULP_SR_SYM_TL4_HDR_TYPE_TCP = 0,
 808         ULP_SR_SYM_TL4_HDR_TYPE_UDP = 1,
 809         ULP_SR_SYM_TUN_HDR_VALID_IGNORE = 0,
 810         ULP_SR_SYM_TUN_HDR_VALID_NO = 0,
 811         ULP_SR_SYM_TUN_HDR_VALID_YES = 1,
 812         ULP_SR_SYM_TUN_HDR_ERROR_IGNORE = 0,
 813         ULP_SR_SYM_TUN_HDR_ERROR_NO = 0,
 814         ULP_SR_SYM_TUN_HDR_ERROR_YES = 1,
 815         ULP_SR_SYM_TUN_HDR_TYPE_IGNORE = 0,
 816         ULP_SR_SYM_TUN_HDR_TYPE_VXLAN = 0,
 817         ULP_SR_SYM_TUN_HDR_TYPE_GENEVE = 1,
 818         ULP_SR_SYM_TUN_HDR_TYPE_NVGRE = 2,
 819         ULP_SR_SYM_TUN_HDR_TYPE_GRE = 3,
 820         ULP_SR_SYM_TUN_HDR_TYPE_IPV4 = 4,
 821         ULP_SR_SYM_TUN_HDR_TYPE_IPV6 = 5,
 822         ULP_SR_SYM_TUN_HDR_TYPE_PPPOE = 6,
 823         ULP_SR_SYM_TUN_HDR_TYPE_MPLS = 7,
 824         ULP_SR_SYM_TUN_HDR_TYPE_UPAR1 = 8,
 825         ULP_SR_SYM_TUN_HDR_TYPE_UPAR2 = 9,
 826         ULP_SR_SYM_TUN_HDR_TYPE_NONE = 15,
 827         ULP_SR_SYM_TUN_HDR_FLAGS_IGNORE = 0,
 828         ULP_SR_SYM_L2_HDR_VALID_IGNORE = 0,
 829         ULP_SR_SYM_L2_HDR_VALID_NO = 0,
 830         ULP_SR_SYM_L2_HDR_VALID_YES = 1,
 831         ULP_SR_SYM_L2_HDR_ERROR_IGNORE = 0,
 832         ULP_SR_SYM_L2_HDR_ERROR_NO = 0,
 833         ULP_SR_SYM_L2_HDR_ERROR_YES = 1,
 834         ULP_SR_SYM_L2_HDR_TYPE_IGNORE = 0,
 835         ULP_SR_SYM_L2_HDR_TYPE_DIX = 0,
 836         ULP_SR_SYM_L2_HDR_TYPE_LLC_SNAP = 1,
 837         ULP_SR_SYM_L2_HDR_TYPE_LLC = 2,
 838         ULP_SR_SYM_L2_UC_MC_BC_IGNORE = 0,
 839         ULP_SR_SYM_L2_UC_MC_BC_UC = 0,
 840         ULP_SR_SYM_L2_UC_MC_BC_MC = 2,
 841         ULP_SR_SYM_L2_UC_MC_BC_BC = 3,
 842         ULP_SR_SYM_L2_VTAG_PRESENT_IGNORE = 0,
 843         ULP_SR_SYM_L2_VTAG_PRESENT_NO = 0,
 844         ULP_SR_SYM_L2_VTAG_PRESENT_YES = 1,
 845         ULP_SR_SYM_L2_TWO_VTAGS_IGNORE = 0,
 846         ULP_SR_SYM_L2_TWO_VTAGS_NO = 0,
 847         ULP_SR_SYM_L2_TWO_VTAGS_YES = 1,
 848         ULP_SR_SYM_L3_HDR_VALID_IGNORE = 0,
 849         ULP_SR_SYM_L3_HDR_VALID_NO = 0,
 850         ULP_SR_SYM_L3_HDR_VALID_YES = 1,
 851         ULP_SR_SYM_L3_HDR_ERROR_IGNORE = 0,
 852         ULP_SR_SYM_L3_HDR_ERROR_NO = 0,
 853         ULP_SR_SYM_L3_HDR_ERROR_YES = 1,
 854         ULP_SR_SYM_L3_HDR_TYPE_IGNORE = 0,
 855         ULP_SR_SYM_L3_HDR_TYPE_IPV4 = 0,
 856         ULP_SR_SYM_L3_HDR_TYPE_IPV6 = 1,
 857         ULP_SR_SYM_L3_HDR_TYPE_ARP = 2,
 858         ULP_SR_SYM_L3_HDR_TYPE_PTP = 3,
 859         ULP_SR_SYM_L3_HDR_TYPE_EAPOL = 4,
 860         ULP_SR_SYM_L3_HDR_TYPE_ROCE = 5,
 861         ULP_SR_SYM_L3_HDR_TYPE_FCOE = 6,
 862         ULP_SR_SYM_L3_HDR_TYPE_UPAR1 = 7,
 863         ULP_SR_SYM_L3_HDR_TYPE_UPAR2 = 8,
 864         ULP_SR_SYM_L3_HDR_ISIP_IGNORE = 0,
 865         ULP_SR_SYM_L3_HDR_ISIP_NO = 0,
 866         ULP_SR_SYM_L3_HDR_ISIP_YES = 1,
 867         ULP_SR_SYM_L3_IPV6_CMP_SRC_IGNORE = 0,
 868         ULP_SR_SYM_L3_IPV6_CMP_SRC_NO = 0,
 869         ULP_SR_SYM_L3_IPV6_CMP_SRC_YES = 1,
 870         ULP_SR_SYM_L3_IPV6_CMP_DST_IGNORE = 0,
 871         ULP_SR_SYM_L3_IPV6_CMP_DST_NO = 0,
 872         ULP_SR_SYM_L3_IPV6_CMP_DST_YES = 1,
 873         ULP_SR_SYM_L4_HDR_VALID_IGNORE = 0,
 874         ULP_SR_SYM_L4_HDR_VALID_NO = 0,
 875         ULP_SR_SYM_L4_HDR_VALID_YES = 1,
 876         ULP_SR_SYM_L4_HDR_ERROR_IGNORE = 0,
 877         ULP_SR_SYM_L4_HDR_ERROR_NO = 0,
 878         ULP_SR_SYM_L4_HDR_ERROR_YES = 1,
 879         ULP_SR_SYM_L4_HDR_TYPE_IGNORE = 0,
 880         ULP_SR_SYM_L4_HDR_TYPE_TCP = 0,
 881         ULP_SR_SYM_L4_HDR_TYPE_UDP = 1,
 882         ULP_SR_SYM_L4_HDR_TYPE_ICMP = 2,
 883         ULP_SR_SYM_L4_HDR_TYPE_UPAR1 = 3,
 884         ULP_SR_SYM_L4_HDR_TYPE_UPAR2 = 4,
 885         ULP_SR_SYM_L4_HDR_TYPE_BTH_V1 = 5,
 886         ULP_SR_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0,
 887         ULP_SR_SYM_L4_HDR_IS_UDP_TCP_NO = 0,
 888         ULP_SR_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
 889         ULP_SR_SYM_POP_VLAN_NO = 0,
 890         ULP_SR_SYM_POP_VLAN_YES = 1,
 891         ULP_SR_SYM_DECAP_FUNC_NONE = 0,
 892         ULP_SR_SYM_DECAP_FUNC_THRU_TL2 = 3,
 893         ULP_SR_SYM_DECAP_FUNC_THRU_TL3 = 8,
 894         ULP_SR_SYM_DECAP_FUNC_THRU_TL4 = 9,
 895         ULP_SR_SYM_DECAP_FUNC_THRU_TUN = 10,
 896         ULP_SR_SYM_DECAP_FUNC_THRU_L2 = 11,
 897         ULP_SR_SYM_DECAP_FUNC_THRU_L3 = 12,
 898         ULP_SR_SYM_DECAP_FUNC_THRU_L4 = 13,
 899         ULP_SR_SYM_ECV_VALID_NO = 0,
 900         ULP_SR_SYM_ECV_VALID_YES = 1,
 901         ULP_SR_SYM_ECV_CUSTOM_EN_NO = 0,
 902         ULP_SR_SYM_ECV_CUSTOM_EN_YES = 1,
 903         ULP_SR_SYM_ECV_L2_EN_NO = 0,
 904         ULP_SR_SYM_ECV_L2_EN_YES = 1,
 905         ULP_SR_SYM_ECV_VTAG_TYPE_NOP = 0,
 906         ULP_SR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1,
 907         ULP_SR_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2,
 908         ULP_SR_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3,
 909         ULP_SR_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4,
 910         ULP_SR_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5,
 911         ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6,
 912         ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7,
 913         ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8,
 914         ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8,
 915         ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8,
 916         ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8,
 917         ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8,
 918         ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8,
 919         ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8,
 920         ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8,
 921         ULP_SR_SYM_ECV_L3_TYPE_NONE = 0,
 922         ULP_SR_SYM_ECV_L3_TYPE_IPV4 = 4,
 923         ULP_SR_SYM_ECV_L3_TYPE_IPV6 = 5,
 924         ULP_SR_SYM_ECV_L3_TYPE_MPLS_8847 = 6,
 925         ULP_SR_SYM_ECV_L3_TYPE_MPLS_8848 = 7,
 926         ULP_SR_SYM_ECV_L4_TYPE_NONE = 0,
 927         ULP_SR_SYM_ECV_L4_TYPE_UDP = 4,
 928         ULP_SR_SYM_ECV_L4_TYPE_UDP_CSUM = 5,
 929         ULP_SR_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6,
 930         ULP_SR_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7,
 931         ULP_SR_SYM_ECV_TUN_TYPE_NONE = 0,
 932         ULP_SR_SYM_ECV_TUN_TYPE_GENERIC = 1,
 933         ULP_SR_SYM_ECV_TUN_TYPE_VXLAN = 2,
 934         ULP_SR_SYM_ECV_TUN_TYPE_NGE = 3,
 935         ULP_SR_SYM_ECV_TUN_TYPE_NVGRE = 4,
 936         ULP_SR_SYM_ECV_TUN_TYPE_GRE = 5,
 937         ULP_SR_SYM_EEM_ACT_REC_INT = 0,
 938         ULP_SR_SYM_EEM_EXT_FLOW_CNTR = 1,
 939         ULP_SR_SYM_UC_ACT_REC = 0,
 940         ULP_SR_SYM_MC_ACT_REC = 1,
 941         ULP_SR_SYM_ACT_REC_DROP_YES = 1,
 942         ULP_SR_SYM_ACT_REC_DROP_NO = 0,
 943         ULP_SR_SYM_ACT_REC_POP_VLAN_YES = 1,
 944         ULP_SR_SYM_ACT_REC_POP_VLAN_NO = 0,
 945         ULP_SR_SYM_ACT_REC_METER_EN_YES = 1,
 946         ULP_SR_SYM_ACT_REC_METER_EN_NO = 0,
 947         ULP_SR_SYM_LOOPBACK_PORT = 16,
 948         ULP_SR_SYM_LOOPBACK_PARIF = 15,
 949         ULP_SR_SYM_EXT_EM_MAX_KEY_SIZE = 448,
 950         ULP_SR_SYM_MATCH_TYPE_EM = 0,
 951         ULP_SR_SYM_MATCH_TYPE_WM = 1,
 952         ULP_SR_SYM_IP_PROTO_ICMP = 1,
 953         ULP_SR_SYM_IP_PROTO_IGMP = 2,
 954         ULP_SR_SYM_IP_PROTO_IP_IN_IP = 4,
 955         ULP_SR_SYM_IP_PROTO_TCP = 6,
 956         ULP_SR_SYM_IP_PROTO_UDP = 17,
 957         ULP_SR_SYM_VF_FUNC_PARIF = 15,
 958         ULP_SR_SYM_NO = 0,
 959         ULP_SR_SYM_YES = 1,
 960         ULP_SR_SYM_RECYCLE_DST = 0x800
 961 };
 962
 963 enum bnxt_ulp_class_hid {
 964         BNXT_ULP_CLASS_HID_005c = 0x005c,
 965         BNXT_ULP_CLASS_HID_0003 = 0x0003,
 966         BNXT_ULP_CLASS_HID_0132 = 0x0132,
 967         BNXT_ULP_CLASS_HID_00e1 = 0x00e1,
 968         BNXT_ULP_CLASS_HID_0044 = 0x0044,
 969         BNXT_ULP_CLASS_HID_001b = 0x001b,
 970         BNXT_ULP_CLASS_HID_012a = 0x012a,
 971         BNXT_ULP_CLASS_HID_00f9 = 0x00f9,
 972         BNXT_ULP_CLASS_HID_018d = 0x018d,
 973         BNXT_ULP_CLASS_HID_00a7 = 0x00a7,
 974         BNXT_ULP_CLASS_HID_006f = 0x006f,
 975         BNXT_ULP_CLASS_HID_0181 = 0x0181,
 976         BNXT_ULP_CLASS_HID_0195 = 0x0195,
 977         BNXT_ULP_CLASS_HID_00bf = 0x00bf,
 978         BNXT_ULP_CLASS_HID_0077 = 0x0077,
 979         BNXT_ULP_CLASS_HID_0199 = 0x0199,
 980         BNXT_ULP_CLASS_HID_009a = 0x009a,
 981         BNXT_ULP_CLASS_HID_0192 = 0x0192,
 982         BNXT_ULP_CLASS_HID_01e2 = 0x01e2,
 983         BNXT_ULP_CLASS_HID_00fa = 0x00fa,
 984         BNXT_ULP_CLASS_HID_0165 = 0x0165,
 985         BNXT_ULP_CLASS_HID_0042 = 0x0042,
 986         BNXT_ULP_CLASS_HID_00cd = 0x00cd,
 987         BNXT_ULP_CLASS_HID_01aa = 0x01aa,
 988         BNXT_ULP_CLASS_HID_0178 = 0x0178,
 989         BNXT_ULP_CLASS_HID_0070 = 0x0070,
 990         BNXT_ULP_CLASS_HID_00f3 = 0x00f3,
 991         BNXT_ULP_CLASS_HID_01d8 = 0x01d8,
 992         BNXT_ULP_CLASS_HID_005b = 0x005b,
 993         BNXT_ULP_CLASS_HID_0153 = 0x0153,
 994         BNXT_ULP_CLASS_HID_01a3 = 0x01a3,
 995         BNXT_ULP_CLASS_HID_00bb = 0x00bb,
 996         BNXT_ULP_CLASS_HID_0082 = 0x0082,
 997         BNXT_ULP_CLASS_HID_018a = 0x018a,
 998         BNXT_ULP_CLASS_HID_01fa = 0x01fa,
 999         BNXT_ULP_CLASS_HID_00e2 = 0x00e2,
1000         BNXT_ULP_CLASS_HID_017d = 0x017d,
1001         BNXT_ULP_CLASS_HID_005a = 0x005a,
1002         BNXT_ULP_CLASS_HID_00d5 = 0x00d5,
1003         BNXT_ULP_CLASS_HID_01b2 = 0x01b2,
1004         BNXT_ULP_CLASS_HID_0160 = 0x0160,
1005         BNXT_ULP_CLASS_HID_0068 = 0x0068,
1006         BNXT_ULP_CLASS_HID_00eb = 0x00eb,
1007         BNXT_ULP_CLASS_HID_01c0 = 0x01c0,
1008         BNXT_ULP_CLASS_HID_0043 = 0x0043,
1009         BNXT_ULP_CLASS_HID_014b = 0x014b,
1010         BNXT_ULP_CLASS_HID_01bb = 0x01bb,
1011         BNXT_ULP_CLASS_HID_00a3 = 0x00a3,
1012         BNXT_ULP_CLASS_HID_00cb = 0x00cb,
1013         BNXT_ULP_CLASS_HID_00b4 = 0x00b4,
1014         BNXT_ULP_CLASS_HID_0013 = 0x0013,
1015         BNXT_ULP_CLASS_HID_001c = 0x001c,
1016         BNXT_ULP_CLASS_HID_017b = 0x017b,
1017         BNXT_ULP_CLASS_HID_0164 = 0x0164,
1018         BNXT_ULP_CLASS_HID_00c3 = 0x00c3,
1019         BNXT_ULP_CLASS_HID_00cc = 0x00cc,
1020         BNXT_ULP_CLASS_HID_01a5 = 0x01a5,
1021         BNXT_ULP_CLASS_HID_0196 = 0x0196,
1022         BNXT_ULP_CLASS_HID_010d = 0x010d,
1023         BNXT_ULP_CLASS_HID_00fe = 0x00fe,
1024         BNXT_ULP_CLASS_HID_0084 = 0x0084,
1025         BNXT_ULP_CLASS_HID_0046 = 0x0046,
1026         BNXT_ULP_CLASS_HID_01ec = 0x01ec,
1027         BNXT_ULP_CLASS_HID_01ae = 0x01ae,
1028         BNXT_ULP_CLASS_HID_00d3 = 0x00d3,
1029         BNXT_ULP_CLASS_HID_00ac = 0x00ac,
1030         BNXT_ULP_CLASS_HID_000b = 0x000b,
1031         BNXT_ULP_CLASS_HID_0004 = 0x0004,
1032         BNXT_ULP_CLASS_HID_0163 = 0x0163,
1033         BNXT_ULP_CLASS_HID_017c = 0x017c,
1034         BNXT_ULP_CLASS_HID_00db = 0x00db,
1035         BNXT_ULP_CLASS_HID_00d4 = 0x00d4,
1036         BNXT_ULP_CLASS_HID_01bd = 0x01bd,
1037         BNXT_ULP_CLASS_HID_018e = 0x018e,
1038         BNXT_ULP_CLASS_HID_0115 = 0x0115,
1039         BNXT_ULP_CLASS_HID_00e6 = 0x00e6,
1040         BNXT_ULP_CLASS_HID_009c = 0x009c,
1041         BNXT_ULP_CLASS_HID_005e = 0x005e,
1042         BNXT_ULP_CLASS_HID_01f4 = 0x01f4,
1043         BNXT_ULP_CLASS_HID_01b6 = 0x01b6
1044 };
1045
1046 enum bnxt_ulp_act_hid {
1047         BNXT_ULP_ACT_HID_0000 = 0x0000,
1048         BNXT_ULP_ACT_HID_0001 = 0x0001,
1049         BNXT_ULP_ACT_HID_0400 = 0x0400,
1050         BNXT_ULP_ACT_HID_0331 = 0x0331,
1051         BNXT_ULP_ACT_HID_0010 = 0x0010,
1052         BNXT_ULP_ACT_HID_0731 = 0x0731,
1053         BNXT_ULP_ACT_HID_0341 = 0x0341,
1054         BNXT_ULP_ACT_HID_0002 = 0x0002,
1055         BNXT_ULP_ACT_HID_0003 = 0x0003,
1056         BNXT_ULP_ACT_HID_0402 = 0x0402,
1057         BNXT_ULP_ACT_HID_0333 = 0x0333,
1058         BNXT_ULP_ACT_HID_0012 = 0x0012,
1059         BNXT_ULP_ACT_HID_0733 = 0x0733,
1060         BNXT_ULP_ACT_HID_0343 = 0x0343
1061 };
1062
1063 enum bnxt_ulp_df_tpl {
1064         BNXT_ULP_DF_TPL_PORT_TO_VS = 2,
1065         BNXT_ULP_DF_TPL_VS_TO_PORT = 3,
1066         BNXT_ULP_DF_TPL_VFREP_TO_VF = 4,
1067         BNXT_ULP_DF_TPL_VF_TO_VFREP = 5,
1068         BNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC = 6
1069 };
1070
1071 #endif