1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
4 #include "cn10k_ethdev.h"
5 #include "cn10k_rte_flow.h"
10 nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
12 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
13 struct rte_eth_dev_data *data = eth_dev->data;
14 struct rte_eth_conf *conf = &data->dev_conf;
15 struct rte_eth_rxmode *rxmode = &conf->rxmode;
18 if (rxmode->mq_mode == RTE_ETH_MQ_RX_RSS &&
19 (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_RSS_HASH))
20 flags |= NIX_RX_OFFLOAD_RSS_F;
22 if (dev->rx_offloads &
23 (RTE_ETH_RX_OFFLOAD_TCP_CKSUM | RTE_ETH_RX_OFFLOAD_UDP_CKSUM))
24 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
26 if (dev->rx_offloads &
27 (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM))
28 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
30 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER)
31 flags |= NIX_RX_MULTI_SEG_F;
33 if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP))
34 flags |= NIX_RX_OFFLOAD_TSTAMP_F;
36 if (!dev->ptype_disable)
37 flags |= NIX_RX_OFFLOAD_PTYPE_F;
39 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)
40 flags |= NIX_RX_OFFLOAD_SECURITY_F;
46 nix_tx_offload_flags(struct rte_eth_dev *eth_dev)
48 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
49 uint64_t conf = dev->tx_offloads;
52 /* Fastpath is dependent on these enums */
53 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_TCP_CKSUM != (1ULL << 52));
54 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_SCTP_CKSUM != (2ULL << 52));
55 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_UDP_CKSUM != (3ULL << 52));
56 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_IP_CKSUM != (1ULL << 54));
57 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_IPV4 != (1ULL << 55));
58 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_OUTER_IP_CKSUM != (1ULL << 58));
59 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_OUTER_IPV4 != (1ULL << 59));
60 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_OUTER_IPV6 != (1ULL << 60));
61 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_OUTER_UDP_CKSUM != (1ULL << 41));
62 RTE_BUILD_BUG_ON(RTE_MBUF_L2_LEN_BITS != 7);
63 RTE_BUILD_BUG_ON(RTE_MBUF_L3_LEN_BITS != 9);
64 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL2_LEN_BITS != 7);
65 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL3_LEN_BITS != 9);
66 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) !=
67 offsetof(struct rte_mbuf, buf_iova) + 8);
68 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
69 offsetof(struct rte_mbuf, buf_iova) + 16);
70 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
71 offsetof(struct rte_mbuf, ol_flags) + 12);
72 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, tx_offload) !=
73 offsetof(struct rte_mbuf, pool) + 2 * sizeof(void *));
75 if (conf & RTE_ETH_TX_OFFLOAD_VLAN_INSERT ||
76 conf & RTE_ETH_TX_OFFLOAD_QINQ_INSERT)
77 flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F;
79 if (conf & RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
80 conf & RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM)
81 flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F;
83 if (conf & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM ||
84 conf & RTE_ETH_TX_OFFLOAD_TCP_CKSUM ||
85 conf & RTE_ETH_TX_OFFLOAD_UDP_CKSUM || conf & RTE_ETH_TX_OFFLOAD_SCTP_CKSUM)
86 flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F;
88 if (!(conf & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE))
89 flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F;
91 if (conf & RTE_ETH_TX_OFFLOAD_MULTI_SEGS)
92 flags |= NIX_TX_MULTI_SEG_F;
94 /* Enable Inner checksum for TSO */
95 if (conf & RTE_ETH_TX_OFFLOAD_TCP_TSO)
96 flags |= (NIX_TX_OFFLOAD_TSO_F | NIX_TX_OFFLOAD_L3_L4_CSUM_F);
98 /* Enable Inner and Outer checksum for Tunnel TSO */
99 if (conf & (RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
100 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO | RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO))
101 flags |= (NIX_TX_OFFLOAD_TSO_F | NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |
102 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
104 if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP))
105 flags |= NIX_TX_OFFLOAD_TSTAMP_F;
107 if (conf & RTE_ETH_TX_OFFLOAD_SECURITY)
108 flags |= NIX_TX_OFFLOAD_SECURITY_F;
114 cn10k_nix_ptypes_set(struct rte_eth_dev *eth_dev, uint32_t ptype_mask)
116 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
119 dev->rx_offload_flags |= NIX_RX_OFFLOAD_PTYPE_F;
120 dev->ptype_disable = 0;
122 dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_PTYPE_F;
123 dev->ptype_disable = 1;
126 cn10k_eth_set_rx_function(eth_dev);
131 nix_form_default_desc(struct cnxk_eth_dev *dev, struct cn10k_eth_txq *txq,
134 struct nix_send_ext_s *send_hdr_ext;
135 union nix_send_hdr_w0_u send_hdr_w0;
136 struct nix_send_mem_s *send_mem;
137 union nix_send_sg_s sg_w0;
141 /* Initialize the fields based on basic single segment packet */
142 memset(&txq->cmd, 0, sizeof(txq->cmd));
146 if (dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
147 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
148 send_hdr_w0.sizem1 = 2;
150 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[0];
151 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
152 if (dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
153 /* Default: one seg packet would have:
154 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
157 send_hdr_w0.sizem1 = 3;
158 send_hdr_ext->w0.tstmp = 1;
160 /* To calculate the offset for send_mem,
161 * send_hdr->w0.sizem1 * 2
163 send_mem = (struct nix_send_mem_s *)(txq->cmd + 2);
164 send_mem->w0.subdc = NIX_SUBDC_MEM;
165 send_mem->w0.alg = NIX_SENDMEMALG_SETTSTMP;
166 send_mem->addr = dev->tstamp.tx_tstamp_iova;
169 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
170 send_hdr_w0.sizem1 = 1;
173 send_hdr_w0.sq = qid;
174 sg_w0.subdc = NIX_SUBDC_SG;
176 sg_w0.ld_type = NIX_SENDLDTYPE_LDD;
178 txq->send_hdr_w0 = send_hdr_w0.u;
179 txq->sg_w0 = sg_w0.u;
185 cn10k_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
186 uint16_t nb_desc, unsigned int socket,
187 const struct rte_eth_txconf *tx_conf)
189 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
190 struct roc_nix *nix = &dev->nix;
191 struct roc_cpt_lf *inl_lf;
192 struct cn10k_eth_txq *txq;
193 struct roc_nix_sq *sq;
197 RTE_SET_USED(socket);
199 /* Common Tx queue setup */
200 rc = cnxk_nix_tx_queue_setup(eth_dev, qid, nb_desc,
201 sizeof(struct cn10k_eth_txq), tx_conf);
206 /* Update fast path queue */
207 txq = eth_dev->data->tx_queues[qid];
208 txq->fc_mem = sq->fc;
209 /* Store lmt base in tx queue for easy access */
210 txq->lmt_base = nix->lmt_base;
211 txq->io_addr = sq->io_addr;
212 txq->nb_sqb_bufs_adj = sq->nb_sqb_bufs_adj;
213 txq->sqes_per_sqb_log2 = sq->sqes_per_sqb_log2;
215 /* Fetch CPT LF info for outbound if present */
216 if (dev->outb.lf_base) {
217 crypto_qid = qid % dev->outb.nb_crypto_qs;
218 inl_lf = dev->outb.lf_base + crypto_qid;
220 txq->cpt_io_addr = inl_lf->io_addr;
221 txq->cpt_fc = inl_lf->fc_addr;
222 txq->cpt_desc = inl_lf->nb_desc * 0.7;
223 txq->sa_base = (uint64_t)dev->outb.sa_base;
224 txq->sa_base |= eth_dev->data->port_id;
225 PLT_STATIC_ASSERT(ROC_NIX_INL_SA_BASE_ALIGN == BIT_ULL(16));
228 nix_form_default_desc(dev, txq, qid);
229 txq->lso_tun_fmt = dev->lso_tun_fmt;
234 cn10k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
235 uint16_t nb_desc, unsigned int socket,
236 const struct rte_eth_rxconf *rx_conf,
237 struct rte_mempool *mp)
239 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
240 struct cnxk_eth_rxq_sp *rxq_sp;
241 struct cn10k_eth_rxq *rxq;
242 struct roc_nix_rq *rq;
243 struct roc_nix_cq *cq;
246 RTE_SET_USED(socket);
248 /* CQ Errata needs min 4K ring */
249 if (dev->cq_min_4k && nb_desc < 4096)
252 /* Common Rx queue setup */
253 rc = cnxk_nix_rx_queue_setup(eth_dev, qid, nb_desc,
254 sizeof(struct cn10k_eth_rxq), rx_conf, mp);
261 /* Update fast path queue */
262 rxq = eth_dev->data->rx_queues[qid];
264 rxq->desc = (uintptr_t)cq->desc_base;
265 rxq->cq_door = cq->door;
266 rxq->cq_status = cq->status;
267 rxq->wdata = cq->wdata;
268 rxq->head = cq->head;
269 rxq->qmask = cq->qmask;
270 rxq->tstamp = &dev->tstamp;
272 /* Data offset from data to start of mbuf is first_skip */
273 rxq->data_off = rq->first_skip;
274 rxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev);
276 /* Setup security related info */
277 if (dev->rx_offload_flags & NIX_RX_OFFLOAD_SECURITY_F) {
278 rxq->lmt_base = dev->nix.lmt_base;
279 rxq->sa_base = roc_nix_inl_inb_sa_base_get(&dev->nix,
282 rxq_sp = cnxk_eth_rxq_to_sp(rxq);
283 rxq->aura_handle = rxq_sp->qconf.mp->pool_id;
286 rxq->lookup_mem = cnxk_nix_fastpath_lookup_mem_get();
291 cn10k_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
293 struct cn10k_eth_txq *txq = eth_dev->data->tx_queues[qidx];
296 rc = cnxk_nix_tx_queue_stop(eth_dev, qidx);
300 /* Clear fc cache pkts to trigger worker stop */
301 txq->fc_cache_pkts = 0;
306 cn10k_nix_configure(struct rte_eth_dev *eth_dev)
308 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
311 /* Common nix configure */
312 rc = cnxk_nix_configure(eth_dev);
316 /* Update offload flags */
317 dev->rx_offload_flags = nix_rx_offload_flags(eth_dev);
318 dev->tx_offload_flags = nix_tx_offload_flags(eth_dev);
320 plt_nix_dbg("Configured port%d platform specific rx_offload_flags=%x"
321 " tx_offload_flags=0x%x",
322 eth_dev->data->port_id, dev->rx_offload_flags,
323 dev->tx_offload_flags);
327 /* Function to enable ptp config for VFs */
329 nix_ptp_enable_vf(struct rte_eth_dev *eth_dev)
331 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
333 if (nix_recalc_mtu(eth_dev))
334 plt_err("Failed to set MTU size for ptp");
336 dev->rx_offload_flags |= NIX_RX_OFFLOAD_TSTAMP_F;
338 /* Setting up the function pointers as per new offload flags */
339 cn10k_eth_set_rx_function(eth_dev);
340 cn10k_eth_set_tx_function(eth_dev);
344 nix_ptp_vf_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
346 struct cn10k_eth_rxq *rxq = queue;
347 struct cnxk_eth_rxq_sp *rxq_sp;
348 struct rte_eth_dev *eth_dev;
353 rxq_sp = cnxk_eth_rxq_to_sp(rxq);
354 eth_dev = rxq_sp->dev->eth_dev;
355 nix_ptp_enable_vf(eth_dev);
361 cn10k_nix_ptp_info_update_cb(struct roc_nix *nix, bool ptp_en)
363 struct cnxk_eth_dev *dev = (struct cnxk_eth_dev *)nix;
364 struct rte_eth_dev *eth_dev;
365 struct cn10k_eth_rxq *rxq;
371 eth_dev = dev->eth_dev;
375 dev->ptp_en = ptp_en;
377 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
378 rxq = eth_dev->data->rx_queues[i];
379 rxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev);
382 if (roc_nix_is_vf_or_sdp(nix) && !(roc_nix_is_sdp(nix)) &&
383 !(roc_nix_is_lbk(nix))) {
384 /* In case of VF, setting of MTU cannot be done directly in this
385 * function as this is running as part of MBOX request(PF->VF)
386 * and MTU setting also requires MBOX message to be
389 eth_dev->rx_pkt_burst = nix_ptp_vf_burst;
397 cn10k_nix_timesync_enable(struct rte_eth_dev *eth_dev)
399 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
402 rc = cnxk_nix_timesync_enable(eth_dev);
406 dev->rx_offload_flags |= NIX_RX_OFFLOAD_TSTAMP_F;
407 dev->tx_offload_flags |= NIX_TX_OFFLOAD_TSTAMP_F;
409 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
410 nix_form_default_desc(dev, eth_dev->data->tx_queues[i], i);
412 /* Setting up the rx[tx]_offload_flags due to change
413 * in rx[tx]_offloads.
415 cn10k_eth_set_rx_function(eth_dev);
416 cn10k_eth_set_tx_function(eth_dev);
421 cn10k_nix_timesync_disable(struct rte_eth_dev *eth_dev)
423 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
426 rc = cnxk_nix_timesync_disable(eth_dev);
430 dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_TSTAMP_F;
431 dev->tx_offload_flags &= ~NIX_TX_OFFLOAD_TSTAMP_F;
433 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
434 nix_form_default_desc(dev, eth_dev->data->tx_queues[i], i);
436 /* Setting up the rx[tx]_offload_flags due to change
437 * in rx[tx]_offloads.
439 cn10k_eth_set_rx_function(eth_dev);
440 cn10k_eth_set_tx_function(eth_dev);
445 cn10k_nix_dev_start(struct rte_eth_dev *eth_dev)
447 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
448 struct roc_nix *nix = &dev->nix;
451 /* Common eth dev start */
452 rc = cnxk_nix_dev_start(eth_dev);
456 /* Update VF about data off shifted by 8 bytes if PTP already
457 * enabled in PF owning this VF
459 if (dev->ptp_en && (!roc_nix_is_pf(nix) && (!roc_nix_is_sdp(nix))))
460 nix_ptp_enable_vf(eth_dev);
462 /* Setting up the rx[tx]_offload_flags due to change
463 * in rx[tx]_offloads.
465 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
466 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
468 cn10k_eth_set_tx_function(eth_dev);
469 cn10k_eth_set_rx_function(eth_dev);
473 /* Update platform specific eth dev ops */
475 nix_eth_dev_ops_override(void)
477 static int init_once;
483 /* Update platform specific ops */
484 cnxk_eth_dev_ops.dev_configure = cn10k_nix_configure;
485 cnxk_eth_dev_ops.tx_queue_setup = cn10k_nix_tx_queue_setup;
486 cnxk_eth_dev_ops.rx_queue_setup = cn10k_nix_rx_queue_setup;
487 cnxk_eth_dev_ops.tx_queue_stop = cn10k_nix_tx_queue_stop;
488 cnxk_eth_dev_ops.dev_start = cn10k_nix_dev_start;
489 cnxk_eth_dev_ops.dev_ptypes_set = cn10k_nix_ptypes_set;
490 cnxk_eth_dev_ops.timesync_enable = cn10k_nix_timesync_enable;
491 cnxk_eth_dev_ops.timesync_disable = cn10k_nix_timesync_disable;
495 npc_flow_ops_override(void)
497 static int init_once;
503 /* Update platform specific ops */
504 cnxk_flow_ops.create = cn10k_flow_create;
505 cnxk_flow_ops.destroy = cn10k_flow_destroy;
509 cn10k_nix_remove(struct rte_pci_device *pci_dev)
511 return cnxk_nix_remove(pci_dev);
515 cn10k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
517 struct rte_eth_dev *eth_dev;
518 struct cnxk_eth_dev *dev;
521 if (RTE_CACHE_LINE_SIZE != 64) {
522 plt_err("Driver not compiled for CN10K");
528 plt_err("Failed to initialize platform model, rc=%d", rc);
532 nix_eth_dev_ops_override();
533 npc_flow_ops_override();
535 cn10k_eth_sec_ops_override();
538 rc = cnxk_nix_probe(pci_drv, pci_dev);
542 /* Find eth dev allocated */
543 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
547 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
548 /* Setup callbacks for secondary process */
549 cn10k_eth_set_tx_function(eth_dev);
550 cn10k_eth_set_rx_function(eth_dev);
554 dev = cnxk_eth_pmd_priv(eth_dev);
556 /* DROP_RE is not supported with inline IPSec for CN10K A0 */
557 if (roc_model_is_cn10ka_a0() || roc_model_is_cnf10ka_a0() ||
558 roc_model_is_cnf10kb_a0())
559 dev->ipsecd_drop_re_dis = 1;
561 /* Register up msg callbacks for PTP information */
562 roc_nix_ptp_info_cb_register(&dev->nix, cn10k_nix_ptp_info_update_cb);
567 static const struct rte_pci_id cn10k_pci_nix_map[] = {
568 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_PF),
569 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_PF),
570 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_PF),
571 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_VF),
572 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_VF),
573 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_VF),
574 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_AF_VF),
575 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_AF_VF),
576 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_AF_VF),
582 static struct rte_pci_driver cn10k_pci_nix = {
583 .id_table = cn10k_pci_nix_map,
584 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
585 RTE_PCI_DRV_INTR_LSC,
586 .probe = cn10k_nix_probe,
587 .remove = cn10k_nix_remove,
590 RTE_PMD_REGISTER_PCI(net_cn10k, cn10k_pci_nix);
591 RTE_PMD_REGISTER_PCI_TABLE(net_cn10k, cn10k_pci_nix_map);
592 RTE_PMD_REGISTER_KMOD_DEP(net_cn10k, "vfio-pci");