1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
4 #include "cn10k_ethdev.h"
5 #include "cn10k_rte_flow.h"
10 nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
12 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
13 struct rte_eth_dev_data *data = eth_dev->data;
14 struct rte_eth_conf *conf = &data->dev_conf;
15 struct rte_eth_rxmode *rxmode = &conf->rxmode;
18 if (rxmode->mq_mode == ETH_MQ_RX_RSS &&
19 (dev->rx_offloads & DEV_RX_OFFLOAD_RSS_HASH))
20 flags |= NIX_RX_OFFLOAD_RSS_F;
22 if (dev->rx_offloads &
23 (DEV_RX_OFFLOAD_TCP_CKSUM | DEV_RX_OFFLOAD_UDP_CKSUM))
24 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
26 if (dev->rx_offloads &
27 (DEV_RX_OFFLOAD_IPV4_CKSUM | DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM))
28 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
30 if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
31 flags |= NIX_RX_MULTI_SEG_F;
33 if (!dev->ptype_disable)
34 flags |= NIX_RX_OFFLOAD_PTYPE_F;
40 nix_tx_offload_flags(struct rte_eth_dev *eth_dev)
42 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
43 uint64_t conf = dev->tx_offloads;
46 /* Fastpath is dependent on these enums */
47 RTE_BUILD_BUG_ON(PKT_TX_TCP_CKSUM != (1ULL << 52));
48 RTE_BUILD_BUG_ON(PKT_TX_SCTP_CKSUM != (2ULL << 52));
49 RTE_BUILD_BUG_ON(PKT_TX_UDP_CKSUM != (3ULL << 52));
50 RTE_BUILD_BUG_ON(PKT_TX_IP_CKSUM != (1ULL << 54));
51 RTE_BUILD_BUG_ON(PKT_TX_IPV4 != (1ULL << 55));
52 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IP_CKSUM != (1ULL << 58));
53 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV4 != (1ULL << 59));
54 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV6 != (1ULL << 60));
55 RTE_BUILD_BUG_ON(PKT_TX_OUTER_UDP_CKSUM != (1ULL << 41));
56 RTE_BUILD_BUG_ON(RTE_MBUF_L2_LEN_BITS != 7);
57 RTE_BUILD_BUG_ON(RTE_MBUF_L3_LEN_BITS != 9);
58 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL2_LEN_BITS != 7);
59 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL3_LEN_BITS != 9);
60 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) !=
61 offsetof(struct rte_mbuf, buf_iova) + 8);
62 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
63 offsetof(struct rte_mbuf, buf_iova) + 16);
64 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
65 offsetof(struct rte_mbuf, ol_flags) + 12);
66 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, tx_offload) !=
67 offsetof(struct rte_mbuf, pool) + 2 * sizeof(void *));
69 if (conf & DEV_TX_OFFLOAD_VLAN_INSERT ||
70 conf & DEV_TX_OFFLOAD_QINQ_INSERT)
71 flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F;
73 if (conf & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
74 conf & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
75 flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F;
77 if (conf & DEV_TX_OFFLOAD_IPV4_CKSUM ||
78 conf & DEV_TX_OFFLOAD_TCP_CKSUM ||
79 conf & DEV_TX_OFFLOAD_UDP_CKSUM || conf & DEV_TX_OFFLOAD_SCTP_CKSUM)
80 flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F;
82 if (!(conf & DEV_TX_OFFLOAD_MBUF_FAST_FREE))
83 flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F;
85 if (conf & DEV_TX_OFFLOAD_MULTI_SEGS)
86 flags |= NIX_TX_MULTI_SEG_F;
88 /* Enable Inner checksum for TSO */
89 if (conf & DEV_TX_OFFLOAD_TCP_TSO)
90 flags |= (NIX_TX_OFFLOAD_TSO_F | NIX_TX_OFFLOAD_L3_L4_CSUM_F);
92 /* Enable Inner and Outer checksum for Tunnel TSO */
93 if (conf & (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
94 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | DEV_TX_OFFLOAD_GRE_TNL_TSO))
95 flags |= (NIX_TX_OFFLOAD_TSO_F | NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |
96 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
102 cn10k_nix_ptypes_set(struct rte_eth_dev *eth_dev, uint32_t ptype_mask)
104 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
107 dev->rx_offload_flags |= NIX_RX_OFFLOAD_PTYPE_F;
108 dev->ptype_disable = 0;
110 dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_PTYPE_F;
111 dev->ptype_disable = 1;
114 cn10k_eth_set_rx_function(eth_dev);
119 nix_form_default_desc(struct cnxk_eth_dev *dev, struct cn10k_eth_txq *txq,
122 struct nix_send_ext_s *send_hdr_ext;
123 union nix_send_hdr_w0_u send_hdr_w0;
124 union nix_send_sg_s sg_w0;
128 /* Initialize the fields based on basic single segment packet */
129 memset(&txq->cmd, 0, sizeof(txq->cmd));
133 if (dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
134 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
135 send_hdr_w0.sizem1 = 2;
137 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[0];
138 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
140 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
141 send_hdr_w0.sizem1 = 1;
144 send_hdr_w0.sq = qid;
145 sg_w0.subdc = NIX_SUBDC_SG;
147 sg_w0.ld_type = NIX_SENDLDTYPE_LDD;
149 txq->send_hdr_w0 = send_hdr_w0.u;
150 txq->sg_w0 = sg_w0.u;
156 cn10k_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
157 uint16_t nb_desc, unsigned int socket,
158 const struct rte_eth_txconf *tx_conf)
160 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
161 struct cn10k_eth_txq *txq;
162 struct roc_nix_sq *sq;
165 RTE_SET_USED(socket);
167 /* Common Tx queue setup */
168 rc = cnxk_nix_tx_queue_setup(eth_dev, qid, nb_desc,
169 sizeof(struct cn10k_eth_txq), tx_conf);
174 /* Update fast path queue */
175 txq = eth_dev->data->tx_queues[qid];
176 txq->fc_mem = sq->fc;
177 /* Store lmt base in tx queue for easy access */
178 txq->lmt_base = dev->nix.lmt_base;
179 txq->io_addr = sq->io_addr;
180 txq->nb_sqb_bufs_adj = sq->nb_sqb_bufs_adj;
181 txq->sqes_per_sqb_log2 = sq->sqes_per_sqb_log2;
183 nix_form_default_desc(dev, txq, qid);
184 txq->lso_tun_fmt = dev->lso_tun_fmt;
189 cn10k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
190 uint16_t nb_desc, unsigned int socket,
191 const struct rte_eth_rxconf *rx_conf,
192 struct rte_mempool *mp)
194 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
195 struct cn10k_eth_rxq *rxq;
196 struct roc_nix_rq *rq;
197 struct roc_nix_cq *cq;
200 RTE_SET_USED(socket);
202 /* CQ Errata needs min 4K ring */
203 if (dev->cq_min_4k && nb_desc < 4096)
206 /* Common Rx queue setup */
207 rc = cnxk_nix_rx_queue_setup(eth_dev, qid, nb_desc,
208 sizeof(struct cn10k_eth_rxq), rx_conf, mp);
215 /* Update fast path queue */
216 rxq = eth_dev->data->rx_queues[qid];
218 rxq->desc = (uintptr_t)cq->desc_base;
219 rxq->cq_door = cq->door;
220 rxq->cq_status = cq->status;
221 rxq->wdata = cq->wdata;
222 rxq->head = cq->head;
223 rxq->qmask = cq->qmask;
225 /* Data offset from data to start of mbuf is first_skip */
226 rxq->data_off = rq->first_skip;
227 rxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev);
230 rxq->lookup_mem = cnxk_nix_fastpath_lookup_mem_get();
235 cn10k_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
237 struct cn10k_eth_txq *txq = eth_dev->data->tx_queues[qidx];
240 rc = cnxk_nix_tx_queue_stop(eth_dev, qidx);
244 /* Clear fc cache pkts to trigger worker stop */
245 txq->fc_cache_pkts = 0;
250 cn10k_nix_configure(struct rte_eth_dev *eth_dev)
252 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
255 /* Common nix configure */
256 rc = cnxk_nix_configure(eth_dev);
260 /* Update offload flags */
261 dev->rx_offload_flags = nix_rx_offload_flags(eth_dev);
262 dev->tx_offload_flags = nix_tx_offload_flags(eth_dev);
264 plt_nix_dbg("Configured port%d platform specific rx_offload_flags=%x"
265 " tx_offload_flags=0x%x",
266 eth_dev->data->port_id, dev->rx_offload_flags,
267 dev->tx_offload_flags);
271 /* Function to enable ptp config for VFs */
273 nix_ptp_enable_vf(struct rte_eth_dev *eth_dev)
275 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
277 if (nix_recalc_mtu(eth_dev))
278 plt_err("Failed to set MTU size for ptp");
280 dev->scalar_ena = true;
281 dev->rx_offload_flags |= NIX_RX_OFFLOAD_TSTAMP_F;
283 /* Setting up the function pointers as per new offload flags */
284 cn10k_eth_set_rx_function(eth_dev);
285 cn10k_eth_set_tx_function(eth_dev);
289 nix_ptp_vf_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
291 struct cn10k_eth_rxq *rxq = queue;
292 struct cnxk_eth_rxq_sp *rxq_sp;
293 struct rte_eth_dev *eth_dev;
298 rxq_sp = cnxk_eth_rxq_to_sp(rxq);
299 eth_dev = rxq_sp->dev->eth_dev;
300 nix_ptp_enable_vf(eth_dev);
306 cn10k_nix_ptp_info_update_cb(struct roc_nix *nix, bool ptp_en)
308 struct cnxk_eth_dev *dev = (struct cnxk_eth_dev *)nix;
309 struct rte_eth_dev *eth_dev;
310 struct cn10k_eth_rxq *rxq;
316 eth_dev = dev->eth_dev;
320 dev->ptp_en = ptp_en;
322 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
323 rxq = eth_dev->data->rx_queues[i];
324 rxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev);
327 if (roc_nix_is_vf_or_sdp(nix) && !(roc_nix_is_sdp(nix)) &&
328 !(roc_nix_is_lbk(nix))) {
329 /* In case of VF, setting of MTU cannot be done directly in this
330 * function as this is running as part of MBOX request(PF->VF)
331 * and MTU setting also requires MBOX message to be
334 eth_dev->rx_pkt_burst = nix_ptp_vf_burst;
342 cn10k_nix_dev_start(struct rte_eth_dev *eth_dev)
344 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
347 /* Common eth dev start */
348 rc = cnxk_nix_dev_start(eth_dev);
352 /* Setting up the rx[tx]_offload_flags due to change
353 * in rx[tx]_offloads.
355 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
356 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
358 cn10k_eth_set_tx_function(eth_dev);
359 cn10k_eth_set_rx_function(eth_dev);
363 /* Update platform specific eth dev ops */
365 nix_eth_dev_ops_override(void)
367 static int init_once;
373 /* Update platform specific ops */
374 cnxk_eth_dev_ops.dev_configure = cn10k_nix_configure;
375 cnxk_eth_dev_ops.tx_queue_setup = cn10k_nix_tx_queue_setup;
376 cnxk_eth_dev_ops.rx_queue_setup = cn10k_nix_rx_queue_setup;
377 cnxk_eth_dev_ops.tx_queue_stop = cn10k_nix_tx_queue_stop;
378 cnxk_eth_dev_ops.dev_start = cn10k_nix_dev_start;
379 cnxk_eth_dev_ops.dev_ptypes_set = cn10k_nix_ptypes_set;
383 npc_flow_ops_override(void)
385 static int init_once;
391 /* Update platform specific ops */
392 cnxk_flow_ops.create = cn10k_flow_create;
393 cnxk_flow_ops.destroy = cn10k_flow_destroy;
397 cn10k_nix_remove(struct rte_pci_device *pci_dev)
399 return cnxk_nix_remove(pci_dev);
403 cn10k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
405 struct rte_eth_dev *eth_dev;
406 struct cnxk_eth_dev *dev;
409 if (RTE_CACHE_LINE_SIZE != 64) {
410 plt_err("Driver not compiled for CN10K");
416 plt_err("Failed to initialize platform model, rc=%d", rc);
420 nix_eth_dev_ops_override();
421 npc_flow_ops_override();
424 rc = cnxk_nix_probe(pci_drv, pci_dev);
428 /* Find eth dev allocated */
429 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
433 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
434 /* Setup callbacks for secondary process */
435 cn10k_eth_set_tx_function(eth_dev);
436 cn10k_eth_set_rx_function(eth_dev);
440 dev = cnxk_eth_pmd_priv(eth_dev);
442 /* Register up msg callbacks for PTP information */
443 roc_nix_ptp_info_cb_register(&dev->nix, cn10k_nix_ptp_info_update_cb);
448 static const struct rte_pci_id cn10k_pci_nix_map[] = {
449 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_PF),
450 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_PF),
451 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_VF),
452 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_VF),
453 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_AF_VF),
454 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_AF_VF),
460 static struct rte_pci_driver cn10k_pci_nix = {
461 .id_table = cn10k_pci_nix_map,
462 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
463 RTE_PCI_DRV_INTR_LSC,
464 .probe = cn10k_nix_probe,
465 .remove = cn10k_nix_remove,
468 RTE_PMD_REGISTER_PCI(net_cn10k, cn10k_pci_nix);
469 RTE_PMD_REGISTER_PCI_TABLE(net_cn10k, cn10k_pci_nix_map);
470 RTE_PMD_REGISTER_KMOD_DEP(net_cn10k, "vfio-pci");