drivers/net/cnxk/cn10k_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4 #include "cn10k_ethdev.h"
   5 #include "cn10k_rx.h"
   6 #include "cn10k_tx.h"
   7
   8 static int
   9 cn10k_nix_ptypes_set(struct rte_eth_dev *eth_dev, uint32_t ptype_mask)
  10 {
  11         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
  12
  13         if (ptype_mask) {
  14                 dev->rx_offload_flags |= NIX_RX_OFFLOAD_PTYPE_F;
  15                 dev->ptype_disable = 0;
  16         } else {
  17                 dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_PTYPE_F;
  18                 dev->ptype_disable = 1;
  19         }
  20
  21         return 0;
  22 }
  23
  24 static void
  25 nix_form_default_desc(struct cnxk_eth_dev *dev, struct cn10k_eth_txq *txq,
  26                       uint16_t qid)
  27 {
  28         struct nix_send_ext_s *send_hdr_ext;
  29         union nix_send_hdr_w0_u send_hdr_w0;
  30         union nix_send_sg_s sg_w0;
  31
  32         RTE_SET_USED(dev);
  33
  34         /* Initialize the fields based on basic single segment packet */
  35         memset(&txq->cmd, 0, sizeof(txq->cmd));
  36         send_hdr_w0.u = 0;
  37         sg_w0.u = 0;
  38
  39         if (dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
  40                 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
  41                 send_hdr_w0.sizem1 = 2;
  42
  43                 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[0];
  44                 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
  45         } else {
  46                 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
  47                 send_hdr_w0.sizem1 = 1;
  48         }
  49
  50         send_hdr_w0.sq = qid;
  51         sg_w0.subdc = NIX_SUBDC_SG;
  52         sg_w0.segs = 1;
  53         sg_w0.ld_type = NIX_SENDLDTYPE_LDD;
  54
  55         txq->send_hdr_w0 = send_hdr_w0.u;
  56         txq->sg_w0 = sg_w0.u;
  57
  58         rte_wmb();
  59 }
  60
  61 static int
  62 cn10k_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
  63                          uint16_t nb_desc, unsigned int socket,
  64                          const struct rte_eth_txconf *tx_conf)
  65 {
  66         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
  67         struct cn10k_eth_txq *txq;
  68         struct roc_nix_sq *sq;
  69         int rc;
  70
  71         RTE_SET_USED(socket);
  72
  73         /* Common Tx queue setup */
  74         rc = cnxk_nix_tx_queue_setup(eth_dev, qid, nb_desc,
  75                                      sizeof(struct cn10k_eth_txq), tx_conf);
  76         if (rc)
  77                 return rc;
  78
  79         sq = &dev->sqs[qid];
  80         /* Update fast path queue */
  81         txq = eth_dev->data->tx_queues[qid];
  82         txq->fc_mem = sq->fc;
  83         /* Store lmt base in tx queue for easy access */
  84         txq->lmt_base = dev->nix.lmt_base;
  85         txq->io_addr = sq->io_addr;
  86         txq->nb_sqb_bufs_adj = sq->nb_sqb_bufs_adj;
  87         txq->sqes_per_sqb_log2 = sq->sqes_per_sqb_log2;
  88
  89         nix_form_default_desc(dev, txq, qid);
  90         txq->lso_tun_fmt = dev->lso_tun_fmt;
  91         return 0;
  92 }
  93
  94 static int
  95 cn10k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
  96                          uint16_t nb_desc, unsigned int socket,
  97                          const struct rte_eth_rxconf *rx_conf,
  98                          struct rte_mempool *mp)
  99 {
 100         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 101         struct cn10k_eth_rxq *rxq;
 102         struct roc_nix_rq *rq;
 103         struct roc_nix_cq *cq;
 104         int rc;
 105
 106         RTE_SET_USED(socket);
 107
 108         /* CQ Errata needs min 4K ring */
 109         if (dev->cq_min_4k && nb_desc < 4096)
 110                 nb_desc = 4096;
 111
 112         /* Common Rx queue setup */
 113         rc = cnxk_nix_rx_queue_setup(eth_dev, qid, nb_desc,
 114                                      sizeof(struct cn10k_eth_rxq), rx_conf, mp);
 115         if (rc)
 116                 return rc;
 117
 118         rq = &dev->rqs[qid];
 119         cq = &dev->cqs[qid];
 120
 121         /* Update fast path queue */
 122         rxq = eth_dev->data->rx_queues[qid];
 123         rxq->rq = qid;
 124         rxq->desc = (uintptr_t)cq->desc_base;
 125         rxq->cq_door = cq->door;
 126         rxq->cq_status = cq->status;
 127         rxq->wdata = cq->wdata;
 128         rxq->head = cq->head;
 129         rxq->qmask = cq->qmask;
 130
 131         /* Data offset from data to start of mbuf is first_skip */
 132         rxq->data_off = rq->first_skip;
 133         rxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev);
 134
 135         /* Lookup mem */
 136         rxq->lookup_mem = cnxk_nix_fastpath_lookup_mem_get();
 137         return 0;
 138 }
 139
 140 static int
 141 cn10k_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
 142 {
 143         struct cn10k_eth_txq *txq = eth_dev->data->tx_queues[qidx];
 144         int rc;
 145
 146         rc = cnxk_nix_tx_queue_stop(eth_dev, qidx);
 147         if (rc)
 148                 return rc;
 149
 150         /* Clear fc cache pkts to trigger worker stop */
 151         txq->fc_cache_pkts = 0;
 152         return 0;
 153 }
 154
 155 static int
 156 cn10k_nix_configure(struct rte_eth_dev *eth_dev)
 157 {
 158         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 159         int rc;
 160
 161         /* Common nix configure */
 162         rc = cnxk_nix_configure(eth_dev);
 163         if (rc)
 164                 return rc;
 165
 166         plt_nix_dbg("Configured port%d platform specific rx_offload_flags=%x"
 167                     " tx_offload_flags=0x%x",
 168                     eth_dev->data->port_id, dev->rx_offload_flags,
 169                     dev->tx_offload_flags);
 170         return 0;
 171 }
 172
 173 /* Update platform specific eth dev ops */
 174 static void
 175 nix_eth_dev_ops_override(void)
 176 {
 177         static int init_once;
 178
 179         if (init_once)
 180                 return;
 181         init_once = 1;
 182
 183         /* Update platform specific ops */
 184         cnxk_eth_dev_ops.dev_configure = cn10k_nix_configure;
 185         cnxk_eth_dev_ops.tx_queue_setup = cn10k_nix_tx_queue_setup;
 186         cnxk_eth_dev_ops.rx_queue_setup = cn10k_nix_rx_queue_setup;
 187         cnxk_eth_dev_ops.tx_queue_stop = cn10k_nix_tx_queue_stop;
 188         cnxk_eth_dev_ops.dev_ptypes_set = cn10k_nix_ptypes_set;
 189 }
 190
 191 static int
 192 cn10k_nix_remove(struct rte_pci_device *pci_dev)
 193 {
 194         return cnxk_nix_remove(pci_dev);
 195 }
 196
 197 static int
 198 cn10k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
 199 {
 200         struct rte_eth_dev *eth_dev;
 201         int rc;
 202
 203         if (RTE_CACHE_LINE_SIZE != 64) {
 204                 plt_err("Driver not compiled for CN10K");
 205                 return -EFAULT;
 206         }
 207
 208         rc = roc_plt_init();
 209         if (rc) {
 210                 plt_err("Failed to initialize platform model, rc=%d", rc);
 211                 return rc;
 212         }
 213
 214         nix_eth_dev_ops_override();
 215
 216         /* Common probe */
 217         rc = cnxk_nix_probe(pci_drv, pci_dev);
 218         if (rc)
 219                 return rc;
 220
 221         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 222                 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
 223                 if (!eth_dev)
 224                         return -ENOENT;
 225         }
 226         return 0;
 227 }
 228
 229 static const struct rte_pci_id cn10k_pci_nix_map[] = {
 230         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_PF),
 231         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_PF),
 232         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_VF),
 233         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_VF),
 234         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_AF_VF),
 235         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_AF_VF),
 236         {
 237                 .vendor_id = 0,
 238         },
 239 };
 240
 241 static struct rte_pci_driver cn10k_pci_nix = {
 242         .id_table = cn10k_pci_nix_map,
 243         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
 244                      RTE_PCI_DRV_INTR_LSC,
 245         .probe = cn10k_nix_probe,
 246         .remove = cn10k_nix_remove,
 247 };
 248
 249 RTE_PMD_REGISTER_PCI(net_cn10k, cn10k_pci_nix);
 250 RTE_PMD_REGISTER_PCI_TABLE(net_cn10k, cn10k_pci_nix_map);
 251 RTE_PMD_REGISTER_KMOD_DEP(net_cn10k, "vfio-pci");