1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
4 #include "cn10k_ethdev.h"
9 cn10k_nix_ptypes_set(struct rte_eth_dev *eth_dev, uint32_t ptype_mask)
11 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
14 dev->rx_offload_flags |= NIX_RX_OFFLOAD_PTYPE_F;
15 dev->ptype_disable = 0;
17 dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_PTYPE_F;
18 dev->ptype_disable = 1;
25 nix_form_default_desc(struct cnxk_eth_dev *dev, struct cn10k_eth_txq *txq,
28 struct nix_send_ext_s *send_hdr_ext;
29 union nix_send_hdr_w0_u send_hdr_w0;
30 union nix_send_sg_s sg_w0;
34 /* Initialize the fields based on basic single segment packet */
35 memset(&txq->cmd, 0, sizeof(txq->cmd));
39 if (dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
40 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
41 send_hdr_w0.sizem1 = 2;
43 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[0];
44 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
46 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
47 send_hdr_w0.sizem1 = 1;
51 sg_w0.subdc = NIX_SUBDC_SG;
53 sg_w0.ld_type = NIX_SENDLDTYPE_LDD;
55 txq->send_hdr_w0 = send_hdr_w0.u;
62 cn10k_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
63 uint16_t nb_desc, unsigned int socket,
64 const struct rte_eth_txconf *tx_conf)
66 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
67 struct cn10k_eth_txq *txq;
68 struct roc_nix_sq *sq;
73 /* Common Tx queue setup */
74 rc = cnxk_nix_tx_queue_setup(eth_dev, qid, nb_desc,
75 sizeof(struct cn10k_eth_txq), tx_conf);
80 /* Update fast path queue */
81 txq = eth_dev->data->tx_queues[qid];
83 /* Store lmt base in tx queue for easy access */
84 txq->lmt_base = dev->nix.lmt_base;
85 txq->io_addr = sq->io_addr;
86 txq->nb_sqb_bufs_adj = sq->nb_sqb_bufs_adj;
87 txq->sqes_per_sqb_log2 = sq->sqes_per_sqb_log2;
89 nix_form_default_desc(dev, txq, qid);
90 txq->lso_tun_fmt = dev->lso_tun_fmt;
95 cn10k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
96 uint16_t nb_desc, unsigned int socket,
97 const struct rte_eth_rxconf *rx_conf,
98 struct rte_mempool *mp)
100 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
101 struct cn10k_eth_rxq *rxq;
102 struct roc_nix_rq *rq;
103 struct roc_nix_cq *cq;
106 RTE_SET_USED(socket);
108 /* CQ Errata needs min 4K ring */
109 if (dev->cq_min_4k && nb_desc < 4096)
112 /* Common Rx queue setup */
113 rc = cnxk_nix_rx_queue_setup(eth_dev, qid, nb_desc,
114 sizeof(struct cn10k_eth_rxq), rx_conf, mp);
121 /* Update fast path queue */
122 rxq = eth_dev->data->rx_queues[qid];
124 rxq->desc = (uintptr_t)cq->desc_base;
125 rxq->cq_door = cq->door;
126 rxq->cq_status = cq->status;
127 rxq->wdata = cq->wdata;
128 rxq->head = cq->head;
129 rxq->qmask = cq->qmask;
131 /* Data offset from data to start of mbuf is first_skip */
132 rxq->data_off = rq->first_skip;
133 rxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev);
136 rxq->lookup_mem = cnxk_nix_fastpath_lookup_mem_get();
141 cn10k_nix_configure(struct rte_eth_dev *eth_dev)
143 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
146 /* Common nix configure */
147 rc = cnxk_nix_configure(eth_dev);
151 plt_nix_dbg("Configured port%d platform specific rx_offload_flags=%x"
152 " tx_offload_flags=0x%x",
153 eth_dev->data->port_id, dev->rx_offload_flags,
154 dev->tx_offload_flags);
158 /* Update platform specific eth dev ops */
160 nix_eth_dev_ops_override(void)
162 static int init_once;
168 /* Update platform specific ops */
169 cnxk_eth_dev_ops.dev_configure = cn10k_nix_configure;
170 cnxk_eth_dev_ops.tx_queue_setup = cn10k_nix_tx_queue_setup;
171 cnxk_eth_dev_ops.rx_queue_setup = cn10k_nix_rx_queue_setup;
172 cnxk_eth_dev_ops.dev_ptypes_set = cn10k_nix_ptypes_set;
176 cn10k_nix_remove(struct rte_pci_device *pci_dev)
178 return cnxk_nix_remove(pci_dev);
182 cn10k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
184 struct rte_eth_dev *eth_dev;
187 if (RTE_CACHE_LINE_SIZE != 64) {
188 plt_err("Driver not compiled for CN10K");
194 plt_err("Failed to initialize platform model, rc=%d", rc);
198 nix_eth_dev_ops_override();
201 rc = cnxk_nix_probe(pci_drv, pci_dev);
205 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
206 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
213 static const struct rte_pci_id cn10k_pci_nix_map[] = {
214 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_PF),
215 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_PF),
216 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_VF),
217 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_VF),
218 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_AF_VF),
219 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_AF_VF),
225 static struct rte_pci_driver cn10k_pci_nix = {
226 .id_table = cn10k_pci_nix_map,
227 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
228 RTE_PCI_DRV_INTR_LSC,
229 .probe = cn10k_nix_probe,
230 .remove = cn10k_nix_remove,
233 RTE_PMD_REGISTER_PCI(net_cn10k, cn10k_pci_nix);
234 RTE_PMD_REGISTER_PCI_TABLE(net_cn10k, cn10k_pci_nix_map);
235 RTE_PMD_REGISTER_KMOD_DEP(net_cn10k, "vfio-pci");