1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
4 #include "cn10k_ethdev.h"
5 #include "cn10k_rte_flow.h"
10 nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
12 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
13 struct rte_eth_dev_data *data = eth_dev->data;
14 struct rte_eth_conf *conf = &data->dev_conf;
15 struct rte_eth_rxmode *rxmode = &conf->rxmode;
18 if (rxmode->mq_mode == RTE_ETH_MQ_RX_RSS &&
19 (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_RSS_HASH))
20 flags |= NIX_RX_OFFLOAD_RSS_F;
22 if (dev->rx_offloads &
23 (RTE_ETH_RX_OFFLOAD_TCP_CKSUM | RTE_ETH_RX_OFFLOAD_UDP_CKSUM))
24 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
26 if (dev->rx_offloads &
27 (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM))
28 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
30 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER)
31 flags |= NIX_RX_MULTI_SEG_F;
33 if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP))
34 flags |= NIX_RX_OFFLOAD_TSTAMP_F;
36 if (!dev->ptype_disable)
37 flags |= NIX_RX_OFFLOAD_PTYPE_F;
39 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)
40 flags |= NIX_RX_OFFLOAD_SECURITY_F;
46 nix_tx_offload_flags(struct rte_eth_dev *eth_dev)
48 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
49 uint64_t conf = dev->tx_offloads;
52 /* Fastpath is dependent on these enums */
53 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_TCP_CKSUM != (1ULL << 52));
54 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_SCTP_CKSUM != (2ULL << 52));
55 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_UDP_CKSUM != (3ULL << 52));
56 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_IP_CKSUM != (1ULL << 54));
57 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_IPV4 != (1ULL << 55));
58 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_OUTER_IP_CKSUM != (1ULL << 58));
59 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_OUTER_IPV4 != (1ULL << 59));
60 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_OUTER_IPV6 != (1ULL << 60));
61 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_OUTER_UDP_CKSUM != (1ULL << 41));
62 RTE_BUILD_BUG_ON(RTE_MBUF_L2_LEN_BITS != 7);
63 RTE_BUILD_BUG_ON(RTE_MBUF_L3_LEN_BITS != 9);
64 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL2_LEN_BITS != 7);
65 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL3_LEN_BITS != 9);
66 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) !=
67 offsetof(struct rte_mbuf, buf_iova) + 8);
68 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
69 offsetof(struct rte_mbuf, buf_iova) + 16);
70 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
71 offsetof(struct rte_mbuf, ol_flags) + 12);
72 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, tx_offload) !=
73 offsetof(struct rte_mbuf, pool) + 2 * sizeof(void *));
75 if (conf & RTE_ETH_TX_OFFLOAD_VLAN_INSERT ||
76 conf & RTE_ETH_TX_OFFLOAD_QINQ_INSERT)
77 flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F;
79 if (conf & RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
80 conf & RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM)
81 flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F;
83 if (conf & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM ||
84 conf & RTE_ETH_TX_OFFLOAD_TCP_CKSUM ||
85 conf & RTE_ETH_TX_OFFLOAD_UDP_CKSUM || conf & RTE_ETH_TX_OFFLOAD_SCTP_CKSUM)
86 flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F;
88 if (!(conf & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE))
89 flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F;
91 if (conf & RTE_ETH_TX_OFFLOAD_MULTI_SEGS)
92 flags |= NIX_TX_MULTI_SEG_F;
94 /* Enable Inner checksum for TSO */
95 if (conf & RTE_ETH_TX_OFFLOAD_TCP_TSO)
96 flags |= (NIX_TX_OFFLOAD_TSO_F | NIX_TX_OFFLOAD_L3_L4_CSUM_F);
98 /* Enable Inner and Outer checksum for Tunnel TSO */
99 if (conf & (RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
100 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO | RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO))
101 flags |= (NIX_TX_OFFLOAD_TSO_F | NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |
102 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
104 if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP))
105 flags |= NIX_TX_OFFLOAD_TSTAMP_F;
107 if (conf & RTE_ETH_TX_OFFLOAD_SECURITY)
108 flags |= NIX_TX_OFFLOAD_SECURITY_F;
114 cn10k_nix_ptypes_set(struct rte_eth_dev *eth_dev, uint32_t ptype_mask)
116 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
119 dev->rx_offload_flags |= NIX_RX_OFFLOAD_PTYPE_F;
120 dev->ptype_disable = 0;
122 dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_PTYPE_F;
123 dev->ptype_disable = 1;
126 cn10k_eth_set_rx_function(eth_dev);
131 nix_form_default_desc(struct cnxk_eth_dev *dev, struct cn10k_eth_txq *txq,
134 union nix_send_hdr_w0_u send_hdr_w0;
136 /* Initialize the fields based on basic single segment packet */
138 if (dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
139 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
140 send_hdr_w0.sizem1 = 2;
141 if (dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
142 /* Default: one seg packet would have:
143 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
146 send_hdr_w0.sizem1 = 3;
148 /* To calculate the offset for send_mem,
149 * send_hdr->w0.sizem1 * 2
151 txq->ts_mem = dev->tstamp.tx_tstamp_iova;
154 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
155 send_hdr_w0.sizem1 = 1;
157 send_hdr_w0.sq = qid;
158 txq->send_hdr_w0 = send_hdr_w0.u;
163 cn10k_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
164 uint16_t nb_desc, unsigned int socket,
165 const struct rte_eth_txconf *tx_conf)
167 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
168 struct roc_nix *nix = &dev->nix;
169 struct roc_cpt_lf *inl_lf;
170 struct cn10k_eth_txq *txq;
171 struct roc_nix_sq *sq;
175 RTE_SET_USED(socket);
177 /* Common Tx queue setup */
178 rc = cnxk_nix_tx_queue_setup(eth_dev, qid, nb_desc,
179 sizeof(struct cn10k_eth_txq), tx_conf);
184 /* Update fast path queue */
185 txq = eth_dev->data->tx_queues[qid];
186 txq->fc_mem = sq->fc;
187 /* Store lmt base in tx queue for easy access */
188 txq->lmt_base = nix->lmt_base;
189 txq->io_addr = sq->io_addr;
190 txq->nb_sqb_bufs_adj = sq->nb_sqb_bufs_adj;
191 txq->sqes_per_sqb_log2 = sq->sqes_per_sqb_log2;
193 /* Fetch CPT LF info for outbound if present */
194 if (dev->outb.lf_base) {
195 crypto_qid = qid % dev->outb.nb_crypto_qs;
196 inl_lf = dev->outb.lf_base + crypto_qid;
198 txq->cpt_io_addr = inl_lf->io_addr;
199 txq->cpt_fc = inl_lf->fc_addr;
200 txq->cpt_desc = inl_lf->nb_desc * 0.7;
201 txq->sa_base = (uint64_t)dev->outb.sa_base;
202 txq->sa_base |= eth_dev->data->port_id;
203 PLT_STATIC_ASSERT(ROC_NIX_INL_SA_BASE_ALIGN == BIT_ULL(16));
206 nix_form_default_desc(dev, txq, qid);
207 txq->lso_tun_fmt = dev->lso_tun_fmt;
212 cn10k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
213 uint16_t nb_desc, unsigned int socket,
214 const struct rte_eth_rxconf *rx_conf,
215 struct rte_mempool *mp)
217 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
218 struct cnxk_eth_rxq_sp *rxq_sp;
219 struct cn10k_eth_rxq *rxq;
220 struct roc_nix_rq *rq;
221 struct roc_nix_cq *cq;
224 RTE_SET_USED(socket);
226 /* CQ Errata needs min 4K ring */
227 if (dev->cq_min_4k && nb_desc < 4096)
230 /* Common Rx queue setup */
231 rc = cnxk_nix_rx_queue_setup(eth_dev, qid, nb_desc,
232 sizeof(struct cn10k_eth_rxq), rx_conf, mp);
239 /* Update fast path queue */
240 rxq = eth_dev->data->rx_queues[qid];
242 rxq->desc = (uintptr_t)cq->desc_base;
243 rxq->cq_door = cq->door;
244 rxq->cq_status = cq->status;
245 rxq->wdata = cq->wdata;
246 rxq->head = cq->head;
247 rxq->qmask = cq->qmask;
248 rxq->tstamp = &dev->tstamp;
250 /* Data offset from data to start of mbuf is first_skip */
251 rxq->data_off = rq->first_skip;
252 rxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev);
254 /* Setup security related info */
255 if (dev->rx_offload_flags & NIX_RX_OFFLOAD_SECURITY_F) {
256 rxq->lmt_base = dev->nix.lmt_base;
257 rxq->sa_base = roc_nix_inl_inb_sa_base_get(&dev->nix,
260 rxq_sp = cnxk_eth_rxq_to_sp(rxq);
261 rxq->aura_handle = rxq_sp->qconf.mp->pool_id;
264 rxq->lookup_mem = cnxk_nix_fastpath_lookup_mem_get();
269 cn10k_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
271 struct cn10k_eth_txq *txq = eth_dev->data->tx_queues[qidx];
274 rc = cnxk_nix_tx_queue_stop(eth_dev, qidx);
278 /* Clear fc cache pkts to trigger worker stop */
279 txq->fc_cache_pkts = 0;
284 cn10k_nix_configure(struct rte_eth_dev *eth_dev)
286 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
289 /* Common nix configure */
290 rc = cnxk_nix_configure(eth_dev);
294 /* Update offload flags */
295 dev->rx_offload_flags = nix_rx_offload_flags(eth_dev);
296 dev->tx_offload_flags = nix_tx_offload_flags(eth_dev);
298 plt_nix_dbg("Configured port%d platform specific rx_offload_flags=%x"
299 " tx_offload_flags=0x%x",
300 eth_dev->data->port_id, dev->rx_offload_flags,
301 dev->tx_offload_flags);
305 /* Function to enable ptp config for VFs */
307 nix_ptp_enable_vf(struct rte_eth_dev *eth_dev)
309 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
311 if (nix_recalc_mtu(eth_dev))
312 plt_err("Failed to set MTU size for ptp");
314 dev->rx_offload_flags |= NIX_RX_OFFLOAD_TSTAMP_F;
316 /* Setting up the function pointers as per new offload flags */
317 cn10k_eth_set_rx_function(eth_dev);
318 cn10k_eth_set_tx_function(eth_dev);
322 nix_ptp_vf_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
324 struct cn10k_eth_rxq *rxq = queue;
325 struct cnxk_eth_rxq_sp *rxq_sp;
326 struct rte_eth_dev *eth_dev;
331 rxq_sp = cnxk_eth_rxq_to_sp(rxq);
332 eth_dev = rxq_sp->dev->eth_dev;
333 nix_ptp_enable_vf(eth_dev);
339 cn10k_nix_ptp_info_update_cb(struct roc_nix *nix, bool ptp_en)
341 struct cnxk_eth_dev *dev = (struct cnxk_eth_dev *)nix;
342 struct rte_eth_dev *eth_dev;
343 struct cn10k_eth_rxq *rxq;
349 eth_dev = dev->eth_dev;
353 dev->ptp_en = ptp_en;
355 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
356 rxq = eth_dev->data->rx_queues[i];
357 rxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev);
360 if (roc_nix_is_vf_or_sdp(nix) && !(roc_nix_is_sdp(nix)) &&
361 !(roc_nix_is_lbk(nix))) {
362 /* In case of VF, setting of MTU cannot be done directly in this
363 * function as this is running as part of MBOX request(PF->VF)
364 * and MTU setting also requires MBOX message to be
367 eth_dev->rx_pkt_burst = nix_ptp_vf_burst;
375 cn10k_nix_timesync_enable(struct rte_eth_dev *eth_dev)
377 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
380 rc = cnxk_nix_timesync_enable(eth_dev);
384 dev->rx_offload_flags |= NIX_RX_OFFLOAD_TSTAMP_F;
385 dev->tx_offload_flags |= NIX_TX_OFFLOAD_TSTAMP_F;
387 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
388 nix_form_default_desc(dev, eth_dev->data->tx_queues[i], i);
390 /* Setting up the rx[tx]_offload_flags due to change
391 * in rx[tx]_offloads.
393 cn10k_eth_set_rx_function(eth_dev);
394 cn10k_eth_set_tx_function(eth_dev);
399 cn10k_nix_timesync_disable(struct rte_eth_dev *eth_dev)
401 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
404 rc = cnxk_nix_timesync_disable(eth_dev);
408 dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_TSTAMP_F;
409 dev->tx_offload_flags &= ~NIX_TX_OFFLOAD_TSTAMP_F;
411 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
412 nix_form_default_desc(dev, eth_dev->data->tx_queues[i], i);
414 /* Setting up the rx[tx]_offload_flags due to change
415 * in rx[tx]_offloads.
417 cn10k_eth_set_rx_function(eth_dev);
418 cn10k_eth_set_tx_function(eth_dev);
423 cn10k_nix_dev_start(struct rte_eth_dev *eth_dev)
425 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
426 struct roc_nix *nix = &dev->nix;
429 /* Common eth dev start */
430 rc = cnxk_nix_dev_start(eth_dev);
434 /* Update VF about data off shifted by 8 bytes if PTP already
435 * enabled in PF owning this VF
437 if (dev->ptp_en && (!roc_nix_is_pf(nix) && (!roc_nix_is_sdp(nix))))
438 nix_ptp_enable_vf(eth_dev);
440 /* Setting up the rx[tx]_offload_flags due to change
441 * in rx[tx]_offloads.
443 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
444 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
446 cn10k_eth_set_tx_function(eth_dev);
447 cn10k_eth_set_rx_function(eth_dev);
451 /* Update platform specific eth dev ops */
453 nix_eth_dev_ops_override(void)
455 static int init_once;
461 /* Update platform specific ops */
462 cnxk_eth_dev_ops.dev_configure = cn10k_nix_configure;
463 cnxk_eth_dev_ops.tx_queue_setup = cn10k_nix_tx_queue_setup;
464 cnxk_eth_dev_ops.rx_queue_setup = cn10k_nix_rx_queue_setup;
465 cnxk_eth_dev_ops.tx_queue_stop = cn10k_nix_tx_queue_stop;
466 cnxk_eth_dev_ops.dev_start = cn10k_nix_dev_start;
467 cnxk_eth_dev_ops.dev_ptypes_set = cn10k_nix_ptypes_set;
468 cnxk_eth_dev_ops.timesync_enable = cn10k_nix_timesync_enable;
469 cnxk_eth_dev_ops.timesync_disable = cn10k_nix_timesync_disable;
473 npc_flow_ops_override(void)
475 static int init_once;
481 /* Update platform specific ops */
482 cnxk_flow_ops.create = cn10k_flow_create;
483 cnxk_flow_ops.destroy = cn10k_flow_destroy;
487 cn10k_nix_remove(struct rte_pci_device *pci_dev)
489 return cnxk_nix_remove(pci_dev);
493 cn10k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
495 struct rte_eth_dev *eth_dev;
496 struct cnxk_eth_dev *dev;
499 if (RTE_CACHE_LINE_SIZE != 64) {
500 plt_err("Driver not compiled for CN10K");
506 plt_err("Failed to initialize platform model, rc=%d", rc);
510 nix_eth_dev_ops_override();
511 npc_flow_ops_override();
513 cn10k_eth_sec_ops_override();
516 rc = cnxk_nix_probe(pci_drv, pci_dev);
520 /* Find eth dev allocated */
521 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
525 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
526 /* Setup callbacks for secondary process */
527 cn10k_eth_set_tx_function(eth_dev);
528 cn10k_eth_set_rx_function(eth_dev);
532 dev = cnxk_eth_pmd_priv(eth_dev);
534 /* DROP_RE is not supported with inline IPSec for CN10K A0 and
535 * when vector mode is enabled.
537 if ((roc_model_is_cn10ka_a0() || roc_model_is_cnf10ka_a0() ||
538 roc_model_is_cnf10kb_a0()) &&
539 !roc_env_is_asim()) {
540 dev->ipsecd_drop_re_dis = 1;
541 dev->vec_drop_re_dis = 1;
544 /* Register up msg callbacks for PTP information */
545 roc_nix_ptp_info_cb_register(&dev->nix, cn10k_nix_ptp_info_update_cb);
550 static const struct rte_pci_id cn10k_pci_nix_map[] = {
551 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_PF),
552 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_PF),
553 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_PF),
554 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_VF),
555 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_VF),
556 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_VF),
557 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_AF_VF),
558 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_AF_VF),
559 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_AF_VF),
565 static struct rte_pci_driver cn10k_pci_nix = {
566 .id_table = cn10k_pci_nix_map,
567 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
568 RTE_PCI_DRV_INTR_LSC,
569 .probe = cn10k_nix_probe,
570 .remove = cn10k_nix_remove,
573 RTE_PMD_REGISTER_PCI(net_cn10k, cn10k_pci_nix);
574 RTE_PMD_REGISTER_PCI_TABLE(net_cn10k, cn10k_pci_nix_map);
575 RTE_PMD_REGISTER_KMOD_DEP(net_cn10k, "vfio-pci");