1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
4 #include "cn10k_ethdev.h"
5 #include "cn10k_flow.h"
10 nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
12 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
13 struct rte_eth_dev_data *data = eth_dev->data;
14 struct rte_eth_conf *conf = &data->dev_conf;
15 struct rte_eth_rxmode *rxmode = &conf->rxmode;
18 if (rxmode->mq_mode == RTE_ETH_MQ_RX_RSS &&
19 (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_RSS_HASH))
20 flags |= NIX_RX_OFFLOAD_RSS_F;
22 if (dev->rx_offloads &
23 (RTE_ETH_RX_OFFLOAD_TCP_CKSUM | RTE_ETH_RX_OFFLOAD_UDP_CKSUM))
24 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
26 if (dev->rx_offloads &
27 (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM))
28 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
30 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER)
31 flags |= NIX_RX_MULTI_SEG_F;
33 if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP))
34 flags |= NIX_RX_OFFLOAD_TSTAMP_F;
36 if (!dev->ptype_disable)
37 flags |= NIX_RX_OFFLOAD_PTYPE_F;
39 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)
40 flags |= NIX_RX_OFFLOAD_SECURITY_F;
42 if (dev->rx_mark_update)
43 flags |= NIX_RX_OFFLOAD_MARK_UPDATE_F;
49 nix_tx_offload_flags(struct rte_eth_dev *eth_dev)
51 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
52 uint64_t conf = dev->tx_offloads;
55 /* Fastpath is dependent on these enums */
56 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_TCP_CKSUM != (1ULL << 52));
57 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_SCTP_CKSUM != (2ULL << 52));
58 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_UDP_CKSUM != (3ULL << 52));
59 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_IP_CKSUM != (1ULL << 54));
60 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_IPV4 != (1ULL << 55));
61 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_OUTER_IP_CKSUM != (1ULL << 58));
62 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_OUTER_IPV4 != (1ULL << 59));
63 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_OUTER_IPV6 != (1ULL << 60));
64 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_OUTER_UDP_CKSUM != (1ULL << 41));
65 RTE_BUILD_BUG_ON(RTE_MBUF_L2_LEN_BITS != 7);
66 RTE_BUILD_BUG_ON(RTE_MBUF_L3_LEN_BITS != 9);
67 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL2_LEN_BITS != 7);
68 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL3_LEN_BITS != 9);
69 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) !=
70 offsetof(struct rte_mbuf, buf_iova) + 8);
71 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
72 offsetof(struct rte_mbuf, buf_iova) + 16);
73 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
74 offsetof(struct rte_mbuf, ol_flags) + 12);
75 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, tx_offload) !=
76 offsetof(struct rte_mbuf, pool) + 2 * sizeof(void *));
78 if (conf & RTE_ETH_TX_OFFLOAD_VLAN_INSERT ||
79 conf & RTE_ETH_TX_OFFLOAD_QINQ_INSERT)
80 flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F;
82 if (conf & RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
83 conf & RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM)
84 flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F;
86 if (conf & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM ||
87 conf & RTE_ETH_TX_OFFLOAD_TCP_CKSUM ||
88 conf & RTE_ETH_TX_OFFLOAD_UDP_CKSUM || conf & RTE_ETH_TX_OFFLOAD_SCTP_CKSUM)
89 flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F;
91 if (!(conf & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE))
92 flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F;
94 if (conf & RTE_ETH_TX_OFFLOAD_MULTI_SEGS)
95 flags |= NIX_TX_MULTI_SEG_F;
97 /* Enable Inner checksum for TSO */
98 if (conf & RTE_ETH_TX_OFFLOAD_TCP_TSO)
99 flags |= (NIX_TX_OFFLOAD_TSO_F | NIX_TX_OFFLOAD_L3_L4_CSUM_F);
101 /* Enable Inner and Outer checksum for Tunnel TSO */
102 if (conf & (RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
103 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO | RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO))
104 flags |= (NIX_TX_OFFLOAD_TSO_F | NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |
105 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
107 if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP))
108 flags |= NIX_TX_OFFLOAD_TSTAMP_F;
110 if (conf & RTE_ETH_TX_OFFLOAD_SECURITY)
111 flags |= NIX_TX_OFFLOAD_SECURITY_F;
117 cn10k_nix_ptypes_set(struct rte_eth_dev *eth_dev, uint32_t ptype_mask)
119 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
122 dev->rx_offload_flags |= NIX_RX_OFFLOAD_PTYPE_F;
123 dev->ptype_disable = 0;
125 dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_PTYPE_F;
126 dev->ptype_disable = 1;
129 cn10k_eth_set_rx_function(eth_dev);
134 nix_form_default_desc(struct cnxk_eth_dev *dev, struct cn10k_eth_txq *txq,
137 union nix_send_hdr_w0_u send_hdr_w0;
139 /* Initialize the fields based on basic single segment packet */
141 if (dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
142 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
143 send_hdr_w0.sizem1 = 2;
144 if (dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
145 /* Default: one seg packet would have:
146 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
149 send_hdr_w0.sizem1 = 3;
151 /* To calculate the offset for send_mem,
152 * send_hdr->w0.sizem1 * 2
154 txq->ts_mem = dev->tstamp.tx_tstamp_iova;
157 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
158 send_hdr_w0.sizem1 = 1;
160 send_hdr_w0.sq = qid;
161 txq->send_hdr_w0 = send_hdr_w0.u;
166 cn10k_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
167 uint16_t nb_desc, unsigned int socket,
168 const struct rte_eth_txconf *tx_conf)
170 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
171 struct roc_nix *nix = &dev->nix;
172 struct roc_cpt_lf *inl_lf;
173 struct cn10k_eth_txq *txq;
174 struct roc_nix_sq *sq;
178 RTE_SET_USED(socket);
180 /* Common Tx queue setup */
181 rc = cnxk_nix_tx_queue_setup(eth_dev, qid, nb_desc,
182 sizeof(struct cn10k_eth_txq), tx_conf);
187 /* Update fast path queue */
188 txq = eth_dev->data->tx_queues[qid];
189 txq->fc_mem = sq->fc;
190 /* Store lmt base in tx queue for easy access */
191 txq->lmt_base = nix->lmt_base;
192 txq->io_addr = sq->io_addr;
193 txq->nb_sqb_bufs_adj = sq->nb_sqb_bufs_adj;
194 txq->sqes_per_sqb_log2 = sq->sqes_per_sqb_log2;
196 /* Fetch CPT LF info for outbound if present */
197 if (dev->outb.lf_base) {
198 crypto_qid = qid % dev->outb.nb_crypto_qs;
199 inl_lf = dev->outb.lf_base + crypto_qid;
201 txq->cpt_io_addr = inl_lf->io_addr;
202 txq->cpt_fc = inl_lf->fc_addr;
203 txq->cpt_desc = inl_lf->nb_desc * 0.7;
204 txq->sa_base = (uint64_t)dev->outb.sa_base;
205 txq->sa_base |= eth_dev->data->port_id;
206 PLT_STATIC_ASSERT(ROC_NIX_INL_SA_BASE_ALIGN == BIT_ULL(16));
209 nix_form_default_desc(dev, txq, qid);
210 txq->lso_tun_fmt = dev->lso_tun_fmt;
215 cn10k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
216 uint16_t nb_desc, unsigned int socket,
217 const struct rte_eth_rxconf *rx_conf,
218 struct rte_mempool *mp)
220 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
221 struct cnxk_eth_rxq_sp *rxq_sp;
222 struct cn10k_eth_rxq *rxq;
223 struct roc_nix_rq *rq;
224 struct roc_nix_cq *cq;
227 RTE_SET_USED(socket);
229 /* CQ Errata needs min 4K ring */
230 if (dev->cq_min_4k && nb_desc < 4096)
233 /* Common Rx queue setup */
234 rc = cnxk_nix_rx_queue_setup(eth_dev, qid, nb_desc,
235 sizeof(struct cn10k_eth_rxq), rx_conf, mp);
242 /* Update fast path queue */
243 rxq = eth_dev->data->rx_queues[qid];
245 rxq->desc = (uintptr_t)cq->desc_base;
246 rxq->cq_door = cq->door;
247 rxq->cq_status = cq->status;
248 rxq->wdata = cq->wdata;
249 rxq->head = cq->head;
250 rxq->qmask = cq->qmask;
251 rxq->tstamp = &dev->tstamp;
253 /* Data offset from data to start of mbuf is first_skip */
254 rxq->data_off = rq->first_skip;
255 rxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev);
257 /* Setup security related info */
258 if (dev->rx_offload_flags & NIX_RX_OFFLOAD_SECURITY_F) {
259 rxq->lmt_base = dev->nix.lmt_base;
260 rxq->sa_base = roc_nix_inl_inb_sa_base_get(&dev->nix,
263 rxq_sp = cnxk_eth_rxq_to_sp(rxq);
264 rxq->aura_handle = rxq_sp->qconf.mp->pool_id;
267 rxq->lookup_mem = cnxk_nix_fastpath_lookup_mem_get();
272 cn10k_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
274 struct cn10k_eth_txq *txq = eth_dev->data->tx_queues[qidx];
277 rc = cnxk_nix_tx_queue_stop(eth_dev, qidx);
281 /* Clear fc cache pkts to trigger worker stop */
282 txq->fc_cache_pkts = 0;
287 cn10k_nix_configure(struct rte_eth_dev *eth_dev)
289 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
292 /* Common nix configure */
293 rc = cnxk_nix_configure(eth_dev);
297 if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY ||
298 dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
299 /* Register callback to handle security error work */
300 roc_nix_inl_cb_register(cn10k_eth_sec_sso_work_cb, NULL);
303 /* Update offload flags */
304 dev->rx_offload_flags = nix_rx_offload_flags(eth_dev);
305 dev->tx_offload_flags = nix_tx_offload_flags(eth_dev);
307 /* reset reassembly dynfield/flag offset */
308 dev->reass_dynfield_off = -1;
309 dev->reass_dynflag_bit = -1;
311 plt_nix_dbg("Configured port%d platform specific rx_offload_flags=%x"
312 " tx_offload_flags=0x%x",
313 eth_dev->data->port_id, dev->rx_offload_flags,
314 dev->tx_offload_flags);
318 /* Function to enable ptp config for VFs */
320 nix_ptp_enable_vf(struct rte_eth_dev *eth_dev)
322 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
324 if (nix_recalc_mtu(eth_dev))
325 plt_err("Failed to set MTU size for ptp");
327 dev->rx_offload_flags |= NIX_RX_OFFLOAD_TSTAMP_F;
329 /* Setting up the function pointers as per new offload flags */
330 cn10k_eth_set_rx_function(eth_dev);
331 cn10k_eth_set_tx_function(eth_dev);
335 nix_ptp_vf_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
337 struct cn10k_eth_rxq *rxq = queue;
338 struct cnxk_eth_rxq_sp *rxq_sp;
339 struct rte_eth_dev *eth_dev;
344 rxq_sp = cnxk_eth_rxq_to_sp(rxq);
345 eth_dev = rxq_sp->dev->eth_dev;
346 nix_ptp_enable_vf(eth_dev);
352 cn10k_nix_ptp_info_update_cb(struct roc_nix *nix, bool ptp_en)
354 struct cnxk_eth_dev *dev = (struct cnxk_eth_dev *)nix;
355 struct rte_eth_dev *eth_dev;
356 struct cn10k_eth_rxq *rxq;
362 eth_dev = dev->eth_dev;
366 dev->ptp_en = ptp_en;
368 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
369 rxq = eth_dev->data->rx_queues[i];
370 rxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev);
373 if (roc_nix_is_vf_or_sdp(nix) && !(roc_nix_is_sdp(nix)) &&
374 !(roc_nix_is_lbk(nix))) {
375 /* In case of VF, setting of MTU cannot be done directly in this
376 * function as this is running as part of MBOX request(PF->VF)
377 * and MTU setting also requires MBOX message to be
380 eth_dev->rx_pkt_burst = nix_ptp_vf_burst;
388 cn10k_nix_timesync_enable(struct rte_eth_dev *eth_dev)
390 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
393 rc = cnxk_nix_timesync_enable(eth_dev);
397 dev->rx_offload_flags |= NIX_RX_OFFLOAD_TSTAMP_F;
398 dev->tx_offload_flags |= NIX_TX_OFFLOAD_TSTAMP_F;
400 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
401 nix_form_default_desc(dev, eth_dev->data->tx_queues[i], i);
403 /* Setting up the rx[tx]_offload_flags due to change
404 * in rx[tx]_offloads.
406 cn10k_eth_set_rx_function(eth_dev);
407 cn10k_eth_set_tx_function(eth_dev);
412 cn10k_nix_timesync_disable(struct rte_eth_dev *eth_dev)
414 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
417 rc = cnxk_nix_timesync_disable(eth_dev);
421 dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_TSTAMP_F;
422 dev->tx_offload_flags &= ~NIX_TX_OFFLOAD_TSTAMP_F;
424 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
425 nix_form_default_desc(dev, eth_dev->data->tx_queues[i], i);
427 /* Setting up the rx[tx]_offload_flags due to change
428 * in rx[tx]_offloads.
430 cn10k_eth_set_rx_function(eth_dev);
431 cn10k_eth_set_tx_function(eth_dev);
436 cn10k_nix_timesync_read_tx_timestamp(struct rte_eth_dev *eth_dev,
437 struct timespec *timestamp)
439 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
440 struct cnxk_timesync_info *tstamp = &dev->tstamp;
443 if (*tstamp->tx_tstamp == 0)
446 *tstamp->tx_tstamp = ((*tstamp->tx_tstamp >> 32) * NSEC_PER_SEC) +
447 (*tstamp->tx_tstamp & 0xFFFFFFFFUL);
448 ns = rte_timecounter_update(&dev->tx_tstamp_tc, *tstamp->tx_tstamp);
449 *timestamp = rte_ns_to_timespec(ns);
450 *tstamp->tx_tstamp = 0;
457 cn10k_nix_dev_start(struct rte_eth_dev *eth_dev)
459 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
460 struct roc_nix *nix = &dev->nix;
463 /* Common eth dev start */
464 rc = cnxk_nix_dev_start(eth_dev);
468 /* Update VF about data off shifted by 8 bytes if PTP already
469 * enabled in PF owning this VF
471 if (dev->ptp_en && (!roc_nix_is_pf(nix) && (!roc_nix_is_sdp(nix))))
472 nix_ptp_enable_vf(eth_dev);
474 /* Setting up the rx[tx]_offload_flags due to change
475 * in rx[tx]_offloads.
477 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
478 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
480 cn10k_eth_set_tx_function(eth_dev);
481 cn10k_eth_set_rx_function(eth_dev);
486 cn10k_nix_rx_metadata_negotiate(struct rte_eth_dev *eth_dev, uint64_t *features)
488 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
491 (RTE_ETH_RX_METADATA_USER_FLAG | RTE_ETH_RX_METADATA_USER_MARK);
494 dev->rx_offload_flags |= NIX_RX_OFFLOAD_MARK_UPDATE_F;
495 dev->rx_mark_update = true;
497 dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_MARK_UPDATE_F;
498 dev->rx_mark_update = false;
501 cn10k_eth_set_rx_function(eth_dev);
507 cn10k_nix_reassembly_capability_get(struct rte_eth_dev *eth_dev,
508 struct rte_eth_ip_reassembly_params *reassembly_capa)
510 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
512 RTE_SET_USED(eth_dev);
514 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
515 reassembly_capa->timeout_ms = 60 * 1000;
516 reassembly_capa->max_frags = 4;
517 reassembly_capa->flags = RTE_ETH_DEV_REASSEMBLY_F_IPV4 |
518 RTE_ETH_DEV_REASSEMBLY_F_IPV6;
526 cn10k_nix_reassembly_conf_get(struct rte_eth_dev *eth_dev,
527 struct rte_eth_ip_reassembly_params *conf)
529 RTE_SET_USED(eth_dev);
535 cn10k_nix_reassembly_conf_set(struct rte_eth_dev *eth_dev,
536 const struct rte_eth_ip_reassembly_params *conf)
538 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
541 rc = roc_nix_reassembly_configure(conf->timeout_ms,
543 if (!rc && dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)
544 dev->rx_offload_flags |= NIX_RX_REAS_F;
549 /* Update platform specific eth dev ops */
551 nix_eth_dev_ops_override(void)
553 static int init_once;
559 /* Update platform specific ops */
560 cnxk_eth_dev_ops.dev_configure = cn10k_nix_configure;
561 cnxk_eth_dev_ops.tx_queue_setup = cn10k_nix_tx_queue_setup;
562 cnxk_eth_dev_ops.rx_queue_setup = cn10k_nix_rx_queue_setup;
563 cnxk_eth_dev_ops.tx_queue_stop = cn10k_nix_tx_queue_stop;
564 cnxk_eth_dev_ops.dev_start = cn10k_nix_dev_start;
565 cnxk_eth_dev_ops.dev_ptypes_set = cn10k_nix_ptypes_set;
566 cnxk_eth_dev_ops.timesync_enable = cn10k_nix_timesync_enable;
567 cnxk_eth_dev_ops.timesync_disable = cn10k_nix_timesync_disable;
568 cnxk_eth_dev_ops.rx_metadata_negotiate =
569 cn10k_nix_rx_metadata_negotiate;
570 cnxk_eth_dev_ops.timesync_read_tx_timestamp =
571 cn10k_nix_timesync_read_tx_timestamp;
572 cnxk_eth_dev_ops.ip_reassembly_capability_get =
573 cn10k_nix_reassembly_capability_get;
574 cnxk_eth_dev_ops.ip_reassembly_conf_get = cn10k_nix_reassembly_conf_get;
575 cnxk_eth_dev_ops.ip_reassembly_conf_set = cn10k_nix_reassembly_conf_set;
579 npc_flow_ops_override(void)
581 static int init_once;
587 /* Update platform specific ops */
588 cnxk_flow_ops.create = cn10k_flow_create;
589 cnxk_flow_ops.destroy = cn10k_flow_destroy;
593 cn10k_nix_remove(struct rte_pci_device *pci_dev)
595 return cnxk_nix_remove(pci_dev);
599 cn10k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
601 struct rte_eth_dev *eth_dev;
602 struct cnxk_eth_dev *dev;
605 if (RTE_CACHE_LINE_SIZE != 64) {
606 plt_err("Driver not compiled for CN10K");
612 plt_err("Failed to initialize platform model, rc=%d", rc);
616 nix_eth_dev_ops_override();
617 npc_flow_ops_override();
619 cn10k_eth_sec_ops_override();
622 rc = cnxk_nix_probe(pci_drv, pci_dev);
626 /* Find eth dev allocated */
627 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
631 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
632 /* Setup callbacks for secondary process */
633 cn10k_eth_set_tx_function(eth_dev);
634 cn10k_eth_set_rx_function(eth_dev);
638 dev = cnxk_eth_pmd_priv(eth_dev);
640 /* DROP_RE is not supported with inline IPSec for CN10K A0 and
641 * when vector mode is enabled.
643 if ((roc_model_is_cn10ka_a0() || roc_model_is_cnf10ka_a0() ||
644 roc_model_is_cnf10kb_a0()) &&
645 !roc_env_is_asim()) {
646 dev->ipsecd_drop_re_dis = 1;
647 dev->vec_drop_re_dis = 1;
650 /* Register up msg callbacks for PTP information */
651 roc_nix_ptp_info_cb_register(&dev->nix, cn10k_nix_ptp_info_update_cb);
656 static const struct rte_pci_id cn10k_pci_nix_map[] = {
657 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_PF),
658 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_PF),
659 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_PF),
660 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_VF),
661 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_VF),
662 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_VF),
663 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_AF_VF),
664 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_AF_VF),
665 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_AF_VF),
671 static struct rte_pci_driver cn10k_pci_nix = {
672 .id_table = cn10k_pci_nix_map,
673 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
674 RTE_PCI_DRV_INTR_LSC,
675 .probe = cn10k_nix_probe,
676 .remove = cn10k_nix_remove,
679 RTE_PMD_REGISTER_PCI(net_cn10k, cn10k_pci_nix);
680 RTE_PMD_REGISTER_PCI_TABLE(net_cn10k, cn10k_pci_nix_map);
681 RTE_PMD_REGISTER_KMOD_DEP(net_cn10k, "vfio-pci");