1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
4 #include "cn9k_ethdev.h"
5 #include "cn9k_rte_flow.h"
10 nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
12 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
13 struct rte_eth_dev_data *data = eth_dev->data;
14 struct rte_eth_conf *conf = &data->dev_conf;
15 struct rte_eth_rxmode *rxmode = &conf->rxmode;
18 if (rxmode->mq_mode == RTE_ETH_MQ_RX_RSS &&
19 (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_RSS_HASH))
20 flags |= NIX_RX_OFFLOAD_RSS_F;
22 if (dev->rx_offloads &
23 (RTE_ETH_RX_OFFLOAD_TCP_CKSUM | RTE_ETH_RX_OFFLOAD_UDP_CKSUM))
24 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
26 if (dev->rx_offloads &
27 (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM))
28 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
30 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER)
31 flags |= NIX_RX_MULTI_SEG_F;
33 if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP))
34 flags |= NIX_RX_OFFLOAD_TSTAMP_F;
36 if (!dev->ptype_disable)
37 flags |= NIX_RX_OFFLOAD_PTYPE_F;
39 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)
40 flags |= NIX_RX_OFFLOAD_SECURITY_F;
46 nix_tx_offload_flags(struct rte_eth_dev *eth_dev)
48 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
49 uint64_t conf = dev->tx_offloads;
52 /* Fastpath is dependent on these enums */
53 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_TCP_CKSUM != (1ULL << 52));
54 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_SCTP_CKSUM != (2ULL << 52));
55 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_UDP_CKSUM != (3ULL << 52));
56 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_IP_CKSUM != (1ULL << 54));
57 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_IPV4 != (1ULL << 55));
58 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_OUTER_IP_CKSUM != (1ULL << 58));
59 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_OUTER_IPV4 != (1ULL << 59));
60 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_OUTER_IPV6 != (1ULL << 60));
61 RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_OUTER_UDP_CKSUM != (1ULL << 41));
62 RTE_BUILD_BUG_ON(RTE_MBUF_L2_LEN_BITS != 7);
63 RTE_BUILD_BUG_ON(RTE_MBUF_L3_LEN_BITS != 9);
64 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL2_LEN_BITS != 7);
65 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL3_LEN_BITS != 9);
66 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) !=
67 offsetof(struct rte_mbuf, buf_iova) + 8);
68 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
69 offsetof(struct rte_mbuf, buf_iova) + 16);
70 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
71 offsetof(struct rte_mbuf, ol_flags) + 12);
72 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, tx_offload) !=
73 offsetof(struct rte_mbuf, pool) + 2 * sizeof(void *));
75 if (conf & RTE_ETH_TX_OFFLOAD_VLAN_INSERT ||
76 conf & RTE_ETH_TX_OFFLOAD_QINQ_INSERT)
77 flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F;
79 if (conf & RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
80 conf & RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM)
81 flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F;
83 if (conf & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM ||
84 conf & RTE_ETH_TX_OFFLOAD_TCP_CKSUM ||
85 conf & RTE_ETH_TX_OFFLOAD_UDP_CKSUM || conf & RTE_ETH_TX_OFFLOAD_SCTP_CKSUM)
86 flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F;
88 if (!(conf & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE))
89 flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F;
91 if (conf & RTE_ETH_TX_OFFLOAD_MULTI_SEGS)
92 flags |= NIX_TX_MULTI_SEG_F;
94 /* Enable Inner checksum for TSO */
95 if (conf & RTE_ETH_TX_OFFLOAD_TCP_TSO)
96 flags |= (NIX_TX_OFFLOAD_TSO_F | NIX_TX_OFFLOAD_L3_L4_CSUM_F);
98 /* Enable Inner and Outer checksum for Tunnel TSO */
99 if (conf & (RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
100 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO | RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO))
101 flags |= (NIX_TX_OFFLOAD_TSO_F | NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |
102 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
104 if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP))
105 flags |= NIX_TX_OFFLOAD_TSTAMP_F;
107 if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY)
108 flags |= NIX_TX_OFFLOAD_SECURITY_F;
114 cn9k_nix_ptypes_set(struct rte_eth_dev *eth_dev, uint32_t ptype_mask)
116 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
119 dev->rx_offload_flags |= NIX_RX_OFFLOAD_PTYPE_F;
120 dev->ptype_disable = 0;
122 dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_PTYPE_F;
123 dev->ptype_disable = 1;
126 cn9k_eth_set_rx_function(eth_dev);
131 nix_form_default_desc(struct cnxk_eth_dev *dev, struct cn9k_eth_txq *txq,
134 union nix_send_hdr_w0_u send_hdr_w0;
136 /* Initialize the fields based on basic single segment packet */
138 if (dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
139 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
140 send_hdr_w0.sizem1 = 2;
141 if (dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
142 /* Default: one seg packet would have:
143 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
146 send_hdr_w0.sizem1 = 3;
148 /* To calculate the offset for send_mem,
149 * send_hdr->w0.sizem1 * 2
151 txq->ts_mem = dev->tstamp.tx_tstamp_iova;
154 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
155 send_hdr_w0.sizem1 = 1;
157 send_hdr_w0.sq = qid;
158 txq->send_hdr_w0 = send_hdr_w0.u;
163 cn9k_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
164 uint16_t nb_desc, unsigned int socket,
165 const struct rte_eth_txconf *tx_conf)
167 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
168 struct roc_cpt_lf *inl_lf;
169 struct cn9k_eth_txq *txq;
170 struct roc_nix_sq *sq;
174 RTE_SET_USED(socket);
176 /* Common Tx queue setup */
177 rc = cnxk_nix_tx_queue_setup(eth_dev, qid, nb_desc,
178 sizeof(struct cn9k_eth_txq), tx_conf);
183 /* Update fast path queue */
184 txq = eth_dev->data->tx_queues[qid];
185 txq->fc_mem = sq->fc;
186 txq->lmt_addr = sq->lmt_addr;
187 txq->io_addr = sq->io_addr;
188 txq->nb_sqb_bufs_adj = sq->nb_sqb_bufs_adj;
189 txq->sqes_per_sqb_log2 = sq->sqes_per_sqb_log2;
191 /* Fetch CPT LF info for outbound if present */
192 if (dev->outb.lf_base) {
193 crypto_qid = qid % dev->outb.nb_crypto_qs;
194 inl_lf = dev->outb.lf_base + crypto_qid;
196 txq->cpt_io_addr = inl_lf->io_addr;
197 txq->cpt_fc = inl_lf->fc_addr;
198 txq->cpt_desc = inl_lf->nb_desc * 0.7;
199 txq->sa_base = (uint64_t)dev->outb.sa_base;
200 txq->sa_base |= eth_dev->data->port_id;
201 PLT_STATIC_ASSERT(BIT_ULL(16) == ROC_NIX_INL_SA_BASE_ALIGN);
204 nix_form_default_desc(dev, txq, qid);
205 txq->lso_tun_fmt = dev->lso_tun_fmt;
210 cn9k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
211 uint16_t nb_desc, unsigned int socket,
212 const struct rte_eth_rxconf *rx_conf,
213 struct rte_mempool *mp)
215 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
216 struct cn9k_eth_rxq *rxq;
217 struct roc_nix_rq *rq;
218 struct roc_nix_cq *cq;
221 RTE_SET_USED(socket);
223 /* CQ Errata needs min 4K ring */
224 if (dev->cq_min_4k && nb_desc < 4096)
227 /* Common Rx queue setup */
228 rc = cnxk_nix_rx_queue_setup(eth_dev, qid, nb_desc,
229 sizeof(struct cn9k_eth_rxq), rx_conf, mp);
236 /* Update fast path queue */
237 rxq = eth_dev->data->rx_queues[qid];
239 rxq->desc = (uintptr_t)cq->desc_base;
240 rxq->cq_door = cq->door;
241 rxq->cq_status = cq->status;
242 rxq->wdata = cq->wdata;
243 rxq->head = cq->head;
244 rxq->qmask = cq->qmask;
245 rxq->tstamp = &dev->tstamp;
247 /* Data offset from data to start of mbuf is first_skip */
248 rxq->data_off = rq->first_skip;
249 rxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev);
252 rxq->lookup_mem = cnxk_nix_fastpath_lookup_mem_get();
257 cn9k_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
259 struct cn9k_eth_txq *txq = eth_dev->data->tx_queues[qidx];
262 rc = cnxk_nix_tx_queue_stop(eth_dev, qidx);
266 /* Clear fc cache pkts to trigger worker stop */
267 txq->fc_cache_pkts = 0;
272 cn9k_nix_configure(struct rte_eth_dev *eth_dev)
274 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
275 struct rte_eth_conf *conf = ð_dev->data->dev_conf;
276 struct rte_eth_txmode *txmode = &conf->txmode;
279 /* Platform specific checks */
280 if ((roc_model_is_cn96_a0() || roc_model_is_cn95_a0()) &&
281 (txmode->offloads & RTE_ETH_TX_OFFLOAD_SCTP_CKSUM) &&
282 ((txmode->offloads & RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
283 (txmode->offloads & RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
284 plt_err("Outer IP and SCTP checksum unsupported");
288 /* Common nix configure */
289 rc = cnxk_nix_configure(eth_dev);
293 /* Update offload flags */
294 dev->rx_offload_flags = nix_rx_offload_flags(eth_dev);
295 dev->tx_offload_flags = nix_tx_offload_flags(eth_dev);
297 plt_nix_dbg("Configured port%d platform specific rx_offload_flags=%x"
298 " tx_offload_flags=0x%x",
299 eth_dev->data->port_id, dev->rx_offload_flags,
300 dev->tx_offload_flags);
304 /* Function to enable ptp config for VFs */
306 nix_ptp_enable_vf(struct rte_eth_dev *eth_dev)
308 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
310 if (nix_recalc_mtu(eth_dev))
311 plt_err("Failed to set MTU size for ptp");
313 dev->rx_offload_flags |= NIX_RX_OFFLOAD_TSTAMP_F;
315 /* Setting up the function pointers as per new offload flags */
316 cn9k_eth_set_rx_function(eth_dev);
317 cn9k_eth_set_tx_function(eth_dev);
321 nix_ptp_vf_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
323 struct cn9k_eth_rxq *rxq = queue;
324 struct cnxk_eth_rxq_sp *rxq_sp;
325 struct rte_eth_dev *eth_dev;
330 rxq_sp = cnxk_eth_rxq_to_sp(rxq);
331 eth_dev = rxq_sp->dev->eth_dev;
332 nix_ptp_enable_vf(eth_dev);
338 cn9k_nix_ptp_info_update_cb(struct roc_nix *nix, bool ptp_en)
340 struct cnxk_eth_dev *dev = (struct cnxk_eth_dev *)nix;
341 struct rte_eth_dev *eth_dev;
342 struct cn9k_eth_rxq *rxq;
348 eth_dev = dev->eth_dev;
352 dev->ptp_en = ptp_en;
354 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
355 rxq = eth_dev->data->rx_queues[i];
356 rxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev);
359 if (roc_nix_is_vf_or_sdp(nix) && !(roc_nix_is_sdp(nix)) &&
360 !(roc_nix_is_lbk(nix))) {
361 /* In case of VF, setting of MTU cannot be done directly in this
362 * function as this is running as part of MBOX request(PF->VF)
363 * and MTU setting also requires MBOX message to be
366 eth_dev->rx_pkt_burst = nix_ptp_vf_burst;
374 cn9k_nix_timesync_enable(struct rte_eth_dev *eth_dev)
376 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
379 rc = cnxk_nix_timesync_enable(eth_dev);
383 dev->rx_offload_flags |= NIX_RX_OFFLOAD_TSTAMP_F;
384 dev->tx_offload_flags |= NIX_TX_OFFLOAD_TSTAMP_F;
386 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
387 nix_form_default_desc(dev, eth_dev->data->tx_queues[i], i);
389 /* Setting up the rx[tx]_offload_flags due to change
390 * in rx[tx]_offloads.
392 cn9k_eth_set_rx_function(eth_dev);
393 cn9k_eth_set_tx_function(eth_dev);
398 cn9k_nix_timesync_disable(struct rte_eth_dev *eth_dev)
400 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
403 rc = cnxk_nix_timesync_disable(eth_dev);
407 dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_TSTAMP_F;
408 dev->tx_offload_flags &= ~NIX_TX_OFFLOAD_TSTAMP_F;
410 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
411 nix_form_default_desc(dev, eth_dev->data->tx_queues[i], i);
413 /* Setting up the rx[tx]_offload_flags due to change
414 * in rx[tx]_offloads.
416 cn9k_eth_set_rx_function(eth_dev);
417 cn9k_eth_set_tx_function(eth_dev);
422 cn9k_nix_dev_start(struct rte_eth_dev *eth_dev)
424 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
425 struct roc_nix *nix = &dev->nix;
428 /* Common eth dev start */
429 rc = cnxk_nix_dev_start(eth_dev);
433 /* Update VF about data off shifted by 8 bytes if PTP already
434 * enabled in PF owning this VF
436 if (dev->ptp_en && (!roc_nix_is_pf(nix) && (!roc_nix_is_sdp(nix))))
437 nix_ptp_enable_vf(eth_dev);
439 /* Setting up the rx[tx]_offload_flags due to change
440 * in rx[tx]_offloads.
442 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
443 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
445 cn9k_eth_set_tx_function(eth_dev);
446 cn9k_eth_set_rx_function(eth_dev);
450 /* Update platform specific eth dev ops */
452 nix_eth_dev_ops_override(void)
454 static int init_once;
460 /* Update platform specific ops */
461 cnxk_eth_dev_ops.dev_configure = cn9k_nix_configure;
462 cnxk_eth_dev_ops.tx_queue_setup = cn9k_nix_tx_queue_setup;
463 cnxk_eth_dev_ops.rx_queue_setup = cn9k_nix_rx_queue_setup;
464 cnxk_eth_dev_ops.tx_queue_stop = cn9k_nix_tx_queue_stop;
465 cnxk_eth_dev_ops.dev_start = cn9k_nix_dev_start;
466 cnxk_eth_dev_ops.dev_ptypes_set = cn9k_nix_ptypes_set;
467 cnxk_eth_dev_ops.timesync_enable = cn9k_nix_timesync_enable;
468 cnxk_eth_dev_ops.timesync_disable = cn9k_nix_timesync_disable;
469 cnxk_eth_dev_ops.mtr_ops_get = NULL;
473 npc_flow_ops_override(void)
475 static int init_once;
481 /* Update platform specific ops */
482 cnxk_flow_ops.create = cn9k_flow_create;
483 cnxk_flow_ops.destroy = cn9k_flow_destroy;
487 cn9k_nix_remove(struct rte_pci_device *pci_dev)
489 return cnxk_nix_remove(pci_dev);
493 cn9k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
495 struct rte_eth_dev *eth_dev;
496 struct cnxk_eth_dev *dev;
499 if (RTE_CACHE_LINE_SIZE != 128) {
500 plt_err("Driver not compiled for CN9K");
506 plt_err("Failed to initialize platform model, rc=%d", rc);
510 nix_eth_dev_ops_override();
511 npc_flow_ops_override();
513 cn9k_eth_sec_ops_override();
516 rc = cnxk_nix_probe(pci_drv, pci_dev);
520 /* Find eth dev allocated */
521 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
525 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
526 /* Setup callbacks for secondary process */
527 cn9k_eth_set_tx_function(eth_dev);
528 cn9k_eth_set_rx_function(eth_dev);
532 dev = cnxk_eth_pmd_priv(eth_dev);
533 /* Update capabilities already set for TSO.
534 * TSO not supported for earlier chip revisions
536 if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0())
537 dev->tx_offload_capa &= ~(RTE_ETH_TX_OFFLOAD_TCP_TSO |
538 RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
539 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |
540 RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO);
542 /* 50G and 100G to be supported for board version C0
545 if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0()) {
546 dev->speed_capa &= ~(uint64_t)RTE_ETH_LINK_SPEED_50G;
547 dev->speed_capa &= ~(uint64_t)RTE_ETH_LINK_SPEED_100G;
552 /* Register up msg callbacks for PTP information */
553 roc_nix_ptp_info_cb_register(&dev->nix, cn9k_nix_ptp_info_update_cb);
555 /* Update HW erratas */
556 if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0())
561 static const struct rte_pci_id cn9k_pci_nix_map[] = {
562 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_PF),
563 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_PF),
564 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_PF),
565 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_PF),
566 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_PF),
567 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_VF),
568 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_VF),
569 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_VF),
570 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_VF),
571 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_VF),
572 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_AF_VF),
573 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_AF_VF),
574 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_AF_VF),
575 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_AF_VF),
576 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_AF_VF),
582 static struct rte_pci_driver cn9k_pci_nix = {
583 .id_table = cn9k_pci_nix_map,
584 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
585 RTE_PCI_DRV_INTR_LSC,
586 .probe = cn9k_nix_probe,
587 .remove = cn9k_nix_remove,
590 RTE_PMD_REGISTER_PCI(net_cn9k, cn9k_pci_nix);
591 RTE_PMD_REGISTER_PCI_TABLE(net_cn9k, cn9k_pci_nix_map);
592 RTE_PMD_REGISTER_KMOD_DEP(net_cn9k, "vfio-pci");