1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
4 #include "cn9k_ethdev.h"
5 #include "cn9k_rte_flow.h"
10 nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
12 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
13 struct rte_eth_dev_data *data = eth_dev->data;
14 struct rte_eth_conf *conf = &data->dev_conf;
15 struct rte_eth_rxmode *rxmode = &conf->rxmode;
18 if (rxmode->mq_mode == ETH_MQ_RX_RSS &&
19 (dev->rx_offloads & DEV_RX_OFFLOAD_RSS_HASH))
20 flags |= NIX_RX_OFFLOAD_RSS_F;
22 if (dev->rx_offloads &
23 (DEV_RX_OFFLOAD_TCP_CKSUM | DEV_RX_OFFLOAD_UDP_CKSUM))
24 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
26 if (dev->rx_offloads &
27 (DEV_RX_OFFLOAD_IPV4_CKSUM | DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM))
28 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
30 if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
31 flags |= NIX_RX_MULTI_SEG_F;
33 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
34 flags |= NIX_RX_OFFLOAD_TSTAMP_F;
36 if (!dev->ptype_disable)
37 flags |= NIX_RX_OFFLOAD_PTYPE_F;
43 nix_tx_offload_flags(struct rte_eth_dev *eth_dev)
45 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
46 uint64_t conf = dev->tx_offloads;
49 /* Fastpath is dependent on these enums */
50 RTE_BUILD_BUG_ON(PKT_TX_TCP_CKSUM != (1ULL << 52));
51 RTE_BUILD_BUG_ON(PKT_TX_SCTP_CKSUM != (2ULL << 52));
52 RTE_BUILD_BUG_ON(PKT_TX_UDP_CKSUM != (3ULL << 52));
53 RTE_BUILD_BUG_ON(PKT_TX_IP_CKSUM != (1ULL << 54));
54 RTE_BUILD_BUG_ON(PKT_TX_IPV4 != (1ULL << 55));
55 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IP_CKSUM != (1ULL << 58));
56 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV4 != (1ULL << 59));
57 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV6 != (1ULL << 60));
58 RTE_BUILD_BUG_ON(PKT_TX_OUTER_UDP_CKSUM != (1ULL << 41));
59 RTE_BUILD_BUG_ON(RTE_MBUF_L2_LEN_BITS != 7);
60 RTE_BUILD_BUG_ON(RTE_MBUF_L3_LEN_BITS != 9);
61 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL2_LEN_BITS != 7);
62 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL3_LEN_BITS != 9);
63 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) !=
64 offsetof(struct rte_mbuf, buf_iova) + 8);
65 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
66 offsetof(struct rte_mbuf, buf_iova) + 16);
67 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
68 offsetof(struct rte_mbuf, ol_flags) + 12);
69 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, tx_offload) !=
70 offsetof(struct rte_mbuf, pool) + 2 * sizeof(void *));
72 if (conf & DEV_TX_OFFLOAD_VLAN_INSERT ||
73 conf & DEV_TX_OFFLOAD_QINQ_INSERT)
74 flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F;
76 if (conf & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
77 conf & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
78 flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F;
80 if (conf & DEV_TX_OFFLOAD_IPV4_CKSUM ||
81 conf & DEV_TX_OFFLOAD_TCP_CKSUM ||
82 conf & DEV_TX_OFFLOAD_UDP_CKSUM || conf & DEV_TX_OFFLOAD_SCTP_CKSUM)
83 flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F;
85 if (!(conf & DEV_TX_OFFLOAD_MBUF_FAST_FREE))
86 flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F;
88 if (conf & DEV_TX_OFFLOAD_MULTI_SEGS)
89 flags |= NIX_TX_MULTI_SEG_F;
91 /* Enable Inner checksum for TSO */
92 if (conf & DEV_TX_OFFLOAD_TCP_TSO)
93 flags |= (NIX_TX_OFFLOAD_TSO_F | NIX_TX_OFFLOAD_L3_L4_CSUM_F);
95 /* Enable Inner and Outer checksum for Tunnel TSO */
96 if (conf & (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
97 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | DEV_TX_OFFLOAD_GRE_TNL_TSO))
98 flags |= (NIX_TX_OFFLOAD_TSO_F | NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |
99 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
101 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
102 flags |= NIX_TX_OFFLOAD_TSTAMP_F;
108 cn9k_nix_ptypes_set(struct rte_eth_dev *eth_dev, uint32_t ptype_mask)
110 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
113 dev->rx_offload_flags |= NIX_RX_OFFLOAD_PTYPE_F;
114 dev->ptype_disable = 0;
116 dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_PTYPE_F;
117 dev->ptype_disable = 1;
120 cn9k_eth_set_rx_function(eth_dev);
125 nix_form_default_desc(struct cnxk_eth_dev *dev, struct cn9k_eth_txq *txq,
128 struct nix_send_ext_s *send_hdr_ext;
129 struct nix_send_hdr_s *send_hdr;
130 struct nix_send_mem_s *send_mem;
131 union nix_send_sg_s *sg;
133 /* Initialize the fields based on basic single segment packet */
134 memset(&txq->cmd, 0, sizeof(txq->cmd));
136 if (dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
137 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
138 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
139 send_hdr->w0.sizem1 = 2;
141 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];
142 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
143 if (dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
144 /* Default: one seg packet would have:
145 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
148 send_hdr->w0.sizem1 = 3;
149 send_hdr_ext->w0.tstmp = 1;
151 /* To calculate the offset for send_mem,
152 * send_hdr->w0.sizem1 * 2
154 send_mem = (struct nix_send_mem_s *)
155 (txq->cmd + (send_hdr->w0.sizem1 << 1));
156 send_mem->w0.cn9k.subdc = NIX_SUBDC_MEM;
157 send_mem->w0.cn9k.alg = NIX_SENDMEMALG_SETTSTMP;
158 send_mem->addr = dev->tstamp.tx_tstamp_iova;
160 sg = (union nix_send_sg_s *)&txq->cmd[4];
162 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
163 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
164 send_hdr->w0.sizem1 = 1;
165 sg = (union nix_send_sg_s *)&txq->cmd[2];
168 send_hdr->w0.sq = qid;
169 sg->subdc = NIX_SUBDC_SG;
171 sg->ld_type = NIX_SENDLDTYPE_LDD;
177 cn9k_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
178 uint16_t nb_desc, unsigned int socket,
179 const struct rte_eth_txconf *tx_conf)
181 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
182 struct cn9k_eth_txq *txq;
183 struct roc_nix_sq *sq;
186 RTE_SET_USED(socket);
188 /* Common Tx queue setup */
189 rc = cnxk_nix_tx_queue_setup(eth_dev, qid, nb_desc,
190 sizeof(struct cn9k_eth_txq), tx_conf);
195 /* Update fast path queue */
196 txq = eth_dev->data->tx_queues[qid];
197 txq->fc_mem = sq->fc;
198 txq->lmt_addr = sq->lmt_addr;
199 txq->io_addr = sq->io_addr;
200 txq->nb_sqb_bufs_adj = sq->nb_sqb_bufs_adj;
201 txq->sqes_per_sqb_log2 = sq->sqes_per_sqb_log2;
203 nix_form_default_desc(dev, txq, qid);
204 txq->lso_tun_fmt = dev->lso_tun_fmt;
209 cn9k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
210 uint16_t nb_desc, unsigned int socket,
211 const struct rte_eth_rxconf *rx_conf,
212 struct rte_mempool *mp)
214 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
215 struct cn9k_eth_rxq *rxq;
216 struct roc_nix_rq *rq;
217 struct roc_nix_cq *cq;
220 RTE_SET_USED(socket);
222 /* CQ Errata needs min 4K ring */
223 if (dev->cq_min_4k && nb_desc < 4096)
226 /* Common Rx queue setup */
227 rc = cnxk_nix_rx_queue_setup(eth_dev, qid, nb_desc,
228 sizeof(struct cn9k_eth_rxq), rx_conf, mp);
235 /* Update fast path queue */
236 rxq = eth_dev->data->rx_queues[qid];
238 rxq->desc = (uintptr_t)cq->desc_base;
239 rxq->cq_door = cq->door;
240 rxq->cq_status = cq->status;
241 rxq->wdata = cq->wdata;
242 rxq->head = cq->head;
243 rxq->qmask = cq->qmask;
244 rxq->tstamp = &dev->tstamp;
246 /* Data offset from data to start of mbuf is first_skip */
247 rxq->data_off = rq->first_skip;
248 rxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev);
251 rxq->lookup_mem = cnxk_nix_fastpath_lookup_mem_get();
256 cn9k_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
258 struct cn9k_eth_txq *txq = eth_dev->data->tx_queues[qidx];
261 rc = cnxk_nix_tx_queue_stop(eth_dev, qidx);
265 /* Clear fc cache pkts to trigger worker stop */
266 txq->fc_cache_pkts = 0;
271 cn9k_nix_configure(struct rte_eth_dev *eth_dev)
273 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
274 struct rte_eth_conf *conf = ð_dev->data->dev_conf;
275 struct rte_eth_txmode *txmode = &conf->txmode;
278 /* Platform specific checks */
279 if ((roc_model_is_cn96_a0() || roc_model_is_cn95_a0()) &&
280 (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
281 ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
282 (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
283 plt_err("Outer IP and SCTP checksum unsupported");
287 /* Common nix configure */
288 rc = cnxk_nix_configure(eth_dev);
292 /* Update offload flags */
293 dev->rx_offload_flags = nix_rx_offload_flags(eth_dev);
294 dev->tx_offload_flags = nix_tx_offload_flags(eth_dev);
296 plt_nix_dbg("Configured port%d platform specific rx_offload_flags=%x"
297 " tx_offload_flags=0x%x",
298 eth_dev->data->port_id, dev->rx_offload_flags,
299 dev->tx_offload_flags);
303 /* Function to enable ptp config for VFs */
305 nix_ptp_enable_vf(struct rte_eth_dev *eth_dev)
307 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
309 if (nix_recalc_mtu(eth_dev))
310 plt_err("Failed to set MTU size for ptp");
312 dev->rx_offload_flags |= NIX_RX_OFFLOAD_TSTAMP_F;
314 /* Setting up the function pointers as per new offload flags */
315 cn9k_eth_set_rx_function(eth_dev);
316 cn9k_eth_set_tx_function(eth_dev);
320 nix_ptp_vf_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
322 struct cn9k_eth_rxq *rxq = queue;
323 struct cnxk_eth_rxq_sp *rxq_sp;
324 struct rte_eth_dev *eth_dev;
329 rxq_sp = cnxk_eth_rxq_to_sp(rxq);
330 eth_dev = rxq_sp->dev->eth_dev;
331 nix_ptp_enable_vf(eth_dev);
337 cn9k_nix_ptp_info_update_cb(struct roc_nix *nix, bool ptp_en)
339 struct cnxk_eth_dev *dev = (struct cnxk_eth_dev *)nix;
340 struct rte_eth_dev *eth_dev;
341 struct cn9k_eth_rxq *rxq;
347 eth_dev = dev->eth_dev;
351 dev->ptp_en = ptp_en;
353 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
354 rxq = eth_dev->data->rx_queues[i];
355 rxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev);
358 if (roc_nix_is_vf_or_sdp(nix) && !(roc_nix_is_sdp(nix)) &&
359 !(roc_nix_is_lbk(nix))) {
360 /* In case of VF, setting of MTU cannot be done directly in this
361 * function as this is running as part of MBOX request(PF->VF)
362 * and MTU setting also requires MBOX message to be
365 eth_dev->rx_pkt_burst = nix_ptp_vf_burst;
373 cn9k_nix_timesync_enable(struct rte_eth_dev *eth_dev)
375 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
378 rc = cnxk_nix_timesync_enable(eth_dev);
382 dev->rx_offload_flags |= NIX_RX_OFFLOAD_TSTAMP_F;
383 dev->tx_offload_flags |= NIX_TX_OFFLOAD_TSTAMP_F;
385 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
386 nix_form_default_desc(dev, eth_dev->data->tx_queues[i], i);
388 /* Setting up the rx[tx]_offload_flags due to change
389 * in rx[tx]_offloads.
391 cn9k_eth_set_rx_function(eth_dev);
392 cn9k_eth_set_tx_function(eth_dev);
397 cn9k_nix_timesync_disable(struct rte_eth_dev *eth_dev)
399 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
402 rc = cnxk_nix_timesync_disable(eth_dev);
406 dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_TSTAMP_F;
407 dev->tx_offload_flags &= ~NIX_TX_OFFLOAD_TSTAMP_F;
409 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
410 nix_form_default_desc(dev, eth_dev->data->tx_queues[i], i);
412 /* Setting up the rx[tx]_offload_flags due to change
413 * in rx[tx]_offloads.
415 cn9k_eth_set_rx_function(eth_dev);
416 cn9k_eth_set_tx_function(eth_dev);
421 cn9k_nix_dev_start(struct rte_eth_dev *eth_dev)
423 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
424 struct roc_nix *nix = &dev->nix;
427 /* Common eth dev start */
428 rc = cnxk_nix_dev_start(eth_dev);
432 /* Update VF about data off shifted by 8 bytes if PTP already
433 * enabled in PF owning this VF
435 if (dev->ptp_en && (!roc_nix_is_pf(nix) && (!roc_nix_is_sdp(nix))))
436 nix_ptp_enable_vf(eth_dev);
438 /* Setting up the rx[tx]_offload_flags due to change
439 * in rx[tx]_offloads.
441 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
442 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
444 cn9k_eth_set_tx_function(eth_dev);
445 cn9k_eth_set_rx_function(eth_dev);
449 /* Update platform specific eth dev ops */
451 nix_eth_dev_ops_override(void)
453 static int init_once;
459 /* Update platform specific ops */
460 cnxk_eth_dev_ops.dev_configure = cn9k_nix_configure;
461 cnxk_eth_dev_ops.tx_queue_setup = cn9k_nix_tx_queue_setup;
462 cnxk_eth_dev_ops.rx_queue_setup = cn9k_nix_rx_queue_setup;
463 cnxk_eth_dev_ops.tx_queue_stop = cn9k_nix_tx_queue_stop;
464 cnxk_eth_dev_ops.dev_start = cn9k_nix_dev_start;
465 cnxk_eth_dev_ops.dev_ptypes_set = cn9k_nix_ptypes_set;
466 cnxk_eth_dev_ops.timesync_enable = cn9k_nix_timesync_enable;
467 cnxk_eth_dev_ops.timesync_disable = cn9k_nix_timesync_disable;
471 npc_flow_ops_override(void)
473 static int init_once;
479 /* Update platform specific ops */
480 cnxk_flow_ops.create = cn9k_flow_create;
481 cnxk_flow_ops.destroy = cn9k_flow_destroy;
485 cn9k_nix_remove(struct rte_pci_device *pci_dev)
487 return cnxk_nix_remove(pci_dev);
491 cn9k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
493 struct rte_eth_dev *eth_dev;
494 struct cnxk_eth_dev *dev;
497 if (RTE_CACHE_LINE_SIZE != 128) {
498 plt_err("Driver not compiled for CN9K");
504 plt_err("Failed to initialize platform model, rc=%d", rc);
508 nix_eth_dev_ops_override();
509 npc_flow_ops_override();
512 rc = cnxk_nix_probe(pci_drv, pci_dev);
516 /* Find eth dev allocated */
517 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
521 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
522 /* Setup callbacks for secondary process */
523 cn9k_eth_set_tx_function(eth_dev);
524 cn9k_eth_set_rx_function(eth_dev);
528 dev = cnxk_eth_pmd_priv(eth_dev);
529 /* Update capabilities already set for TSO.
530 * TSO not supported for earlier chip revisions
532 if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0())
533 dev->tx_offload_capa &= ~(DEV_TX_OFFLOAD_TCP_TSO |
534 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
535 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
536 DEV_TX_OFFLOAD_GRE_TNL_TSO);
538 /* 50G and 100G to be supported for board version C0
541 if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0()) {
542 dev->speed_capa &= ~(uint64_t)ETH_LINK_SPEED_50G;
543 dev->speed_capa &= ~(uint64_t)ETH_LINK_SPEED_100G;
548 /* Register up msg callbacks for PTP information */
549 roc_nix_ptp_info_cb_register(&dev->nix, cn9k_nix_ptp_info_update_cb);
551 /* Update HW erratas */
552 if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0())
557 static const struct rte_pci_id cn9k_pci_nix_map[] = {
563 static struct rte_pci_driver cn9k_pci_nix = {
564 .id_table = cn9k_pci_nix_map,
565 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
566 RTE_PCI_DRV_INTR_LSC,
567 .probe = cn9k_nix_probe,
568 .remove = cn9k_nix_remove,
571 RTE_PMD_REGISTER_PCI(net_cn9k, cn9k_pci_nix);
572 RTE_PMD_REGISTER_PCI_TABLE(net_cn9k, cn9k_pci_nix_map);
573 RTE_PMD_REGISTER_KMOD_DEP(net_cn9k, "vfio-pci");