drivers/net/cnxk/cn9k_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4 #include "cn9k_ethdev.h"
   5 #include "cn9k_rx.h"
   6 #include "cn9k_tx.h"
   7
   8 static int
   9 cn9k_nix_ptypes_set(struct rte_eth_dev *eth_dev, uint32_t ptype_mask)
  10 {
  11         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
  12
  13         if (ptype_mask) {
  14                 dev->rx_offload_flags |= NIX_RX_OFFLOAD_PTYPE_F;
  15                 dev->ptype_disable = 0;
  16         } else {
  17                 dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_PTYPE_F;
  18                 dev->ptype_disable = 1;
  19         }
  20
  21         return 0;
  22 }
  23
  24 static void
  25 nix_form_default_desc(struct cnxk_eth_dev *dev, struct cn9k_eth_txq *txq,
  26                       uint16_t qid)
  27 {
  28         struct nix_send_ext_s *send_hdr_ext;
  29         struct nix_send_hdr_s *send_hdr;
  30         union nix_send_sg_s *sg;
  31
  32         RTE_SET_USED(dev);
  33
  34         /* Initialize the fields based on basic single segment packet */
  35         memset(&txq->cmd, 0, sizeof(txq->cmd));
  36
  37         if (dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
  38                 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
  39                 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
  40                 send_hdr->w0.sizem1 = 2;
  41
  42                 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];
  43                 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
  44                 sg = (union nix_send_sg_s *)&txq->cmd[4];
  45         } else {
  46                 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
  47                 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
  48                 send_hdr->w0.sizem1 = 1;
  49                 sg = (union nix_send_sg_s *)&txq->cmd[2];
  50         }
  51
  52         send_hdr->w0.sq = qid;
  53         sg->subdc = NIX_SUBDC_SG;
  54         sg->segs = 1;
  55         sg->ld_type = NIX_SENDLDTYPE_LDD;
  56
  57         rte_wmb();
  58 }
  59
  60 static int
  61 cn9k_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
  62                         uint16_t nb_desc, unsigned int socket,
  63                         const struct rte_eth_txconf *tx_conf)
  64 {
  65         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
  66         struct cn9k_eth_txq *txq;
  67         struct roc_nix_sq *sq;
  68         int rc;
  69
  70         RTE_SET_USED(socket);
  71
  72         /* Common Tx queue setup */
  73         rc = cnxk_nix_tx_queue_setup(eth_dev, qid, nb_desc,
  74                                      sizeof(struct cn9k_eth_txq), tx_conf);
  75         if (rc)
  76                 return rc;
  77
  78         sq = &dev->sqs[qid];
  79         /* Update fast path queue */
  80         txq = eth_dev->data->tx_queues[qid];
  81         txq->fc_mem = sq->fc;
  82         txq->lmt_addr = sq->lmt_addr;
  83         txq->io_addr = sq->io_addr;
  84         txq->nb_sqb_bufs_adj = sq->nb_sqb_bufs_adj;
  85         txq->sqes_per_sqb_log2 = sq->sqes_per_sqb_log2;
  86
  87         nix_form_default_desc(dev, txq, qid);
  88         txq->lso_tun_fmt = dev->lso_tun_fmt;
  89         return 0;
  90 }
  91
  92 static int
  93 cn9k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
  94                         uint16_t nb_desc, unsigned int socket,
  95                         const struct rte_eth_rxconf *rx_conf,
  96                         struct rte_mempool *mp)
  97 {
  98         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
  99         struct cn9k_eth_rxq *rxq;
 100         struct roc_nix_rq *rq;
 101         struct roc_nix_cq *cq;
 102         int rc;
 103
 104         RTE_SET_USED(socket);
 105
 106         /* CQ Errata needs min 4K ring */
 107         if (dev->cq_min_4k && nb_desc < 4096)
 108                 nb_desc = 4096;
 109
 110         /* Common Rx queue setup */
 111         rc = cnxk_nix_rx_queue_setup(eth_dev, qid, nb_desc,
 112                                      sizeof(struct cn9k_eth_rxq), rx_conf, mp);
 113         if (rc)
 114                 return rc;
 115
 116         rq = &dev->rqs[qid];
 117         cq = &dev->cqs[qid];
 118
 119         /* Update fast path queue */
 120         rxq = eth_dev->data->rx_queues[qid];
 121         rxq->rq = qid;
 122         rxq->desc = (uintptr_t)cq->desc_base;
 123         rxq->cq_door = cq->door;
 124         rxq->cq_status = cq->status;
 125         rxq->wdata = cq->wdata;
 126         rxq->head = cq->head;
 127         rxq->qmask = cq->qmask;
 128
 129         /* Data offset from data to start of mbuf is first_skip */
 130         rxq->data_off = rq->first_skip;
 131         rxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev);
 132
 133         /* Lookup mem */
 134         rxq->lookup_mem = cnxk_nix_fastpath_lookup_mem_get();
 135         return 0;
 136 }
 137
 138 static int
 139 cn9k_nix_configure(struct rte_eth_dev *eth_dev)
 140 {
 141         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 142         struct rte_eth_conf *conf = &eth_dev->data->dev_conf;
 143         struct rte_eth_txmode *txmode = &conf->txmode;
 144         int rc;
 145
 146         /* Platform specific checks */
 147         if ((roc_model_is_cn96_a0() || roc_model_is_cn95_a0()) &&
 148             (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
 149             ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
 150              (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
 151                 plt_err("Outer IP and SCTP checksum unsupported");
 152                 return -EINVAL;
 153         }
 154
 155         /* Common nix configure */
 156         rc = cnxk_nix_configure(eth_dev);
 157         if (rc)
 158                 return rc;
 159
 160         plt_nix_dbg("Configured port%d platform specific rx_offload_flags=%x"
 161                     " tx_offload_flags=0x%x",
 162                     eth_dev->data->port_id, dev->rx_offload_flags,
 163                     dev->tx_offload_flags);
 164         return 0;
 165 }
 166
 167 /* Update platform specific eth dev ops */
 168 static void
 169 nix_eth_dev_ops_override(void)
 170 {
 171         static int init_once;
 172
 173         if (init_once)
 174                 return;
 175         init_once = 1;
 176
 177         /* Update platform specific ops */
 178         cnxk_eth_dev_ops.dev_configure = cn9k_nix_configure;
 179         cnxk_eth_dev_ops.tx_queue_setup = cn9k_nix_tx_queue_setup;
 180         cnxk_eth_dev_ops.rx_queue_setup = cn9k_nix_rx_queue_setup;
 181         cnxk_eth_dev_ops.dev_ptypes_set = cn9k_nix_ptypes_set;
 182 }
 183
 184 static int
 185 cn9k_nix_remove(struct rte_pci_device *pci_dev)
 186 {
 187         return cnxk_nix_remove(pci_dev);
 188 }
 189
 190 static int
 191 cn9k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
 192 {
 193         struct rte_eth_dev *eth_dev;
 194         struct cnxk_eth_dev *dev;
 195         int rc;
 196
 197         if (RTE_CACHE_LINE_SIZE != 128) {
 198                 plt_err("Driver not compiled for CN9K");
 199                 return -EFAULT;
 200         }
 201
 202         rc = roc_plt_init();
 203         if (rc) {
 204                 plt_err("Failed to initialize platform model, rc=%d", rc);
 205                 return rc;
 206         }
 207
 208         nix_eth_dev_ops_override();
 209
 210         /* Common probe */
 211         rc = cnxk_nix_probe(pci_drv, pci_dev);
 212         if (rc)
 213                 return rc;
 214
 215         /* Find eth dev allocated */
 216         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
 217         if (!eth_dev)
 218                 return -ENOENT;
 219
 220         dev = cnxk_eth_pmd_priv(eth_dev);
 221         /* Update capabilities already set for TSO.
 222          * TSO not supported for earlier chip revisions
 223          */
 224         if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0())
 225                 dev->tx_offload_capa &= ~(DEV_TX_OFFLOAD_TCP_TSO |
 226                                           DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 227                                           DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 228                                           DEV_TX_OFFLOAD_GRE_TNL_TSO);
 229
 230         /* 50G and 100G to be supported for board version C0
 231          * and above of CN9K.
 232          */
 233         if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0()) {
 234                 dev->speed_capa &= ~(uint64_t)ETH_LINK_SPEED_50G;
 235                 dev->speed_capa &= ~(uint64_t)ETH_LINK_SPEED_100G;
 236         }
 237
 238         dev->hwcap = 0;
 239
 240         /* Update HW erratas */
 241         if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0())
 242                 dev->cq_min_4k = 1;
 243         return 0;
 244 }
 245
 246 static const struct rte_pci_id cn9k_pci_nix_map[] = {
 247         {
 248                 .vendor_id = 0,
 249         },
 250 };
 251
 252 static struct rte_pci_driver cn9k_pci_nix = {
 253         .id_table = cn9k_pci_nix_map,
 254         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
 255                      RTE_PCI_DRV_INTR_LSC,
 256         .probe = cn9k_nix_probe,
 257         .remove = cn9k_nix_remove,
 258 };
 259
 260 RTE_PMD_REGISTER_PCI(net_cn9k, cn9k_pci_nix);
 261 RTE_PMD_REGISTER_PCI_TABLE(net_cn9k, cn9k_pci_nix_map);
 262 RTE_PMD_REGISTER_KMOD_DEP(net_cn9k, "vfio-pci");