1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
4 #include "cn9k_ethdev.h"
9 nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
11 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
12 struct rte_eth_dev_data *data = eth_dev->data;
13 struct rte_eth_conf *conf = &data->dev_conf;
14 struct rte_eth_rxmode *rxmode = &conf->rxmode;
17 if (rxmode->mq_mode == ETH_MQ_RX_RSS &&
18 (dev->rx_offloads & DEV_RX_OFFLOAD_RSS_HASH))
19 flags |= NIX_RX_OFFLOAD_RSS_F;
21 if (dev->rx_offloads &
22 (DEV_RX_OFFLOAD_TCP_CKSUM | DEV_RX_OFFLOAD_UDP_CKSUM))
23 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
25 if (dev->rx_offloads &
26 (DEV_RX_OFFLOAD_IPV4_CKSUM | DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM))
27 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
29 if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
30 flags |= NIX_RX_MULTI_SEG_F;
32 if (!dev->ptype_disable)
33 flags |= NIX_RX_OFFLOAD_PTYPE_F;
39 nix_tx_offload_flags(struct rte_eth_dev *eth_dev)
41 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
42 uint64_t conf = dev->tx_offloads;
45 /* Fastpath is dependent on these enums */
46 RTE_BUILD_BUG_ON(PKT_TX_TCP_CKSUM != (1ULL << 52));
47 RTE_BUILD_BUG_ON(PKT_TX_SCTP_CKSUM != (2ULL << 52));
48 RTE_BUILD_BUG_ON(PKT_TX_UDP_CKSUM != (3ULL << 52));
49 RTE_BUILD_BUG_ON(PKT_TX_IP_CKSUM != (1ULL << 54));
50 RTE_BUILD_BUG_ON(PKT_TX_IPV4 != (1ULL << 55));
51 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IP_CKSUM != (1ULL << 58));
52 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV4 != (1ULL << 59));
53 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV6 != (1ULL << 60));
54 RTE_BUILD_BUG_ON(PKT_TX_OUTER_UDP_CKSUM != (1ULL << 41));
55 RTE_BUILD_BUG_ON(RTE_MBUF_L2_LEN_BITS != 7);
56 RTE_BUILD_BUG_ON(RTE_MBUF_L3_LEN_BITS != 9);
57 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL2_LEN_BITS != 7);
58 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL3_LEN_BITS != 9);
59 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) !=
60 offsetof(struct rte_mbuf, buf_iova) + 8);
61 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
62 offsetof(struct rte_mbuf, buf_iova) + 16);
63 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
64 offsetof(struct rte_mbuf, ol_flags) + 12);
65 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, tx_offload) !=
66 offsetof(struct rte_mbuf, pool) + 2 * sizeof(void *));
68 if (conf & DEV_TX_OFFLOAD_VLAN_INSERT ||
69 conf & DEV_TX_OFFLOAD_QINQ_INSERT)
70 flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F;
72 if (conf & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
73 conf & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
74 flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F;
76 if (conf & DEV_TX_OFFLOAD_IPV4_CKSUM ||
77 conf & DEV_TX_OFFLOAD_TCP_CKSUM ||
78 conf & DEV_TX_OFFLOAD_UDP_CKSUM || conf & DEV_TX_OFFLOAD_SCTP_CKSUM)
79 flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F;
81 if (!(conf & DEV_TX_OFFLOAD_MBUF_FAST_FREE))
82 flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F;
84 if (conf & DEV_TX_OFFLOAD_MULTI_SEGS)
85 flags |= NIX_TX_MULTI_SEG_F;
87 /* Enable Inner checksum for TSO */
88 if (conf & DEV_TX_OFFLOAD_TCP_TSO)
89 flags |= (NIX_TX_OFFLOAD_TSO_F | NIX_TX_OFFLOAD_L3_L4_CSUM_F);
91 /* Enable Inner and Outer checksum for Tunnel TSO */
92 if (conf & (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
93 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | DEV_TX_OFFLOAD_GRE_TNL_TSO))
94 flags |= (NIX_TX_OFFLOAD_TSO_F | NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |
95 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
101 cn9k_nix_ptypes_set(struct rte_eth_dev *eth_dev, uint32_t ptype_mask)
103 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
106 dev->rx_offload_flags |= NIX_RX_OFFLOAD_PTYPE_F;
107 dev->ptype_disable = 0;
109 dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_PTYPE_F;
110 dev->ptype_disable = 1;
113 cn9k_eth_set_rx_function(eth_dev);
118 nix_form_default_desc(struct cnxk_eth_dev *dev, struct cn9k_eth_txq *txq,
121 struct nix_send_ext_s *send_hdr_ext;
122 struct nix_send_hdr_s *send_hdr;
123 union nix_send_sg_s *sg;
127 /* Initialize the fields based on basic single segment packet */
128 memset(&txq->cmd, 0, sizeof(txq->cmd));
130 if (dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
131 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
132 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
133 send_hdr->w0.sizem1 = 2;
135 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];
136 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
137 sg = (union nix_send_sg_s *)&txq->cmd[4];
139 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
140 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
141 send_hdr->w0.sizem1 = 1;
142 sg = (union nix_send_sg_s *)&txq->cmd[2];
145 send_hdr->w0.sq = qid;
146 sg->subdc = NIX_SUBDC_SG;
148 sg->ld_type = NIX_SENDLDTYPE_LDD;
154 cn9k_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
155 uint16_t nb_desc, unsigned int socket,
156 const struct rte_eth_txconf *tx_conf)
158 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
159 struct cn9k_eth_txq *txq;
160 struct roc_nix_sq *sq;
163 RTE_SET_USED(socket);
165 /* Common Tx queue setup */
166 rc = cnxk_nix_tx_queue_setup(eth_dev, qid, nb_desc,
167 sizeof(struct cn9k_eth_txq), tx_conf);
172 /* Update fast path queue */
173 txq = eth_dev->data->tx_queues[qid];
174 txq->fc_mem = sq->fc;
175 txq->lmt_addr = sq->lmt_addr;
176 txq->io_addr = sq->io_addr;
177 txq->nb_sqb_bufs_adj = sq->nb_sqb_bufs_adj;
178 txq->sqes_per_sqb_log2 = sq->sqes_per_sqb_log2;
180 nix_form_default_desc(dev, txq, qid);
181 txq->lso_tun_fmt = dev->lso_tun_fmt;
186 cn9k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
187 uint16_t nb_desc, unsigned int socket,
188 const struct rte_eth_rxconf *rx_conf,
189 struct rte_mempool *mp)
191 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
192 struct cn9k_eth_rxq *rxq;
193 struct roc_nix_rq *rq;
194 struct roc_nix_cq *cq;
197 RTE_SET_USED(socket);
199 /* CQ Errata needs min 4K ring */
200 if (dev->cq_min_4k && nb_desc < 4096)
203 /* Common Rx queue setup */
204 rc = cnxk_nix_rx_queue_setup(eth_dev, qid, nb_desc,
205 sizeof(struct cn9k_eth_rxq), rx_conf, mp);
212 /* Update fast path queue */
213 rxq = eth_dev->data->rx_queues[qid];
215 rxq->desc = (uintptr_t)cq->desc_base;
216 rxq->cq_door = cq->door;
217 rxq->cq_status = cq->status;
218 rxq->wdata = cq->wdata;
219 rxq->head = cq->head;
220 rxq->qmask = cq->qmask;
222 /* Data offset from data to start of mbuf is first_skip */
223 rxq->data_off = rq->first_skip;
224 rxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev);
227 rxq->lookup_mem = cnxk_nix_fastpath_lookup_mem_get();
232 cn9k_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
234 struct cn9k_eth_txq *txq = eth_dev->data->tx_queues[qidx];
237 rc = cnxk_nix_tx_queue_stop(eth_dev, qidx);
241 /* Clear fc cache pkts to trigger worker stop */
242 txq->fc_cache_pkts = 0;
247 cn9k_nix_configure(struct rte_eth_dev *eth_dev)
249 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
250 struct rte_eth_conf *conf = ð_dev->data->dev_conf;
251 struct rte_eth_txmode *txmode = &conf->txmode;
254 /* Platform specific checks */
255 if ((roc_model_is_cn96_a0() || roc_model_is_cn95_a0()) &&
256 (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
257 ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
258 (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
259 plt_err("Outer IP and SCTP checksum unsupported");
263 /* Common nix configure */
264 rc = cnxk_nix_configure(eth_dev);
268 /* Update offload flags */
269 dev->rx_offload_flags = nix_rx_offload_flags(eth_dev);
270 dev->tx_offload_flags = nix_tx_offload_flags(eth_dev);
272 plt_nix_dbg("Configured port%d platform specific rx_offload_flags=%x"
273 " tx_offload_flags=0x%x",
274 eth_dev->data->port_id, dev->rx_offload_flags,
275 dev->tx_offload_flags);
280 cn9k_nix_dev_start(struct rte_eth_dev *eth_dev)
282 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
285 /* Common eth dev start */
286 rc = cnxk_nix_dev_start(eth_dev);
290 /* Setting up the rx[tx]_offload_flags due to change
291 * in rx[tx]_offloads.
293 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
294 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
296 cn9k_eth_set_tx_function(eth_dev);
297 cn9k_eth_set_rx_function(eth_dev);
301 /* Update platform specific eth dev ops */
303 nix_eth_dev_ops_override(void)
305 static int init_once;
311 /* Update platform specific ops */
312 cnxk_eth_dev_ops.dev_configure = cn9k_nix_configure;
313 cnxk_eth_dev_ops.tx_queue_setup = cn9k_nix_tx_queue_setup;
314 cnxk_eth_dev_ops.rx_queue_setup = cn9k_nix_rx_queue_setup;
315 cnxk_eth_dev_ops.tx_queue_stop = cn9k_nix_tx_queue_stop;
316 cnxk_eth_dev_ops.dev_start = cn9k_nix_dev_start;
317 cnxk_eth_dev_ops.dev_ptypes_set = cn9k_nix_ptypes_set;
321 cn9k_nix_remove(struct rte_pci_device *pci_dev)
323 return cnxk_nix_remove(pci_dev);
327 cn9k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
329 struct rte_eth_dev *eth_dev;
330 struct cnxk_eth_dev *dev;
333 if (RTE_CACHE_LINE_SIZE != 128) {
334 plt_err("Driver not compiled for CN9K");
340 plt_err("Failed to initialize platform model, rc=%d", rc);
344 nix_eth_dev_ops_override();
347 rc = cnxk_nix_probe(pci_drv, pci_dev);
351 /* Find eth dev allocated */
352 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
356 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
357 /* Setup callbacks for secondary process */
358 cn9k_eth_set_tx_function(eth_dev);
359 cn9k_eth_set_rx_function(eth_dev);
363 dev = cnxk_eth_pmd_priv(eth_dev);
364 /* Update capabilities already set for TSO.
365 * TSO not supported for earlier chip revisions
367 if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0())
368 dev->tx_offload_capa &= ~(DEV_TX_OFFLOAD_TCP_TSO |
369 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
370 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
371 DEV_TX_OFFLOAD_GRE_TNL_TSO);
373 /* 50G and 100G to be supported for board version C0
376 if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0()) {
377 dev->speed_capa &= ~(uint64_t)ETH_LINK_SPEED_50G;
378 dev->speed_capa &= ~(uint64_t)ETH_LINK_SPEED_100G;
383 /* Update HW erratas */
384 if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0())
389 static const struct rte_pci_id cn9k_pci_nix_map[] = {
395 static struct rte_pci_driver cn9k_pci_nix = {
396 .id_table = cn9k_pci_nix_map,
397 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
398 RTE_PCI_DRV_INTR_LSC,
399 .probe = cn9k_nix_probe,
400 .remove = cn9k_nix_remove,
403 RTE_PMD_REGISTER_PCI(net_cn9k, cn9k_pci_nix);
404 RTE_PMD_REGISTER_PCI_TABLE(net_cn9k, cn9k_pci_nix_map);
405 RTE_PMD_REGISTER_KMOD_DEP(net_cn9k, "vfio-pci");