drivers/net/cnxk/cn9k_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4 #include "cn9k_ethdev.h"
   5
   6 static int
   7 cn9k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
   8                         uint16_t nb_desc, unsigned int socket,
   9                         const struct rte_eth_rxconf *rx_conf,
  10                         struct rte_mempool *mp)
  11 {
  12         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
  13         struct cn9k_eth_rxq *rxq;
  14         struct roc_nix_rq *rq;
  15         struct roc_nix_cq *cq;
  16         int rc;
  17
  18         RTE_SET_USED(socket);
  19
  20         /* CQ Errata needs min 4K ring */
  21         if (dev->cq_min_4k && nb_desc < 4096)
  22                 nb_desc = 4096;
  23
  24         /* Common Rx queue setup */
  25         rc = cnxk_nix_rx_queue_setup(eth_dev, qid, nb_desc,
  26                                      sizeof(struct cn9k_eth_rxq), rx_conf, mp);
  27         if (rc)
  28                 return rc;
  29
  30         rq = &dev->rqs[qid];
  31         cq = &dev->cqs[qid];
  32
  33         /* Update fast path queue */
  34         rxq = eth_dev->data->rx_queues[qid];
  35         rxq->rq = qid;
  36         rxq->desc = (uintptr_t)cq->desc_base;
  37         rxq->cq_door = cq->door;
  38         rxq->cq_status = cq->status;
  39         rxq->wdata = cq->wdata;
  40         rxq->head = cq->head;
  41         rxq->qmask = cq->qmask;
  42
  43         /* Data offset from data to start of mbuf is first_skip */
  44         rxq->data_off = rq->first_skip;
  45         rxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev);
  46         return 0;
  47 }
  48
  49 static int
  50 cn9k_nix_configure(struct rte_eth_dev *eth_dev)
  51 {
  52         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
  53         struct rte_eth_conf *conf = &eth_dev->data->dev_conf;
  54         struct rte_eth_txmode *txmode = &conf->txmode;
  55         int rc;
  56
  57         /* Platform specific checks */
  58         if ((roc_model_is_cn96_a0() || roc_model_is_cn95_a0()) &&
  59             (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
  60             ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
  61              (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
  62                 plt_err("Outer IP and SCTP checksum unsupported");
  63                 return -EINVAL;
  64         }
  65
  66         /* Common nix configure */
  67         rc = cnxk_nix_configure(eth_dev);
  68         if (rc)
  69                 return rc;
  70
  71         plt_nix_dbg("Configured port%d platform specific rx_offload_flags=%x"
  72                     " tx_offload_flags=0x%x",
  73                     eth_dev->data->port_id, dev->rx_offload_flags,
  74                     dev->tx_offload_flags);
  75         return 0;
  76 }
  77
  78 /* Update platform specific eth dev ops */
  79 static void
  80 nix_eth_dev_ops_override(void)
  81 {
  82         static int init_once;
  83
  84         if (init_once)
  85                 return;
  86         init_once = 1;
  87
  88         /* Update platform specific ops */
  89         cnxk_eth_dev_ops.dev_configure = cn9k_nix_configure;
  90         cnxk_eth_dev_ops.rx_queue_setup = cn9k_nix_rx_queue_setup;
  91 }
  92
  93 static int
  94 cn9k_nix_remove(struct rte_pci_device *pci_dev)
  95 {
  96         return cnxk_nix_remove(pci_dev);
  97 }
  98
  99 static int
 100 cn9k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
 101 {
 102         struct rte_eth_dev *eth_dev;
 103         struct cnxk_eth_dev *dev;
 104         int rc;
 105
 106         if (RTE_CACHE_LINE_SIZE != 128) {
 107                 plt_err("Driver not compiled for CN9K");
 108                 return -EFAULT;
 109         }
 110
 111         rc = roc_plt_init();
 112         if (rc) {
 113                 plt_err("Failed to initialize platform model, rc=%d", rc);
 114                 return rc;
 115         }
 116
 117         nix_eth_dev_ops_override();
 118
 119         /* Common probe */
 120         rc = cnxk_nix_probe(pci_drv, pci_dev);
 121         if (rc)
 122                 return rc;
 123
 124         /* Find eth dev allocated */
 125         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
 126         if (!eth_dev)
 127                 return -ENOENT;
 128
 129         dev = cnxk_eth_pmd_priv(eth_dev);
 130         /* Update capabilities already set for TSO.
 131          * TSO not supported for earlier chip revisions
 132          */
 133         if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0())
 134                 dev->tx_offload_capa &= ~(DEV_TX_OFFLOAD_TCP_TSO |
 135                                           DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 136                                           DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 137                                           DEV_TX_OFFLOAD_GRE_TNL_TSO);
 138
 139         /* 50G and 100G to be supported for board version C0
 140          * and above of CN9K.
 141          */
 142         if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0()) {
 143                 dev->speed_capa &= ~(uint64_t)ETH_LINK_SPEED_50G;
 144                 dev->speed_capa &= ~(uint64_t)ETH_LINK_SPEED_100G;
 145         }
 146
 147         dev->hwcap = 0;
 148
 149         /* Update HW erratas */
 150         if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0())
 151                 dev->cq_min_4k = 1;
 152         return 0;
 153 }
 154
 155 static const struct rte_pci_id cn9k_pci_nix_map[] = {
 156         {
 157                 .vendor_id = 0,
 158         },
 159 };
 160
 161 static struct rte_pci_driver cn9k_pci_nix = {
 162         .id_table = cn9k_pci_nix_map,
 163         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
 164                      RTE_PCI_DRV_INTR_LSC,
 165         .probe = cn9k_nix_probe,
 166         .remove = cn9k_nix_remove,
 167 };
 168
 169 RTE_PMD_REGISTER_PCI(net_cn9k, cn9k_pci_nix);
 170 RTE_PMD_REGISTER_PCI_TABLE(net_cn9k, cn9k_pci_nix_map);
 171 RTE_PMD_REGISTER_KMOD_DEP(net_cn9k, "vfio-pci");