drivers/net/cnxk/cn9k_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4 #include "cn9k_ethdev.h"
   5
   6 static int
   7 cn9k_nix_remove(struct rte_pci_device *pci_dev)
   8 {
   9         return cnxk_nix_remove(pci_dev);
  10 }
  11
  12 static int
  13 cn9k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
  14 {
  15         struct rte_eth_dev *eth_dev;
  16         struct cnxk_eth_dev *dev;
  17         int rc;
  18
  19         if (RTE_CACHE_LINE_SIZE != 128) {
  20                 plt_err("Driver not compiled for CN9K");
  21                 return -EFAULT;
  22         }
  23
  24         rc = roc_plt_init();
  25         if (rc) {
  26                 plt_err("Failed to initialize platform model, rc=%d", rc);
  27                 return rc;
  28         }
  29
  30         /* Common probe */
  31         rc = cnxk_nix_probe(pci_drv, pci_dev);
  32         if (rc)
  33                 return rc;
  34
  35         /* Find eth dev allocated */
  36         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
  37         if (!eth_dev)
  38                 return -ENOENT;
  39
  40         dev = cnxk_eth_pmd_priv(eth_dev);
  41         /* Update capabilities already set for TSO.
  42          * TSO not supported for earlier chip revisions
  43          */
  44         if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0())
  45                 dev->tx_offload_capa &= ~(DEV_TX_OFFLOAD_TCP_TSO |
  46                                           DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
  47                                           DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
  48                                           DEV_TX_OFFLOAD_GRE_TNL_TSO);
  49
  50         /* 50G and 100G to be supported for board version C0
  51          * and above of CN9K.
  52          */
  53         if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0()) {
  54                 dev->speed_capa &= ~(uint64_t)ETH_LINK_SPEED_50G;
  55                 dev->speed_capa &= ~(uint64_t)ETH_LINK_SPEED_100G;
  56         }
  57
  58         dev->hwcap = 0;
  59
  60         /* Update HW erratas */
  61         if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0())
  62                 dev->cq_min_4k = 1;
  63         return 0;
  64 }
  65
  66 static const struct rte_pci_id cn9k_pci_nix_map[] = {
  67         {
  68                 .vendor_id = 0,
  69         },
  70 };
  71
  72 static struct rte_pci_driver cn9k_pci_nix = {
  73         .id_table = cn9k_pci_nix_map,
  74         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
  75                      RTE_PCI_DRV_INTR_LSC,
  76         .probe = cn9k_nix_probe,
  77         .remove = cn9k_nix_remove,
  78 };
  79
  80 RTE_PMD_REGISTER_PCI(net_cn9k, cn9k_pci_nix);
  81 RTE_PMD_REGISTER_PCI_TABLE(net_cn9k, cn9k_pci_nix_map);
  82 RTE_PMD_REGISTER_KMOD_DEP(net_cn9k, "vfio-pci");