1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
4 #include "cn9k_ethdev.h"
7 cn9k_nix_configure(struct rte_eth_dev *eth_dev)
9 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
10 struct rte_eth_conf *conf = ð_dev->data->dev_conf;
11 struct rte_eth_txmode *txmode = &conf->txmode;
14 /* Platform specific checks */
15 if ((roc_model_is_cn96_a0() || roc_model_is_cn95_a0()) &&
16 (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
17 ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
18 (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
19 plt_err("Outer IP and SCTP checksum unsupported");
23 /* Common nix configure */
24 rc = cnxk_nix_configure(eth_dev);
28 plt_nix_dbg("Configured port%d platform specific rx_offload_flags=%x"
29 " tx_offload_flags=0x%x",
30 eth_dev->data->port_id, dev->rx_offload_flags,
31 dev->tx_offload_flags);
35 /* Update platform specific eth dev ops */
37 nix_eth_dev_ops_override(void)
45 /* Update platform specific ops */
46 cnxk_eth_dev_ops.dev_configure = cn9k_nix_configure;
50 cn9k_nix_remove(struct rte_pci_device *pci_dev)
52 return cnxk_nix_remove(pci_dev);
56 cn9k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
58 struct rte_eth_dev *eth_dev;
59 struct cnxk_eth_dev *dev;
62 if (RTE_CACHE_LINE_SIZE != 128) {
63 plt_err("Driver not compiled for CN9K");
69 plt_err("Failed to initialize platform model, rc=%d", rc);
73 nix_eth_dev_ops_override();
76 rc = cnxk_nix_probe(pci_drv, pci_dev);
80 /* Find eth dev allocated */
81 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
85 dev = cnxk_eth_pmd_priv(eth_dev);
86 /* Update capabilities already set for TSO.
87 * TSO not supported for earlier chip revisions
89 if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0())
90 dev->tx_offload_capa &= ~(DEV_TX_OFFLOAD_TCP_TSO |
91 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
92 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
93 DEV_TX_OFFLOAD_GRE_TNL_TSO);
95 /* 50G and 100G to be supported for board version C0
98 if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0()) {
99 dev->speed_capa &= ~(uint64_t)ETH_LINK_SPEED_50G;
100 dev->speed_capa &= ~(uint64_t)ETH_LINK_SPEED_100G;
105 /* Update HW erratas */
106 if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0())
111 static const struct rte_pci_id cn9k_pci_nix_map[] = {
117 static struct rte_pci_driver cn9k_pci_nix = {
118 .id_table = cn9k_pci_nix_map,
119 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
120 RTE_PCI_DRV_INTR_LSC,
121 .probe = cn9k_nix_probe,
122 .remove = cn9k_nix_remove,
125 RTE_PMD_REGISTER_PCI(net_cn9k, cn9k_pci_nix);
126 RTE_PMD_REGISTER_PCI_TABLE(net_cn9k, cn9k_pci_nix_map);
127 RTE_PMD_REGISTER_KMOD_DEP(net_cn9k, "vfio-pci");