1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
4 #include <cnxk_ethdev.h>
7 nix_get_rx_offload_capa(struct cnxk_eth_dev *dev)
9 uint64_t capa = CNXK_NIX_RX_OFFLOAD_CAPA;
11 if (roc_nix_is_vf_or_sdp(&dev->nix) ||
12 dev->npc.switch_header_type == ROC_PRIV_FLAGS_HIGIG)
13 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
18 static inline uint64_t
19 nix_get_tx_offload_capa(struct cnxk_eth_dev *dev)
22 return CNXK_NIX_TX_OFFLOAD_CAPA;
25 static inline uint32_t
26 nix_get_speed_capa(struct cnxk_eth_dev *dev)
30 /* Auto negotiation disabled */
31 speed_capa = ETH_LINK_SPEED_FIXED;
32 if (!roc_nix_is_vf_or_sdp(&dev->nix) && !roc_nix_is_lbk(&dev->nix)) {
33 speed_capa |= ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
34 ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
35 ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
42 nix_enable_mseg_on_jumbo(struct cnxk_eth_rxq_sp *rxq)
44 struct rte_pktmbuf_pool_private *mbp_priv;
45 struct rte_eth_dev *eth_dev;
46 struct cnxk_eth_dev *dev;
50 eth_dev = dev->eth_dev;
52 /* Get rx buffer size */
53 mbp_priv = rte_mempool_get_priv(rxq->qconf.mp);
54 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
56 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buffsz) {
57 dev->rx_offloads |= DEV_RX_OFFLOAD_SCATTER;
58 dev->tx_offloads |= DEV_TX_OFFLOAD_MULTI_SEGS;
63 nix_recalc_mtu(struct rte_eth_dev *eth_dev)
65 struct rte_eth_dev_data *data = eth_dev->data;
66 struct cnxk_eth_rxq_sp *rxq;
70 rxq = ((struct cnxk_eth_rxq_sp *)data->rx_queues[0]) - 1;
71 /* Setup scatter mode if needed by jumbo */
72 nix_enable_mseg_on_jumbo(rxq);
74 /* Setup MTU based on max_rx_pkt_len */
75 mtu = data->dev_conf.rxmode.max_rx_pkt_len - CNXK_NIX_L2_OVERHEAD +
76 CNXK_NIX_MAX_VTAG_ACT_SIZE;
78 rc = cnxk_nix_mtu_set(eth_dev, mtu);
80 plt_err("Failed to set default MTU size, rc=%d", rc);
86 nix_init_flow_ctrl_config(struct rte_eth_dev *eth_dev)
88 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
89 struct cnxk_fc_cfg *fc = &dev->fc_cfg;
90 struct rte_eth_fc_conf fc_conf = {0};
93 /* Both Rx & Tx flow ctrl get enabled(RTE_FC_FULL) in HW
94 * by AF driver, update those info in PMD structure.
96 rc = cnxk_nix_flow_ctrl_get(eth_dev, &fc_conf);
100 fc->mode = fc_conf.mode;
101 fc->rx_pause = (fc_conf.mode == RTE_FC_FULL) ||
102 (fc_conf.mode == RTE_FC_RX_PAUSE);
103 fc->tx_pause = (fc_conf.mode == RTE_FC_FULL) ||
104 (fc_conf.mode == RTE_FC_TX_PAUSE);
111 nix_update_flow_ctrl_config(struct rte_eth_dev *eth_dev)
113 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
114 struct cnxk_fc_cfg *fc = &dev->fc_cfg;
115 struct rte_eth_fc_conf fc_cfg = {0};
117 if (roc_nix_is_vf_or_sdp(&dev->nix))
120 fc_cfg.mode = fc->mode;
122 /* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */
123 if (roc_model_is_cn96_ax() &&
124 dev->npc.switch_header_type != ROC_PRIV_FLAGS_HIGIG &&
125 (fc_cfg.mode == RTE_FC_FULL || fc_cfg.mode == RTE_FC_RX_PAUSE)) {
127 (fc_cfg.mode == RTE_FC_FULL ||
128 fc_cfg.mode == RTE_FC_TX_PAUSE) ?
129 RTE_FC_TX_PAUSE : RTE_FC_NONE;
132 return cnxk_nix_flow_ctrl_set(eth_dev, &fc_cfg);
136 cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev)
138 uint16_t port_id = dev->eth_dev->data->port_id;
139 struct rte_mbuf mb_def;
142 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
143 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
144 offsetof(struct rte_mbuf, data_off) !=
146 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
147 offsetof(struct rte_mbuf, data_off) !=
149 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
150 offsetof(struct rte_mbuf, data_off) !=
153 mb_def.data_off = RTE_PKTMBUF_HEADROOM;
154 mb_def.port = port_id;
155 rte_mbuf_refcnt_set(&mb_def, 1);
157 /* Prevent compiler reordering: rearm_data covers previous fields */
158 rte_compiler_barrier();
159 tmp = (uint64_t *)&mb_def.rearm_data;
164 static inline uint8_t
165 nix_sq_max_sqe_sz(struct cnxk_eth_dev *dev)
168 * Maximum three segments can be supported with W8, Choose
169 * NIX_MAXSQESZ_W16 for multi segment offload.
171 if (dev->tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
172 return NIX_MAXSQESZ_W16;
174 return NIX_MAXSQESZ_W8;
178 cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
179 uint16_t nb_desc, uint16_t fp_tx_q_sz,
180 const struct rte_eth_txconf *tx_conf)
182 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
183 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
184 struct cnxk_eth_txq_sp *txq_sp;
185 struct roc_nix_sq *sq;
189 /* Free memory prior to re-allocation if needed. */
190 if (eth_dev->data->tx_queues[qid] != NULL) {
191 plt_nix_dbg("Freeing memory prior to re-allocation %d", qid);
192 dev_ops->tx_queue_release(eth_dev->data->tx_queues[qid]);
193 eth_dev->data->tx_queues[qid] = NULL;
199 sq->nb_desc = nb_desc;
200 sq->max_sqe_sz = nix_sq_max_sqe_sz(dev);
202 rc = roc_nix_sq_init(&dev->nix, sq);
204 plt_err("Failed to init sq=%d, rc=%d", qid, rc);
209 txq_sz = sizeof(struct cnxk_eth_txq_sp) + fp_tx_q_sz;
210 txq_sp = plt_zmalloc(txq_sz, PLT_CACHE_LINE_SIZE);
212 plt_err("Failed to alloc tx queue mem");
213 rc |= roc_nix_sq_fini(sq);
219 txq_sp->qconf.conf.tx = *tx_conf;
220 txq_sp->qconf.nb_desc = nb_desc;
222 plt_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " lmt_addr=%p"
223 " nb_sqb_bufs=%d sqes_per_sqb_log2=%d",
224 qid, sq->fc, dev->tx_offloads, sq->lmt_addr,
225 sq->nb_sqb_bufs, sq->sqes_per_sqb_log2);
227 /* Store start of fast path area */
228 eth_dev->data->tx_queues[qid] = txq_sp + 1;
229 eth_dev->data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
234 cnxk_nix_tx_queue_release(void *txq)
236 struct cnxk_eth_txq_sp *txq_sp;
237 struct cnxk_eth_dev *dev;
238 struct roc_nix_sq *sq;
245 txq_sp = cnxk_eth_txq_to_sp(txq);
249 plt_nix_dbg("Releasing txq %u", qid);
253 rc = roc_nix_sq_fini(sq);
255 plt_err("Failed to cleanup sq, rc=%d", rc);
262 cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
263 uint16_t nb_desc, uint16_t fp_rx_q_sz,
264 const struct rte_eth_rxconf *rx_conf,
265 struct rte_mempool *mp)
267 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
268 struct cnxk_eth_rxq_sp *rxq_sp;
269 struct rte_mempool_ops *ops;
270 const char *platform_ops;
271 struct roc_nix_rq *rq;
272 struct roc_nix_cq *cq;
278 if (rx_conf->rx_deferred_start == 1) {
279 plt_err("Deferred Rx start is not supported");
283 platform_ops = rte_mbuf_platform_mempool_ops();
284 /* This driver needs cnxk_npa mempool ops to work */
285 ops = rte_mempool_get_ops(mp->ops_index);
286 if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
287 plt_err("mempool ops should be of cnxk_npa type");
291 if (mp->pool_id == 0) {
292 plt_err("Invalid pool_id");
296 /* Free memory prior to re-allocation if needed */
297 if (eth_dev->data->rx_queues[qid] != NULL) {
298 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
300 plt_nix_dbg("Freeing memory prior to re-allocation %d", qid);
301 dev_ops->rx_queue_release(eth_dev->data->rx_queues[qid]);
302 eth_dev->data->rx_queues[qid] = NULL;
308 cq->nb_desc = nb_desc;
309 rc = roc_nix_cq_init(&dev->nix, cq);
311 plt_err("Failed to init roc cq for rq=%d, rc=%d", qid, rc);
318 rq->aura_handle = mp->pool_id;
319 rq->flow_tag_width = 32;
322 /* Calculate first mbuf skip */
323 first_skip = (sizeof(struct rte_mbuf));
324 first_skip += RTE_PKTMBUF_HEADROOM;
325 first_skip += rte_pktmbuf_priv_size(mp);
326 rq->first_skip = first_skip;
327 rq->later_skip = sizeof(struct rte_mbuf);
328 rq->lpb_size = mp->elt_size;
330 rc = roc_nix_rq_init(&dev->nix, rq, !!eth_dev->data->dev_started);
332 plt_err("Failed to init roc rq for rq=%d, rc=%d", qid, rc);
336 /* Allocate and setup fast path rx queue */
338 rxq_sz = sizeof(struct cnxk_eth_rxq_sp) + fp_rx_q_sz;
339 rxq_sp = plt_zmalloc(rxq_sz, PLT_CACHE_LINE_SIZE);
341 plt_err("Failed to alloc rx queue for rq=%d", qid);
345 /* Setup slow path fields */
348 rxq_sp->qconf.conf.rx = *rx_conf;
349 rxq_sp->qconf.nb_desc = nb_desc;
350 rxq_sp->qconf.mp = mp;
352 plt_nix_dbg("rq=%d pool=%s nb_desc=%d->%d", qid, mp->name, nb_desc,
355 /* Store start of fast path area */
356 eth_dev->data->rx_queues[qid] = rxq_sp + 1;
357 eth_dev->data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
361 rc |= roc_nix_rq_fini(rq);
363 rc |= roc_nix_cq_fini(cq);
369 cnxk_nix_rx_queue_release(void *rxq)
371 struct cnxk_eth_rxq_sp *rxq_sp;
372 struct cnxk_eth_dev *dev;
373 struct roc_nix_rq *rq;
374 struct roc_nix_cq *cq;
381 rxq_sp = cnxk_eth_rxq_to_sp(rxq);
385 plt_nix_dbg("Releasing rxq %u", qid);
389 rc = roc_nix_rq_fini(rq);
391 plt_err("Failed to cleanup rq, rc=%d", rc);
395 rc = roc_nix_cq_fini(cq);
397 plt_err("Failed to cleanup cq, rc=%d", rc);
399 /* Finally free fast path area */
404 cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
407 uint32_t flow_key_type[RSS_MAX_LEVELS][6] = {
408 {FLOW_KEY_TYPE_IPV4, FLOW_KEY_TYPE_IPV6, FLOW_KEY_TYPE_TCP,
409 FLOW_KEY_TYPE_UDP, FLOW_KEY_TYPE_SCTP, FLOW_KEY_TYPE_ETH_DMAC},
410 {FLOW_KEY_TYPE_INNR_IPV4, FLOW_KEY_TYPE_INNR_IPV6,
411 FLOW_KEY_TYPE_INNR_TCP, FLOW_KEY_TYPE_INNR_UDP,
412 FLOW_KEY_TYPE_INNR_SCTP, FLOW_KEY_TYPE_INNR_ETH_DMAC},
413 {FLOW_KEY_TYPE_IPV4 | FLOW_KEY_TYPE_INNR_IPV4,
414 FLOW_KEY_TYPE_IPV6 | FLOW_KEY_TYPE_INNR_IPV6,
415 FLOW_KEY_TYPE_TCP | FLOW_KEY_TYPE_INNR_TCP,
416 FLOW_KEY_TYPE_UDP | FLOW_KEY_TYPE_INNR_UDP,
417 FLOW_KEY_TYPE_SCTP | FLOW_KEY_TYPE_INNR_SCTP,
418 FLOW_KEY_TYPE_ETH_DMAC | FLOW_KEY_TYPE_INNR_ETH_DMAC}
420 uint32_t flowkey_cfg = 0;
422 dev->ethdev_rss_hf = ethdev_rss;
424 if (ethdev_rss & ETH_RSS_L2_PAYLOAD &&
425 dev->npc.switch_header_type == ROC_PRIV_FLAGS_LEN_90B) {
426 flowkey_cfg |= FLOW_KEY_TYPE_CH_LEN_90B;
429 if (ethdev_rss & ETH_RSS_C_VLAN)
430 flowkey_cfg |= FLOW_KEY_TYPE_VLAN;
432 if (ethdev_rss & ETH_RSS_L3_SRC_ONLY)
433 flowkey_cfg |= FLOW_KEY_TYPE_L3_SRC;
435 if (ethdev_rss & ETH_RSS_L3_DST_ONLY)
436 flowkey_cfg |= FLOW_KEY_TYPE_L3_DST;
438 if (ethdev_rss & ETH_RSS_L4_SRC_ONLY)
439 flowkey_cfg |= FLOW_KEY_TYPE_L4_SRC;
441 if (ethdev_rss & ETH_RSS_L4_DST_ONLY)
442 flowkey_cfg |= FLOW_KEY_TYPE_L4_DST;
444 if (ethdev_rss & RSS_IPV4_ENABLE)
445 flowkey_cfg |= flow_key_type[rss_level][RSS_IPV4_INDEX];
447 if (ethdev_rss & RSS_IPV6_ENABLE)
448 flowkey_cfg |= flow_key_type[rss_level][RSS_IPV6_INDEX];
450 if (ethdev_rss & ETH_RSS_TCP)
451 flowkey_cfg |= flow_key_type[rss_level][RSS_TCP_INDEX];
453 if (ethdev_rss & ETH_RSS_UDP)
454 flowkey_cfg |= flow_key_type[rss_level][RSS_UDP_INDEX];
456 if (ethdev_rss & ETH_RSS_SCTP)
457 flowkey_cfg |= flow_key_type[rss_level][RSS_SCTP_INDEX];
459 if (ethdev_rss & ETH_RSS_L2_PAYLOAD)
460 flowkey_cfg |= flow_key_type[rss_level][RSS_DMAC_INDEX];
462 if (ethdev_rss & RSS_IPV6_EX_ENABLE)
463 flowkey_cfg |= FLOW_KEY_TYPE_IPV6_EXT;
465 if (ethdev_rss & ETH_RSS_PORT)
466 flowkey_cfg |= FLOW_KEY_TYPE_PORT;
468 if (ethdev_rss & ETH_RSS_NVGRE)
469 flowkey_cfg |= FLOW_KEY_TYPE_NVGRE;
471 if (ethdev_rss & ETH_RSS_VXLAN)
472 flowkey_cfg |= FLOW_KEY_TYPE_VXLAN;
474 if (ethdev_rss & ETH_RSS_GENEVE)
475 flowkey_cfg |= FLOW_KEY_TYPE_GENEVE;
477 if (ethdev_rss & ETH_RSS_GTPU)
478 flowkey_cfg |= FLOW_KEY_TYPE_GTPU;
484 nix_free_queue_mem(struct cnxk_eth_dev *dev)
495 nix_rss_default_setup(struct cnxk_eth_dev *dev)
497 struct rte_eth_dev *eth_dev = dev->eth_dev;
498 uint8_t rss_hash_level;
499 uint32_t flowkey_cfg;
502 rss_hf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
503 rss_hash_level = ETH_RSS_LEVEL(rss_hf);
507 flowkey_cfg = cnxk_rss_ethdev_to_nix(dev, rss_hf, rss_hash_level);
508 return roc_nix_rss_default_setup(&dev->nix, flowkey_cfg);
512 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
514 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
515 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
516 struct cnxk_eth_qconf *tx_qconf = NULL;
517 struct cnxk_eth_qconf *rx_qconf = NULL;
518 struct cnxk_eth_rxq_sp *rxq_sp;
519 struct cnxk_eth_txq_sp *txq_sp;
520 int i, nb_rxq, nb_txq;
523 nb_rxq = RTE_MIN(dev->nb_rxq, eth_dev->data->nb_rx_queues);
524 nb_txq = RTE_MIN(dev->nb_txq, eth_dev->data->nb_tx_queues);
526 tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
527 if (tx_qconf == NULL) {
528 plt_err("Failed to allocate memory for tx_qconf");
532 rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
533 if (rx_qconf == NULL) {
534 plt_err("Failed to allocate memory for rx_qconf");
538 txq = eth_dev->data->tx_queues;
539 for (i = 0; i < nb_txq; i++) {
540 if (txq[i] == NULL) {
541 tx_qconf[i].valid = false;
542 plt_info("txq[%d] is already released", i);
545 txq_sp = cnxk_eth_txq_to_sp(txq[i]);
546 memcpy(&tx_qconf[i], &txq_sp->qconf, sizeof(*tx_qconf));
547 tx_qconf[i].valid = true;
548 dev_ops->tx_queue_release(txq[i]);
549 eth_dev->data->tx_queues[i] = NULL;
552 rxq = eth_dev->data->rx_queues;
553 for (i = 0; i < nb_rxq; i++) {
554 if (rxq[i] == NULL) {
555 rx_qconf[i].valid = false;
556 plt_info("rxq[%d] is already released", i);
559 rxq_sp = cnxk_eth_rxq_to_sp(rxq[i]);
560 memcpy(&rx_qconf[i], &rxq_sp->qconf, sizeof(*rx_qconf));
561 rx_qconf[i].valid = true;
562 dev_ops->rx_queue_release(rxq[i]);
563 eth_dev->data->rx_queues[i] = NULL;
566 dev->tx_qconf = tx_qconf;
567 dev->rx_qconf = rx_qconf;
577 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
579 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
580 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
581 struct cnxk_eth_qconf *tx_qconf = dev->tx_qconf;
582 struct cnxk_eth_qconf *rx_qconf = dev->rx_qconf;
583 int rc, i, nb_rxq, nb_txq;
586 nb_rxq = RTE_MIN(dev->nb_rxq, eth_dev->data->nb_rx_queues);
587 nb_txq = RTE_MIN(dev->nb_txq, eth_dev->data->nb_tx_queues);
590 /* Setup tx & rx queues with previous configuration so
591 * that the queues can be functional in cases like ports
592 * are started without re configuring queues.
594 * Usual re config sequence is like below:
600 * queue_configure() {
607 * In some application's control path, queue_configure() would
608 * NOT be invoked for TXQs/RXQs in port_configure().
609 * In such cases, queues can be functional after start as the
610 * queues are already setup in port_configure().
612 for (i = 0; i < nb_txq; i++) {
613 if (!tx_qconf[i].valid)
615 rc = dev_ops->tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc, 0,
616 &tx_qconf[i].conf.tx);
618 plt_err("Failed to setup tx queue rc=%d", rc);
619 txq = eth_dev->data->tx_queues;
620 for (i -= 1; i >= 0; i--)
621 dev_ops->tx_queue_release(txq[i]);
629 for (i = 0; i < nb_rxq; i++) {
630 if (!rx_qconf[i].valid)
632 rc = dev_ops->rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc, 0,
633 &rx_qconf[i].conf.rx,
636 plt_err("Failed to setup rx queue rc=%d", rc);
637 rxq = eth_dev->data->rx_queues;
638 for (i -= 1; i >= 0; i--)
639 dev_ops->rx_queue_release(rxq[i]);
640 goto tx_queue_release;
650 txq = eth_dev->data->tx_queues;
651 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
652 dev_ops->tx_queue_release(txq[i]);
663 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
673 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
675 /* These dummy functions are required for supporting
676 * some applications which reconfigure queues without
677 * stopping tx burst and rx burst threads(eg kni app)
678 * When the queues context is saved, txq/rxqs are released
679 * which caused app crash since rx/tx burst is still
680 * on different lcores
682 eth_dev->tx_pkt_burst = nix_eth_nop_burst;
683 eth_dev->rx_pkt_burst = nix_eth_nop_burst;
688 nix_lso_tun_fmt_update(struct cnxk_eth_dev *dev)
690 uint8_t udp_tun[ROC_NIX_LSO_TUN_MAX];
691 uint8_t tun[ROC_NIX_LSO_TUN_MAX];
692 struct roc_nix *nix = &dev->nix;
695 rc = roc_nix_lso_fmt_get(nix, udp_tun, tun);
699 dev->lso_tun_fmt = ((uint64_t)tun[ROC_NIX_LSO_TUN_V4V4] |
700 (uint64_t)tun[ROC_NIX_LSO_TUN_V4V6] << 8 |
701 (uint64_t)tun[ROC_NIX_LSO_TUN_V6V4] << 16 |
702 (uint64_t)tun[ROC_NIX_LSO_TUN_V6V6] << 24);
704 dev->lso_tun_fmt |= ((uint64_t)udp_tun[ROC_NIX_LSO_TUN_V4V4] << 32 |
705 (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V4V6] << 40 |
706 (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V6V4] << 48 |
707 (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V6V6] << 56);
712 nix_lso_fmt_setup(struct cnxk_eth_dev *dev)
714 struct roc_nix *nix = &dev->nix;
717 /* Nothing much to do if offload is not enabled */
718 if (!(dev->tx_offloads &
719 (DEV_TX_OFFLOAD_TCP_TSO | DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
720 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | DEV_TX_OFFLOAD_GRE_TNL_TSO)))
723 /* Setup LSO formats in AF. Its a no-op if other ethdev has
726 rc = roc_nix_lso_fmt_setup(nix);
730 return nix_lso_tun_fmt_update(dev);
734 cnxk_nix_configure(struct rte_eth_dev *eth_dev)
736 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
737 struct rte_eth_dev_data *data = eth_dev->data;
738 struct rte_eth_conf *conf = &data->dev_conf;
739 struct rte_eth_rxmode *rxmode = &conf->rxmode;
740 struct rte_eth_txmode *txmode = &conf->txmode;
741 char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
742 struct roc_nix_fc_cfg fc_cfg = {0};
743 struct roc_nix *nix = &dev->nix;
744 struct rte_ether_addr *ea;
745 uint8_t nb_rxq, nb_txq;
753 if (rte_eal_has_hugepages() == 0) {
754 plt_err("Huge page is not configured");
758 if (conf->dcb_capability_en == 1) {
759 plt_err("dcb enable is not supported");
763 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
764 plt_err("Flow director is not supported");
768 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
769 rxmode->mq_mode != ETH_MQ_RX_RSS) {
770 plt_err("Unsupported mq rx mode %d", rxmode->mq_mode);
774 if (txmode->mq_mode != ETH_MQ_TX_NONE) {
775 plt_err("Unsupported mq tx mode %d", txmode->mq_mode);
779 /* Free the resources allocated from the previous configure */
780 if (dev->configured == 1) {
781 /* Unregister queue irq's */
782 roc_nix_unregister_queue_irqs(nix);
784 /* Unregister CQ irqs if present */
785 if (eth_dev->data->dev_conf.intr_conf.rxq)
786 roc_nix_unregister_cq_irqs(nix);
788 /* Set no-op functions */
789 nix_set_nop_rxtx_function(eth_dev);
790 /* Store queue config for later */
791 rc = nix_store_queue_cfg_and_then_release(eth_dev);
794 roc_nix_tm_fini(nix);
795 roc_nix_lf_free(nix);
798 dev->rx_offloads = rxmode->offloads;
799 dev->tx_offloads = txmode->offloads;
802 rx_cfg = ROC_NIX_LF_RX_CFG_DIS_APAD;
803 if (dev->rx_offloads &
804 (DEV_RX_OFFLOAD_TCP_CKSUM | DEV_RX_OFFLOAD_UDP_CKSUM)) {
805 rx_cfg |= ROC_NIX_LF_RX_CFG_CSUM_OL4;
806 rx_cfg |= ROC_NIX_LF_RX_CFG_CSUM_IL4;
808 rx_cfg |= (ROC_NIX_LF_RX_CFG_DROP_RE | ROC_NIX_LF_RX_CFG_L2_LEN_ERR |
809 ROC_NIX_LF_RX_CFG_LEN_IL4 | ROC_NIX_LF_RX_CFG_LEN_IL3 |
810 ROC_NIX_LF_RX_CFG_LEN_OL4 | ROC_NIX_LF_RX_CFG_LEN_OL3);
812 nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
813 nb_txq = RTE_MAX(data->nb_tx_queues, 1);
816 rc = roc_nix_lf_alloc(nix, nb_rxq, nb_txq, rx_cfg);
818 plt_err("Failed to init nix_lf rc=%d", rc);
822 dev->npc.channel = roc_nix_get_base_chan(nix);
824 nb_rxq = data->nb_rx_queues;
825 nb_txq = data->nb_tx_queues;
828 /* Allocate memory for roc rq's and cq's */
829 qs = plt_zmalloc(sizeof(struct roc_nix_rq) * nb_rxq, 0);
831 plt_err("Failed to alloc rqs");
836 qs = plt_zmalloc(sizeof(struct roc_nix_cq) * nb_rxq, 0);
838 plt_err("Failed to alloc cqs");
845 /* Allocate memory for roc sq's */
846 qs = plt_zmalloc(sizeof(struct roc_nix_sq) * nb_txq, 0);
848 plt_err("Failed to alloc sqs");
854 /* Re-enable NIX LF error interrupts */
855 roc_nix_err_intr_ena_dis(nix, true);
856 roc_nix_ras_intr_ena_dis(nix, true);
858 if (nix->rx_ptp_ena &&
859 dev->npc.switch_header_type == ROC_PRIV_FLAGS_HIGIG) {
860 plt_err("Both PTP and switch header enabled");
864 rc = roc_nix_switch_hdr_set(nix, dev->npc.switch_header_type);
866 plt_err("Failed to enable switch type nix_lf rc=%d", rc);
870 /* Setup LSO if needed */
871 rc = nix_lso_fmt_setup(dev);
873 plt_err("Failed to setup nix lso format fields, rc=%d", rc);
878 rc = nix_rss_default_setup(dev);
880 plt_err("Failed to configure rss rc=%d", rc);
884 /* Init the default TM scheduler hierarchy */
885 rc = roc_nix_tm_init(nix);
887 plt_err("Failed to init traffic manager, rc=%d", rc);
891 rc = roc_nix_tm_hierarchy_enable(nix, ROC_NIX_TM_DEFAULT, false);
893 plt_err("Failed to enable default tm hierarchy, rc=%d", rc);
897 /* Register queue IRQs */
898 rc = roc_nix_register_queue_irqs(nix);
900 plt_err("Failed to register queue interrupts rc=%d", rc);
904 /* Register cq IRQs */
905 if (eth_dev->data->dev_conf.intr_conf.rxq) {
906 if (eth_dev->data->nb_rx_queues > dev->nix.cints) {
907 plt_err("Rx interrupt cannot be enabled, rxq > %d",
911 /* Rx interrupt feature cannot work with vector mode because,
912 * vector mode does not process packets unless min 4 pkts are
913 * received, while cq interrupts are generated even for 1 pkt
916 dev->scalar_ena = true;
918 rc = roc_nix_register_cq_irqs(nix);
920 plt_err("Failed to register CQ interrupts rc=%d", rc);
925 /* Configure loop back mode */
926 rc = roc_nix_mac_loopback_enable(nix,
927 eth_dev->data->dev_conf.lpbk_mode);
929 plt_err("Failed to configure cgx loop back mode rc=%d", rc);
933 /* Init flow control configuration */
934 fc_cfg.cq_cfg_valid = false;
935 fc_cfg.rxchan_cfg.enable = true;
936 rc = roc_nix_fc_config_set(nix, &fc_cfg);
938 plt_err("Failed to initialize flow control rc=%d", rc);
942 /* Update flow control configuration to PMD */
943 rc = nix_init_flow_ctrl_config(eth_dev);
945 plt_err("Failed to initialize flow control rc=%d", rc);
949 * Restore queue config when reconfigure followed by
950 * reconfigure and no queue configure invoked from application case.
952 if (dev->configured == 1) {
953 rc = nix_restore_queue_cfg(eth_dev);
958 /* Update the mac address */
959 ea = eth_dev->data->mac_addrs;
960 memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
961 if (rte_is_zero_ether_addr(ea))
962 rte_eth_random_addr((uint8_t *)ea);
964 rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
966 plt_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
967 " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 "",
968 eth_dev->data->port_id, ea_fmt, nb_rxq, nb_txq,
969 dev->rx_offloads, dev->tx_offloads);
973 dev->nb_rxq = data->nb_rx_queues;
974 dev->nb_txq = data->nb_tx_queues;
978 roc_nix_unregister_cq_irqs(nix);
980 roc_nix_unregister_queue_irqs(nix);
982 roc_nix_tm_fini(nix);
984 nix_free_queue_mem(dev);
985 rc |= roc_nix_lf_free(nix);
992 cnxk_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid)
994 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
995 struct rte_eth_dev_data *data = eth_dev->data;
996 struct roc_nix_sq *sq = &dev->sqs[qid];
999 if (data->tx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STARTED)
1002 rc = roc_nix_tm_sq_aura_fc(sq, true);
1004 plt_err("Failed to enable sq aura fc, txq=%u, rc=%d", qid, rc);
1008 data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STARTED;
1014 cnxk_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid)
1016 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1017 struct rte_eth_dev_data *data = eth_dev->data;
1018 struct roc_nix_sq *sq = &dev->sqs[qid];
1021 if (data->tx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STOPPED)
1024 rc = roc_nix_tm_sq_aura_fc(sq, false);
1026 plt_err("Failed to disable sqb aura fc, txq=%u, rc=%d", qid,
1031 data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
1037 cnxk_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid)
1039 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1040 struct rte_eth_dev_data *data = eth_dev->data;
1041 struct roc_nix_rq *rq = &dev->rqs[qid];
1044 if (data->rx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STARTED)
1047 rc = roc_nix_rq_ena_dis(rq, true);
1049 plt_err("Failed to enable rxq=%u, rc=%d", qid, rc);
1053 data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STARTED;
1059 cnxk_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid)
1061 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1062 struct rte_eth_dev_data *data = eth_dev->data;
1063 struct roc_nix_rq *rq = &dev->rqs[qid];
1066 if (data->rx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STOPPED)
1069 rc = roc_nix_rq_ena_dis(rq, false);
1071 plt_err("Failed to disable rxq=%u, rc=%d", qid, rc);
1075 data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
1081 cnxk_nix_dev_stop(struct rte_eth_dev *eth_dev)
1083 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1084 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
1085 struct rte_mbuf *rx_pkts[32];
1086 int count, i, j, rc;
1089 /* Disable switch hdr pkind */
1090 roc_nix_switch_hdr_set(&dev->nix, 0);
1092 /* Stop link change events */
1093 if (!roc_nix_is_vf_or_sdp(&dev->nix))
1094 roc_nix_mac_link_event_start_stop(&dev->nix, false);
1096 /* Disable Rx via NPC */
1097 roc_nix_npc_rx_ena_dis(&dev->nix, false);
1099 /* Stop rx queues and free up pkts pending */
1100 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1101 rc = dev_ops->rx_queue_stop(eth_dev, i);
1105 rxq = eth_dev->data->rx_queues[i];
1106 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1108 for (j = 0; j < count; j++)
1109 rte_pktmbuf_free(rx_pkts[j]);
1110 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1114 /* Stop tx queues */
1115 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1116 dev_ops->tx_queue_stop(eth_dev, i);
1122 cnxk_nix_dev_start(struct rte_eth_dev *eth_dev)
1124 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1127 if (eth_dev->data->nb_rx_queues != 0) {
1128 rc = nix_recalc_mtu(eth_dev);
1133 /* Start rx queues */
1134 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1135 rc = cnxk_nix_rx_queue_start(eth_dev, i);
1140 /* Start tx queues */
1141 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1142 rc = cnxk_nix_tx_queue_start(eth_dev, i);
1147 /* Update Flow control configuration */
1148 rc = nix_update_flow_ctrl_config(eth_dev);
1150 plt_err("Failed to enable flow control. error code(%d)", rc);
1154 /* Enable Rx in NPC */
1155 rc = roc_nix_npc_rx_ena_dis(&dev->nix, true);
1157 plt_err("Failed to enable NPC rx %d", rc);
1161 cnxk_nix_toggle_flag_link_cfg(dev, true);
1163 /* Start link change events */
1164 if (!roc_nix_is_vf_or_sdp(&dev->nix)) {
1165 rc = roc_nix_mac_link_event_start_stop(&dev->nix, true);
1167 plt_err("Failed to start cgx link event %d", rc);
1172 cnxk_nix_toggle_flag_link_cfg(dev, false);
1177 roc_nix_npc_rx_ena_dis(&dev->nix, false);
1178 cnxk_nix_toggle_flag_link_cfg(dev, false);
1182 static int cnxk_nix_dev_reset(struct rte_eth_dev *eth_dev);
1183 static int cnxk_nix_dev_close(struct rte_eth_dev *eth_dev);
1185 /* CNXK platform independent eth dev ops */
1186 struct eth_dev_ops cnxk_eth_dev_ops = {
1187 .mtu_set = cnxk_nix_mtu_set,
1188 .mac_addr_add = cnxk_nix_mac_addr_add,
1189 .mac_addr_remove = cnxk_nix_mac_addr_del,
1190 .mac_addr_set = cnxk_nix_mac_addr_set,
1191 .dev_infos_get = cnxk_nix_info_get,
1192 .link_update = cnxk_nix_link_update,
1193 .tx_queue_release = cnxk_nix_tx_queue_release,
1194 .rx_queue_release = cnxk_nix_rx_queue_release,
1195 .dev_stop = cnxk_nix_dev_stop,
1196 .dev_close = cnxk_nix_dev_close,
1197 .dev_reset = cnxk_nix_dev_reset,
1198 .tx_queue_start = cnxk_nix_tx_queue_start,
1199 .rx_queue_start = cnxk_nix_rx_queue_start,
1200 .rx_queue_stop = cnxk_nix_rx_queue_stop,
1201 .dev_supported_ptypes_get = cnxk_nix_supported_ptypes_get,
1202 .promiscuous_enable = cnxk_nix_promisc_enable,
1203 .promiscuous_disable = cnxk_nix_promisc_disable,
1204 .allmulticast_enable = cnxk_nix_allmulticast_enable,
1205 .allmulticast_disable = cnxk_nix_allmulticast_disable,
1206 .rx_burst_mode_get = cnxk_nix_rx_burst_mode_get,
1207 .tx_burst_mode_get = cnxk_nix_tx_burst_mode_get,
1208 .flow_ctrl_get = cnxk_nix_flow_ctrl_get,
1209 .flow_ctrl_set = cnxk_nix_flow_ctrl_set,
1210 .dev_set_link_up = cnxk_nix_set_link_up,
1211 .dev_set_link_down = cnxk_nix_set_link_down,
1212 .get_module_info = cnxk_nix_get_module_info,
1213 .get_module_eeprom = cnxk_nix_get_module_eeprom,
1214 .rx_queue_intr_enable = cnxk_nix_rx_queue_intr_enable,
1215 .rx_queue_intr_disable = cnxk_nix_rx_queue_intr_disable,
1216 .pool_ops_supported = cnxk_nix_pool_ops_supported,
1217 .queue_stats_mapping_set = cnxk_nix_queue_stats_mapping,
1218 .stats_get = cnxk_nix_stats_get,
1219 .stats_reset = cnxk_nix_stats_reset,
1220 .xstats_get = cnxk_nix_xstats_get,
1221 .xstats_get_names = cnxk_nix_xstats_get_names,
1222 .xstats_reset = cnxk_nix_xstats_reset,
1223 .xstats_get_by_id = cnxk_nix_xstats_get_by_id,
1224 .xstats_get_names_by_id = cnxk_nix_xstats_get_names_by_id,
1225 .fw_version_get = cnxk_nix_fw_version_get,
1226 .rxq_info_get = cnxk_nix_rxq_info_get,
1227 .txq_info_get = cnxk_nix_txq_info_get,
1228 .tx_done_cleanup = cnxk_nix_tx_done_cleanup,
1229 .flow_ops_get = cnxk_nix_flow_ops_get,
1230 .get_reg = cnxk_nix_dev_get_reg,
1234 cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)
1236 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1237 struct roc_nix *nix = &dev->nix;
1238 struct rte_pci_device *pci_dev;
1239 int rc, max_entries;
1241 eth_dev->dev_ops = &cnxk_eth_dev_ops;
1243 /* For secondary processes, the primary has done all the work */
1244 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1247 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1248 rte_eth_copy_pci_info(eth_dev, pci_dev);
1250 /* Parse devargs string */
1251 rc = cnxk_ethdev_parse_devargs(eth_dev->device->devargs, dev);
1253 plt_err("Failed to parse devargs rc=%d", rc);
1257 /* Initialize base roc nix */
1258 nix->pci_dev = pci_dev;
1259 rc = roc_nix_dev_init(nix);
1261 plt_err("Failed to initialize roc nix rc=%d", rc);
1265 /* Register up msg callbacks */
1266 roc_nix_mac_link_cb_register(nix, cnxk_eth_dev_link_status_cb);
1268 dev->eth_dev = eth_dev;
1269 dev->configured = 0;
1270 dev->ptype_disable = 0;
1272 /* For vfs, returned max_entries will be 0. but to keep default mac
1273 * address, one entry must be allocated. so setting up to 1.
1275 if (roc_nix_is_vf_or_sdp(nix))
1278 max_entries = roc_nix_mac_max_entries_get(nix);
1280 if (max_entries <= 0) {
1281 plt_err("Failed to get max entries for mac addr");
1286 eth_dev->data->mac_addrs =
1287 rte_zmalloc("mac_addr", max_entries * RTE_ETHER_ADDR_LEN, 0);
1288 if (eth_dev->data->mac_addrs == NULL) {
1289 plt_err("Failed to allocate memory for mac addr");
1294 dev->max_mac_entries = max_entries;
1296 /* Get mac address */
1297 rc = roc_nix_npc_mac_addr_get(nix, dev->mac_addr);
1299 plt_err("Failed to get mac addr, rc=%d", rc);
1300 goto free_mac_addrs;
1303 /* Update the mac address */
1304 memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1306 if (!roc_nix_is_vf_or_sdp(nix)) {
1307 /* Sync same MAC address to CGX/RPM table */
1308 rc = roc_nix_mac_addr_set(nix, dev->mac_addr);
1310 plt_err("Failed to set mac addr, rc=%d", rc);
1311 goto free_mac_addrs;
1315 /* Union of all capabilities supported by CNXK.
1316 * Platform specific capabilities will be
1319 dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
1320 dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
1321 dev->speed_capa = nix_get_speed_capa(dev);
1323 /* Initialize roc npc */
1324 dev->npc.roc_nix = nix;
1325 rc = roc_npc_init(&dev->npc);
1327 goto free_mac_addrs;
1329 plt_nix_dbg("Port=%d pf=%d vf=%d ver=%s hwcap=0x%" PRIx64
1330 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
1331 eth_dev->data->port_id, roc_nix_get_pf(nix),
1332 roc_nix_get_vf(nix), CNXK_ETH_DEV_PMD_VERSION, dev->hwcap,
1333 dev->rx_offload_capa, dev->tx_offload_capa);
1337 rte_free(eth_dev->data->mac_addrs);
1339 roc_nix_dev_fini(nix);
1341 plt_err("Failed to init nix eth_dev rc=%d", rc);
1346 cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool reset)
1348 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1349 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
1350 struct roc_nix *nix = &dev->nix;
1353 /* Nothing to be done for secondary processes */
1354 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1357 /* Clear the flag since we are closing down */
1358 dev->configured = 0;
1360 roc_nix_npc_rx_ena_dis(nix, false);
1362 /* Disable and free rte_flow entries */
1363 roc_npc_fini(&dev->npc);
1365 /* Disable link status events */
1366 roc_nix_mac_link_event_start_stop(nix, false);
1369 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1370 dev_ops->tx_queue_release(eth_dev->data->tx_queues[i]);
1371 eth_dev->data->tx_queues[i] = NULL;
1373 eth_dev->data->nb_tx_queues = 0;
1375 /* Free up RQ's and CQ's */
1376 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1377 dev_ops->rx_queue_release(eth_dev->data->rx_queues[i]);
1378 eth_dev->data->rx_queues[i] = NULL;
1380 eth_dev->data->nb_rx_queues = 0;
1382 /* Free tm resources */
1383 roc_nix_tm_fini(nix);
1385 /* Unregister queue irqs */
1386 roc_nix_unregister_queue_irqs(nix);
1388 /* Unregister cq irqs */
1389 if (eth_dev->data->dev_conf.intr_conf.rxq)
1390 roc_nix_unregister_cq_irqs(nix);
1392 /* Free ROC RQ's, SQ's and CQ's memory */
1393 nix_free_queue_mem(dev);
1395 /* Free nix lf resources */
1396 rc = roc_nix_lf_free(nix);
1398 plt_err("Failed to free nix lf, rc=%d", rc);
1400 rte_free(eth_dev->data->mac_addrs);
1401 eth_dev->data->mac_addrs = NULL;
1403 rc = roc_nix_dev_fini(nix);
1404 /* Can be freed later by PMD if NPA LF is in use */
1405 if (rc == -EAGAIN) {
1407 eth_dev->data->dev_private = NULL;
1410 plt_err("Failed in nix dev fini, rc=%d", rc);
1417 cnxk_nix_dev_close(struct rte_eth_dev *eth_dev)
1419 cnxk_eth_dev_uninit(eth_dev, false);
1424 cnxk_nix_dev_reset(struct rte_eth_dev *eth_dev)
1428 rc = cnxk_eth_dev_uninit(eth_dev, true);
1432 return cnxk_eth_dev_init(eth_dev);
1436 cnxk_nix_remove(struct rte_pci_device *pci_dev)
1438 struct rte_eth_dev *eth_dev;
1439 struct roc_nix *nix;
1442 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
1444 /* Cleanup eth dev */
1445 rc = cnxk_eth_dev_uninit(eth_dev, false);
1449 rte_eth_dev_release_port(eth_dev);
1452 /* Nothing to be done for secondary processes */
1453 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1456 /* Check if this device is hosting common resource */
1457 nix = roc_idev_npa_nix_get();
1458 if (nix->pci_dev != pci_dev)
1461 /* Try nix fini now */
1462 rc = roc_nix_dev_fini(nix);
1463 if (rc == -EAGAIN) {
1464 plt_info("%s: common resource in use by other devices",
1468 plt_err("Failed in nix dev fini, rc=%d", rc);
1472 /* Free device pointer as rte_ethdev does not have it anymore */
1479 cnxk_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1483 RTE_SET_USED(pci_drv);
1485 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct cnxk_eth_dev),
1488 /* On error on secondary, recheck if port exists in primary or
1489 * in mid of detach state.
1491 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
1492 if (!rte_eth_dev_allocated(pci_dev->device.name))