drivers/net/cnxk/cnxk_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4 #include <cnxk_ethdev.h>
   5
   6 static inline uint64_t
   7 nix_get_rx_offload_capa(struct cnxk_eth_dev *dev)
   8 {
   9         uint64_t capa = CNXK_NIX_RX_OFFLOAD_CAPA;
  10
  11         if (roc_nix_is_vf_or_sdp(&dev->nix) ||
  12             dev->npc.switch_header_type == ROC_PRIV_FLAGS_HIGIG)
  13                 capa &= ~RTE_ETH_RX_OFFLOAD_TIMESTAMP;
  14
  15         return capa;
  16 }
  17
  18 static inline uint64_t
  19 nix_get_tx_offload_capa(struct cnxk_eth_dev *dev)
  20 {
  21         RTE_SET_USED(dev);
  22         return CNXK_NIX_TX_OFFLOAD_CAPA;
  23 }
  24
  25 static inline uint32_t
  26 nix_get_speed_capa(struct cnxk_eth_dev *dev)
  27 {
  28         uint32_t speed_capa;
  29
  30         /* Auto negotiation disabled */
  31         speed_capa = RTE_ETH_LINK_SPEED_FIXED;
  32         if (!roc_nix_is_vf_or_sdp(&dev->nix) && !roc_nix_is_lbk(&dev->nix)) {
  33                 speed_capa |= RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G |
  34                               RTE_ETH_LINK_SPEED_25G | RTE_ETH_LINK_SPEED_40G |
  35                               RTE_ETH_LINK_SPEED_50G | RTE_ETH_LINK_SPEED_100G;
  36         }
  37
  38         return speed_capa;
  39 }
  40
  41 int
  42 cnxk_nix_inb_mode_set(struct cnxk_eth_dev *dev, bool use_inl_dev)
  43 {
  44         struct roc_nix *nix = &dev->nix;
  45
  46         if (dev->inb.inl_dev == use_inl_dev)
  47                 return 0;
  48
  49         plt_nix_dbg("Security sessions(%u) still active, inl=%u!!!",
  50                     dev->inb.nb_sess, !!dev->inb.inl_dev);
  51
  52         /* Change the mode */
  53         dev->inb.inl_dev = use_inl_dev;
  54
  55         /* Update RoC for NPC rule insertion */
  56         roc_nix_inb_mode_set(nix, use_inl_dev);
  57
  58         /* Setup lookup mem */
  59         return cnxk_nix_lookup_mem_sa_base_set(dev);
  60 }
  61
  62 static int
  63 nix_security_setup(struct cnxk_eth_dev *dev)
  64 {
  65         struct roc_nix *nix = &dev->nix;
  66         int i, rc = 0;
  67
  68         if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
  69                 /* Setup Inline Inbound */
  70                 rc = roc_nix_inl_inb_init(nix);
  71                 if (rc) {
  72                         plt_err("Failed to initialize nix inline inb, rc=%d",
  73                                 rc);
  74                         return rc;
  75                 }
  76
  77                 /* By default pick using inline device for poll mode.
  78                  * Will be overridden when event mode rq's are setup.
  79                  */
  80                 cnxk_nix_inb_mode_set(dev, true);
  81
  82                 /* Allocate memory to be used as dptr for CPT ucode
  83                  * WRITE_SA op.
  84                  */
  85                 dev->inb.sa_dptr =
  86                         plt_zmalloc(ROC_NIX_INL_OT_IPSEC_INB_HW_SZ, 0);
  87                 if (!dev->inb.sa_dptr) {
  88                         plt_err("Couldn't allocate memory for SA dptr");
  89                         rc = -ENOMEM;
  90                         goto cleanup;
  91                 }
  92         }
  93
  94         if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY ||
  95             dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
  96                 struct plt_bitmap *bmap;
  97                 size_t bmap_sz;
  98                 void *mem;
  99
 100                 /* Setup enough descriptors for all tx queues */
 101                 nix->outb_nb_desc = dev->outb.nb_desc;
 102                 nix->outb_nb_crypto_qs = dev->outb.nb_crypto_qs;
 103
 104                 /* Setup Inline Outbound */
 105                 rc = roc_nix_inl_outb_init(nix);
 106                 if (rc) {
 107                         plt_err("Failed to initialize nix inline outb, rc=%d",
 108                                 rc);
 109                         goto sa_dptr_free;
 110                 }
 111
 112                 dev->outb.lf_base = roc_nix_inl_outb_lf_base_get(nix);
 113
 114                 /* Skip the rest if DEV_TX_OFFLOAD_SECURITY is not enabled */
 115                 if (!(dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY))
 116                         return 0;
 117
 118                 /* Allocate memory to be used as dptr for CPT ucode
 119                  * WRITE_SA op.
 120                  */
 121                 dev->outb.sa_dptr =
 122                         plt_zmalloc(ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ, 0);
 123                 if (!dev->outb.sa_dptr) {
 124                         plt_err("Couldn't allocate memory for SA dptr");
 125                         rc = -ENOMEM;
 126                         goto sa_dptr_free;
 127                 }
 128
 129                 rc = -ENOMEM;
 130                 /* Allocate a bitmap to alloc and free sa indexes */
 131                 bmap_sz = plt_bitmap_get_memory_footprint(dev->outb.max_sa);
 132                 mem = plt_zmalloc(bmap_sz, PLT_CACHE_LINE_SIZE);
 133                 if (mem == NULL) {
 134                         plt_err("Outbound SA bmap alloc failed");
 135
 136                         rc |= roc_nix_inl_outb_fini(nix);
 137                         goto sa_dptr_free;
 138                 }
 139
 140                 rc = -EIO;
 141                 bmap = plt_bitmap_init(dev->outb.max_sa, mem, bmap_sz);
 142                 if (!bmap) {
 143                         plt_err("Outbound SA bmap init failed");
 144
 145                         rc |= roc_nix_inl_outb_fini(nix);
 146                         plt_free(mem);
 147                         goto sa_dptr_free;
 148                 }
 149
 150                 for (i = 0; i < dev->outb.max_sa; i++)
 151                         plt_bitmap_set(bmap, i);
 152
 153                 dev->outb.sa_base = roc_nix_inl_outb_sa_base_get(nix);
 154                 dev->outb.sa_bmap_mem = mem;
 155                 dev->outb.sa_bmap = bmap;
 156         }
 157         return 0;
 158
 159 sa_dptr_free:
 160         if (dev->inb.sa_dptr)
 161                 plt_free(dev->inb.sa_dptr);
 162         if (dev->outb.sa_dptr)
 163                 plt_free(dev->outb.sa_dptr);
 164 cleanup:
 165         if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)
 166                 rc |= roc_nix_inl_inb_fini(nix);
 167         return rc;
 168 }
 169
 170 static int
 171 nix_meter_fini(struct cnxk_eth_dev *dev)
 172 {
 173         struct cnxk_meter_node *next_mtr = NULL;
 174         struct roc_nix_bpf_objs profs = {0};
 175         struct cnxk_meter_node *mtr = NULL;
 176         struct cnxk_mtr *fms = &dev->mtr;
 177         struct roc_nix *nix = &dev->nix;
 178         struct roc_nix_rq *rq;
 179         uint32_t i;
 180         int rc;
 181
 182         RTE_TAILQ_FOREACH_SAFE(mtr, fms, next, next_mtr) {
 183                 for (i = 0; i < mtr->rq_num; i++) {
 184                         rq = &dev->rqs[mtr->rq_id[i]];
 185                         rc |= roc_nix_bpf_ena_dis(nix, mtr->bpf_id, rq, false);
 186                 }
 187
 188                 profs.level = mtr->level;
 189                 profs.count = 1;
 190                 profs.ids[0] = mtr->bpf_id;
 191                 rc = roc_nix_bpf_free(nix, &profs, 1);
 192
 193                 if (rc)
 194                         return rc;
 195
 196                 TAILQ_REMOVE(fms, mtr, next);
 197                 plt_free(mtr);
 198         }
 199         return 0;
 200 }
 201
 202 static int
 203 nix_security_release(struct cnxk_eth_dev *dev)
 204 {
 205         struct rte_eth_dev *eth_dev = dev->eth_dev;
 206         struct cnxk_eth_sec_sess *eth_sec, *tvar;
 207         struct roc_nix *nix = &dev->nix;
 208         int rc, ret = 0;
 209
 210         /* Cleanup Inline inbound */
 211         if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
 212                 /* Destroy inbound sessions */
 213                 tvar = NULL;
 214                 RTE_TAILQ_FOREACH_SAFE(eth_sec, &dev->inb.list, entry, tvar)
 215                         cnxk_eth_sec_ops.session_destroy(eth_dev,
 216                                                          eth_sec->sess);
 217
 218                 /* Clear lookup mem */
 219                 cnxk_nix_lookup_mem_sa_base_clear(dev);
 220
 221                 rc = roc_nix_inl_inb_fini(nix);
 222                 if (rc)
 223                         plt_err("Failed to cleanup nix inline inb, rc=%d", rc);
 224                 ret |= rc;
 225
 226                 if (dev->inb.sa_dptr) {
 227                         plt_free(dev->inb.sa_dptr);
 228                         dev->inb.sa_dptr = NULL;
 229                 }
 230         }
 231
 232         /* Cleanup Inline outbound */
 233         if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY ||
 234             dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
 235                 /* Destroy outbound sessions */
 236                 tvar = NULL;
 237                 RTE_TAILQ_FOREACH_SAFE(eth_sec, &dev->outb.list, entry, tvar)
 238                         cnxk_eth_sec_ops.session_destroy(eth_dev,
 239                                                          eth_sec->sess);
 240
 241                 rc = roc_nix_inl_outb_fini(nix);
 242                 if (rc)
 243                         plt_err("Failed to cleanup nix inline outb, rc=%d", rc);
 244                 ret |= rc;
 245
 246                 plt_bitmap_free(dev->outb.sa_bmap);
 247                 plt_free(dev->outb.sa_bmap_mem);
 248                 dev->outb.sa_bmap = NULL;
 249                 dev->outb.sa_bmap_mem = NULL;
 250                 if (dev->outb.sa_dptr) {
 251                         plt_free(dev->outb.sa_dptr);
 252                         dev->outb.sa_dptr = NULL;
 253                 }
 254         }
 255
 256         dev->inb.inl_dev = false;
 257         roc_nix_inb_mode_set(nix, false);
 258         dev->nb_rxq_sso = 0;
 259         dev->inb.nb_sess = 0;
 260         dev->outb.nb_sess = 0;
 261         return ret;
 262 }
 263
 264 static void
 265 nix_enable_mseg_on_jumbo(struct cnxk_eth_rxq_sp *rxq)
 266 {
 267         struct rte_pktmbuf_pool_private *mbp_priv;
 268         struct rte_eth_dev *eth_dev;
 269         struct cnxk_eth_dev *dev;
 270         uint32_t buffsz;
 271
 272         dev = rxq->dev;
 273         eth_dev = dev->eth_dev;
 274
 275         /* Get rx buffer size */
 276         mbp_priv = rte_mempool_get_priv(rxq->qconf.mp);
 277         buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
 278
 279         if (eth_dev->data->mtu + (uint32_t)CNXK_NIX_L2_OVERHEAD > buffsz) {
 280                 dev->rx_offloads |= RTE_ETH_RX_OFFLOAD_SCATTER;
 281                 dev->tx_offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
 282         }
 283 }
 284
 285 int
 286 nix_recalc_mtu(struct rte_eth_dev *eth_dev)
 287 {
 288         struct rte_eth_dev_data *data = eth_dev->data;
 289         struct cnxk_eth_rxq_sp *rxq;
 290         int rc;
 291
 292         rxq = ((struct cnxk_eth_rxq_sp *)data->rx_queues[0]) - 1;
 293         /* Setup scatter mode if needed by jumbo */
 294         nix_enable_mseg_on_jumbo(rxq);
 295
 296         rc = cnxk_nix_mtu_set(eth_dev, data->mtu);
 297         if (rc)
 298                 plt_err("Failed to set default MTU size, rc=%d", rc);
 299
 300         return rc;
 301 }
 302
 303 static int
 304 nix_init_flow_ctrl_config(struct rte_eth_dev *eth_dev)
 305 {
 306         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 307         struct cnxk_fc_cfg *fc = &dev->fc_cfg;
 308         struct rte_eth_fc_conf fc_conf = {0};
 309         int rc;
 310
 311         /* Both Rx & Tx flow ctrl get enabled(RTE_ETH_FC_FULL) in HW
 312          * by AF driver, update those info in PMD structure.
 313          */
 314         rc = cnxk_nix_flow_ctrl_get(eth_dev, &fc_conf);
 315         if (rc)
 316                 goto exit;
 317
 318         fc->mode = fc_conf.mode;
 319         fc->rx_pause = (fc_conf.mode == RTE_ETH_FC_FULL) ||
 320                         (fc_conf.mode == RTE_ETH_FC_RX_PAUSE);
 321         fc->tx_pause = (fc_conf.mode == RTE_ETH_FC_FULL) ||
 322                         (fc_conf.mode == RTE_ETH_FC_TX_PAUSE);
 323
 324 exit:
 325         return rc;
 326 }
 327
 328 static int
 329 nix_update_flow_ctrl_config(struct rte_eth_dev *eth_dev)
 330 {
 331         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 332         struct cnxk_fc_cfg *fc = &dev->fc_cfg;
 333         struct rte_eth_fc_conf fc_cfg = {0};
 334
 335         if (roc_nix_is_vf_or_sdp(&dev->nix) && !roc_nix_is_lbk(&dev->nix))
 336                 return 0;
 337
 338         fc_cfg.mode = fc->mode;
 339
 340         /* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */
 341         if (roc_model_is_cn96_ax() &&
 342             dev->npc.switch_header_type != ROC_PRIV_FLAGS_HIGIG &&
 343             (fc_cfg.mode == RTE_ETH_FC_FULL || fc_cfg.mode == RTE_ETH_FC_RX_PAUSE)) {
 344                 fc_cfg.mode =
 345                                 (fc_cfg.mode == RTE_ETH_FC_FULL ||
 346                                 fc_cfg.mode == RTE_ETH_FC_TX_PAUSE) ?
 347                                 RTE_ETH_FC_TX_PAUSE : RTE_ETH_FC_NONE;
 348         }
 349
 350         return cnxk_nix_flow_ctrl_set(eth_dev, &fc_cfg);
 351 }
 352
 353 uint64_t
 354 cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev)
 355 {
 356         uint16_t port_id = dev->eth_dev->data->port_id;
 357         struct rte_mbuf mb_def;
 358         uint64_t *tmp;
 359
 360         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
 361         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
 362                                  offsetof(struct rte_mbuf, data_off) !=
 363                          2);
 364         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
 365                                  offsetof(struct rte_mbuf, data_off) !=
 366                          4);
 367         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
 368                                  offsetof(struct rte_mbuf, data_off) !=
 369                          6);
 370         mb_def.nb_segs = 1;
 371         mb_def.data_off = RTE_PKTMBUF_HEADROOM +
 372                           (dev->ptp_en * CNXK_NIX_TIMESYNC_RX_OFFSET);
 373         mb_def.port = port_id;
 374         rte_mbuf_refcnt_set(&mb_def, 1);
 375
 376         /* Prevent compiler reordering: rearm_data covers previous fields */
 377         rte_compiler_barrier();
 378         tmp = (uint64_t *)&mb_def.rearm_data;
 379
 380         return *tmp;
 381 }
 382
 383 static inline uint8_t
 384 nix_sq_max_sqe_sz(struct cnxk_eth_dev *dev)
 385 {
 386         /*
 387          * Maximum three segments can be supported with W8, Choose
 388          * NIX_MAXSQESZ_W16 for multi segment offload.
 389          */
 390         if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_MULTI_SEGS)
 391                 return NIX_MAXSQESZ_W16;
 392         else
 393                 return NIX_MAXSQESZ_W8;
 394 }
 395
 396 int
 397 cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 398                         uint16_t nb_desc, uint16_t fp_tx_q_sz,
 399                         const struct rte_eth_txconf *tx_conf)
 400 {
 401         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 402         const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
 403         struct cnxk_eth_txq_sp *txq_sp;
 404         struct roc_nix_sq *sq;
 405         size_t txq_sz;
 406         int rc;
 407
 408         /* Free memory prior to re-allocation if needed. */
 409         if (eth_dev->data->tx_queues[qid] != NULL) {
 410                 plt_nix_dbg("Freeing memory prior to re-allocation %d", qid);
 411                 dev_ops->tx_queue_release(eth_dev, qid);
 412                 eth_dev->data->tx_queues[qid] = NULL;
 413         }
 414
 415         /* When Tx Security offload is enabled, increase tx desc count by
 416          * max possible outbound desc count.
 417          */
 418         if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY)
 419                 nb_desc += dev->outb.nb_desc;
 420
 421         /* Setup ROC SQ */
 422         sq = &dev->sqs[qid];
 423         sq->qid = qid;
 424         sq->nb_desc = nb_desc;
 425         sq->max_sqe_sz = nix_sq_max_sqe_sz(dev);
 426
 427         rc = roc_nix_sq_init(&dev->nix, sq);
 428         if (rc) {
 429                 plt_err("Failed to init sq=%d, rc=%d", qid, rc);
 430                 return rc;
 431         }
 432
 433         rc = -ENOMEM;
 434         txq_sz = sizeof(struct cnxk_eth_txq_sp) + fp_tx_q_sz;
 435         txq_sp = plt_zmalloc(txq_sz, PLT_CACHE_LINE_SIZE);
 436         if (!txq_sp) {
 437                 plt_err("Failed to alloc tx queue mem");
 438                 rc |= roc_nix_sq_fini(sq);
 439                 return rc;
 440         }
 441
 442         txq_sp->dev = dev;
 443         txq_sp->qid = qid;
 444         txq_sp->qconf.conf.tx = *tx_conf;
 445         /* Queue config should reflect global offloads */
 446         txq_sp->qconf.conf.tx.offloads = dev->tx_offloads;
 447         txq_sp->qconf.nb_desc = nb_desc;
 448
 449         plt_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " lmt_addr=%p"
 450                     " nb_sqb_bufs=%d sqes_per_sqb_log2=%d",
 451                     qid, sq->fc, dev->tx_offloads, sq->lmt_addr,
 452                     sq->nb_sqb_bufs, sq->sqes_per_sqb_log2);
 453
 454         /* Store start of fast path area */
 455         eth_dev->data->tx_queues[qid] = txq_sp + 1;
 456         eth_dev->data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
 457         return 0;
 458 }
 459
 460 static void
 461 cnxk_nix_tx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)
 462 {
 463         void *txq = eth_dev->data->tx_queues[qid];
 464         struct cnxk_eth_txq_sp *txq_sp;
 465         struct cnxk_eth_dev *dev;
 466         struct roc_nix_sq *sq;
 467         int rc;
 468
 469         if (!txq)
 470                 return;
 471
 472         txq_sp = cnxk_eth_txq_to_sp(txq);
 473
 474         dev = txq_sp->dev;
 475
 476         plt_nix_dbg("Releasing txq %u", qid);
 477
 478         /* Cleanup ROC SQ */
 479         sq = &dev->sqs[qid];
 480         rc = roc_nix_sq_fini(sq);
 481         if (rc)
 482                 plt_err("Failed to cleanup sq, rc=%d", rc);
 483
 484         /* Finally free */
 485         plt_free(txq_sp);
 486 }
 487
 488 int
 489 cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 490                         uint16_t nb_desc, uint16_t fp_rx_q_sz,
 491                         const struct rte_eth_rxconf *rx_conf,
 492                         struct rte_mempool *mp)
 493 {
 494         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 495         struct roc_nix *nix = &dev->nix;
 496         struct cnxk_eth_rxq_sp *rxq_sp;
 497         struct rte_mempool_ops *ops;
 498         const char *platform_ops;
 499         struct roc_nix_rq *rq;
 500         struct roc_nix_cq *cq;
 501         uint16_t first_skip;
 502         int rc = -EINVAL;
 503         size_t rxq_sz;
 504
 505         /* Sanity checks */
 506         if (rx_conf->rx_deferred_start == 1) {
 507                 plt_err("Deferred Rx start is not supported");
 508                 goto fail;
 509         }
 510
 511         platform_ops = rte_mbuf_platform_mempool_ops();
 512         /* This driver needs cnxk_npa mempool ops to work */
 513         ops = rte_mempool_get_ops(mp->ops_index);
 514         if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
 515                 plt_err("mempool ops should be of cnxk_npa type");
 516                 goto fail;
 517         }
 518
 519         if (mp->pool_id == 0) {
 520                 plt_err("Invalid pool_id");
 521                 goto fail;
 522         }
 523
 524         /* Free memory prior to re-allocation if needed */
 525         if (eth_dev->data->rx_queues[qid] != NULL) {
 526                 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
 527
 528                 plt_nix_dbg("Freeing memory prior to re-allocation %d", qid);
 529                 dev_ops->rx_queue_release(eth_dev, qid);
 530                 eth_dev->data->rx_queues[qid] = NULL;
 531         }
 532
 533         /* Clam up cq limit to size of packet pool aura for LBK
 534          * to avoid meta packet drop as LBK does not currently support
 535          * backpressure.
 536          */
 537         if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY && roc_nix_is_lbk(nix)) {
 538                 uint64_t pkt_pool_limit = roc_nix_inl_dev_rq_limit_get();
 539
 540                 /* Use current RQ's aura limit if inl rq is not available */
 541                 if (!pkt_pool_limit)
 542                         pkt_pool_limit = roc_npa_aura_op_limit_get(mp->pool_id);
 543                 nb_desc = RTE_MAX(nb_desc, pkt_pool_limit);
 544         }
 545
 546         /* Setup ROC CQ */
 547         cq = &dev->cqs[qid];
 548         cq->qid = qid;
 549         cq->nb_desc = nb_desc;
 550         rc = roc_nix_cq_init(&dev->nix, cq);
 551         if (rc) {
 552                 plt_err("Failed to init roc cq for rq=%d, rc=%d", qid, rc);
 553                 goto fail;
 554         }
 555
 556         /* Setup ROC RQ */
 557         rq = &dev->rqs[qid];
 558         rq->qid = qid;
 559         rq->aura_handle = mp->pool_id;
 560         rq->flow_tag_width = 32;
 561         rq->sso_ena = false;
 562
 563         /* Calculate first mbuf skip */
 564         first_skip = (sizeof(struct rte_mbuf));
 565         first_skip += RTE_PKTMBUF_HEADROOM;
 566         first_skip += rte_pktmbuf_priv_size(mp);
 567         rq->first_skip = first_skip;
 568         rq->later_skip = sizeof(struct rte_mbuf);
 569         rq->lpb_size = mp->elt_size;
 570
 571         /* Enable Inline IPSec on RQ, will not be used for Poll mode */
 572         if (roc_nix_inl_inb_is_enabled(nix))
 573                 rq->ipsech_ena = true;
 574
 575         rc = roc_nix_rq_init(&dev->nix, rq, !!eth_dev->data->dev_started);
 576         if (rc) {
 577                 plt_err("Failed to init roc rq for rq=%d, rc=%d", qid, rc);
 578                 goto cq_fini;
 579         }
 580
 581         /* Allocate and setup fast path rx queue */
 582         rc = -ENOMEM;
 583         rxq_sz = sizeof(struct cnxk_eth_rxq_sp) + fp_rx_q_sz;
 584         rxq_sp = plt_zmalloc(rxq_sz, PLT_CACHE_LINE_SIZE);
 585         if (!rxq_sp) {
 586                 plt_err("Failed to alloc rx queue for rq=%d", qid);
 587                 goto rq_fini;
 588         }
 589
 590         /* Setup slow path fields */
 591         rxq_sp->dev = dev;
 592         rxq_sp->qid = qid;
 593         rxq_sp->qconf.conf.rx = *rx_conf;
 594         /* Queue config should reflect global offloads */
 595         rxq_sp->qconf.conf.rx.offloads = dev->rx_offloads;
 596         rxq_sp->qconf.nb_desc = nb_desc;
 597         rxq_sp->qconf.mp = mp;
 598
 599         if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
 600                 /* Setup rq reference for inline dev if present */
 601                 rc = roc_nix_inl_dev_rq_get(rq);
 602                 if (rc)
 603                         goto free_mem;
 604         }
 605
 606         plt_nix_dbg("rq=%d pool=%s nb_desc=%d->%d", qid, mp->name, nb_desc,
 607                     cq->nb_desc);
 608
 609         /* Store start of fast path area */
 610         eth_dev->data->rx_queues[qid] = rxq_sp + 1;
 611         eth_dev->data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
 612
 613         /* Calculating delta and freq mult between PTP HI clock and tsc.
 614          * These are needed in deriving raw clock value from tsc counter.
 615          * read_clock eth op returns raw clock value.
 616          */
 617         if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) || dev->ptp_en) {
 618                 rc = cnxk_nix_tsc_convert(dev);
 619                 if (rc) {
 620                         plt_err("Failed to calculate delta and freq mult");
 621                         goto rq_fini;
 622                 }
 623         }
 624
 625         return 0;
 626 free_mem:
 627         plt_free(rxq_sp);
 628 rq_fini:
 629         rc |= roc_nix_rq_fini(rq);
 630 cq_fini:
 631         rc |= roc_nix_cq_fini(cq);
 632 fail:
 633         return rc;
 634 }
 635
 636 static void
 637 cnxk_nix_rx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)
 638 {
 639         void *rxq = eth_dev->data->rx_queues[qid];
 640         struct cnxk_eth_rxq_sp *rxq_sp;
 641         struct cnxk_eth_dev *dev;
 642         struct roc_nix_rq *rq;
 643         struct roc_nix_cq *cq;
 644         int rc;
 645
 646         if (!rxq)
 647                 return;
 648
 649         rxq_sp = cnxk_eth_rxq_to_sp(rxq);
 650         dev = rxq_sp->dev;
 651         rq = &dev->rqs[qid];
 652
 653         plt_nix_dbg("Releasing rxq %u", qid);
 654
 655         /* Release rq reference for inline dev if present */
 656         if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)
 657                 roc_nix_inl_dev_rq_put(rq);
 658
 659         /* Cleanup ROC RQ */
 660         rc = roc_nix_rq_fini(rq);
 661         if (rc)
 662                 plt_err("Failed to cleanup rq, rc=%d", rc);
 663
 664         /* Cleanup ROC CQ */
 665         cq = &dev->cqs[qid];
 666         rc = roc_nix_cq_fini(cq);
 667         if (rc)
 668                 plt_err("Failed to cleanup cq, rc=%d", rc);
 669
 670         /* Finally free fast path area */
 671         plt_free(rxq_sp);
 672 }
 673
 674 uint32_t
 675 cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
 676                        uint8_t rss_level)
 677 {
 678         uint32_t flow_key_type[RSS_MAX_LEVELS][6] = {
 679                 {FLOW_KEY_TYPE_IPV4, FLOW_KEY_TYPE_IPV6, FLOW_KEY_TYPE_TCP,
 680                  FLOW_KEY_TYPE_UDP, FLOW_KEY_TYPE_SCTP, FLOW_KEY_TYPE_ETH_DMAC},
 681                 {FLOW_KEY_TYPE_INNR_IPV4, FLOW_KEY_TYPE_INNR_IPV6,
 682                  FLOW_KEY_TYPE_INNR_TCP, FLOW_KEY_TYPE_INNR_UDP,
 683                  FLOW_KEY_TYPE_INNR_SCTP, FLOW_KEY_TYPE_INNR_ETH_DMAC},
 684                 {FLOW_KEY_TYPE_IPV4 | FLOW_KEY_TYPE_INNR_IPV4,
 685                  FLOW_KEY_TYPE_IPV6 | FLOW_KEY_TYPE_INNR_IPV6,
 686                  FLOW_KEY_TYPE_TCP | FLOW_KEY_TYPE_INNR_TCP,
 687                  FLOW_KEY_TYPE_UDP | FLOW_KEY_TYPE_INNR_UDP,
 688                  FLOW_KEY_TYPE_SCTP | FLOW_KEY_TYPE_INNR_SCTP,
 689                  FLOW_KEY_TYPE_ETH_DMAC | FLOW_KEY_TYPE_INNR_ETH_DMAC}
 690         };
 691         uint32_t flowkey_cfg = 0;
 692
 693         dev->ethdev_rss_hf = ethdev_rss;
 694
 695         if (ethdev_rss & RTE_ETH_RSS_L2_PAYLOAD &&
 696             dev->npc.switch_header_type == ROC_PRIV_FLAGS_LEN_90B) {
 697                 flowkey_cfg |= FLOW_KEY_TYPE_CH_LEN_90B;
 698         }
 699
 700         if (ethdev_rss & RTE_ETH_RSS_C_VLAN)
 701                 flowkey_cfg |= FLOW_KEY_TYPE_VLAN;
 702
 703         if (ethdev_rss & RTE_ETH_RSS_L3_SRC_ONLY)
 704                 flowkey_cfg |= FLOW_KEY_TYPE_L3_SRC;
 705
 706         if (ethdev_rss & RTE_ETH_RSS_L3_DST_ONLY)
 707                 flowkey_cfg |= FLOW_KEY_TYPE_L3_DST;
 708
 709         if (ethdev_rss & RTE_ETH_RSS_L4_SRC_ONLY)
 710                 flowkey_cfg |= FLOW_KEY_TYPE_L4_SRC;
 711
 712         if (ethdev_rss & RTE_ETH_RSS_L4_DST_ONLY)
 713                 flowkey_cfg |= FLOW_KEY_TYPE_L4_DST;
 714
 715         if (ethdev_rss & RSS_IPV4_ENABLE)
 716                 flowkey_cfg |= flow_key_type[rss_level][RSS_IPV4_INDEX];
 717
 718         if (ethdev_rss & RSS_IPV6_ENABLE)
 719                 flowkey_cfg |= flow_key_type[rss_level][RSS_IPV6_INDEX];
 720
 721         if (ethdev_rss & RTE_ETH_RSS_TCP)
 722                 flowkey_cfg |= flow_key_type[rss_level][RSS_TCP_INDEX];
 723
 724         if (ethdev_rss & RTE_ETH_RSS_UDP)
 725                 flowkey_cfg |= flow_key_type[rss_level][RSS_UDP_INDEX];
 726
 727         if (ethdev_rss & RTE_ETH_RSS_SCTP)
 728                 flowkey_cfg |= flow_key_type[rss_level][RSS_SCTP_INDEX];
 729
 730         if (ethdev_rss & RTE_ETH_RSS_L2_PAYLOAD)
 731                 flowkey_cfg |= flow_key_type[rss_level][RSS_DMAC_INDEX];
 732
 733         if (ethdev_rss & RSS_IPV6_EX_ENABLE)
 734                 flowkey_cfg |= FLOW_KEY_TYPE_IPV6_EXT;
 735
 736         if (ethdev_rss & RTE_ETH_RSS_PORT)
 737                 flowkey_cfg |= FLOW_KEY_TYPE_PORT;
 738
 739         if (ethdev_rss & RTE_ETH_RSS_NVGRE)
 740                 flowkey_cfg |= FLOW_KEY_TYPE_NVGRE;
 741
 742         if (ethdev_rss & RTE_ETH_RSS_VXLAN)
 743                 flowkey_cfg |= FLOW_KEY_TYPE_VXLAN;
 744
 745         if (ethdev_rss & RTE_ETH_RSS_GENEVE)
 746                 flowkey_cfg |= FLOW_KEY_TYPE_GENEVE;
 747
 748         if (ethdev_rss & RTE_ETH_RSS_GTPU)
 749                 flowkey_cfg |= FLOW_KEY_TYPE_GTPU;
 750
 751         return flowkey_cfg;
 752 }
 753
 754 static void
 755 nix_free_queue_mem(struct cnxk_eth_dev *dev)
 756 {
 757         plt_free(dev->rqs);
 758         plt_free(dev->cqs);
 759         plt_free(dev->sqs);
 760         dev->rqs = NULL;
 761         dev->cqs = NULL;
 762         dev->sqs = NULL;
 763 }
 764
 765 static int
 766 nix_ingress_policer_setup(struct cnxk_eth_dev *dev)
 767 {
 768         struct rte_eth_dev *eth_dev = dev->eth_dev;
 769         int rc = 0;
 770
 771         TAILQ_INIT(&dev->mtr_profiles);
 772         TAILQ_INIT(&dev->mtr_policy);
 773         TAILQ_INIT(&dev->mtr);
 774
 775         if (eth_dev->dev_ops->mtr_ops_get == NULL)
 776                 return rc;
 777
 778         return nix_mtr_capabilities_init(eth_dev);
 779 }
 780
 781 static int
 782 nix_rss_default_setup(struct cnxk_eth_dev *dev)
 783 {
 784         struct rte_eth_dev *eth_dev = dev->eth_dev;
 785         uint8_t rss_hash_level;
 786         uint32_t flowkey_cfg;
 787         uint64_t rss_hf;
 788
 789         rss_hf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
 790         rss_hash_level = RTE_ETH_RSS_LEVEL(rss_hf);
 791         if (rss_hash_level)
 792                 rss_hash_level -= 1;
 793
 794         flowkey_cfg = cnxk_rss_ethdev_to_nix(dev, rss_hf, rss_hash_level);
 795         return roc_nix_rss_default_setup(&dev->nix, flowkey_cfg);
 796 }
 797
 798 static int
 799 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
 800 {
 801         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 802         const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
 803         struct cnxk_eth_qconf *tx_qconf = NULL;
 804         struct cnxk_eth_qconf *rx_qconf = NULL;
 805         struct cnxk_eth_rxq_sp *rxq_sp;
 806         struct cnxk_eth_txq_sp *txq_sp;
 807         int i, nb_rxq, nb_txq;
 808         void **txq, **rxq;
 809
 810         nb_rxq = RTE_MIN(dev->nb_rxq, eth_dev->data->nb_rx_queues);
 811         nb_txq = RTE_MIN(dev->nb_txq, eth_dev->data->nb_tx_queues);
 812
 813         tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
 814         if (tx_qconf == NULL) {
 815                 plt_err("Failed to allocate memory for tx_qconf");
 816                 goto fail;
 817         }
 818
 819         rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
 820         if (rx_qconf == NULL) {
 821                 plt_err("Failed to allocate memory for rx_qconf");
 822                 goto fail;
 823         }
 824
 825         txq = eth_dev->data->tx_queues;
 826         for (i = 0; i < nb_txq; i++) {
 827                 if (txq[i] == NULL) {
 828                         tx_qconf[i].valid = false;
 829                         plt_info("txq[%d] is already released", i);
 830                         continue;
 831                 }
 832                 txq_sp = cnxk_eth_txq_to_sp(txq[i]);
 833                 memcpy(&tx_qconf[i], &txq_sp->qconf, sizeof(*tx_qconf));
 834                 tx_qconf[i].valid = true;
 835                 dev_ops->tx_queue_release(eth_dev, i);
 836                 eth_dev->data->tx_queues[i] = NULL;
 837         }
 838
 839         rxq = eth_dev->data->rx_queues;
 840         for (i = 0; i < nb_rxq; i++) {
 841                 if (rxq[i] == NULL) {
 842                         rx_qconf[i].valid = false;
 843                         plt_info("rxq[%d] is already released", i);
 844                         continue;
 845                 }
 846                 rxq_sp = cnxk_eth_rxq_to_sp(rxq[i]);
 847                 memcpy(&rx_qconf[i], &rxq_sp->qconf, sizeof(*rx_qconf));
 848                 rx_qconf[i].valid = true;
 849                 dev_ops->rx_queue_release(eth_dev, i);
 850                 eth_dev->data->rx_queues[i] = NULL;
 851         }
 852
 853         dev->tx_qconf = tx_qconf;
 854         dev->rx_qconf = rx_qconf;
 855         return 0;
 856
 857 fail:
 858         free(tx_qconf);
 859         free(rx_qconf);
 860         return -ENOMEM;
 861 }
 862
 863 static int
 864 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
 865 {
 866         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 867         const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
 868         struct cnxk_eth_qconf *tx_qconf = dev->tx_qconf;
 869         struct cnxk_eth_qconf *rx_qconf = dev->rx_qconf;
 870         int rc, i, nb_rxq, nb_txq;
 871
 872         nb_rxq = RTE_MIN(dev->nb_rxq, eth_dev->data->nb_rx_queues);
 873         nb_txq = RTE_MIN(dev->nb_txq, eth_dev->data->nb_tx_queues);
 874
 875         rc = -ENOMEM;
 876         /* Setup tx & rx queues with previous configuration so
 877          * that the queues can be functional in cases like ports
 878          * are started without re configuring queues.
 879          *
 880          * Usual re config sequence is like below:
 881          * port_configure() {
 882          *      if(reconfigure) {
 883          *              queue_release()
 884          *              queue_setup()
 885          *      }
 886          *      queue_configure() {
 887          *              queue_release()
 888          *              queue_setup()
 889          *      }
 890          * }
 891          * port_start()
 892          *
 893          * In some application's control path, queue_configure() would
 894          * NOT be invoked for TXQs/RXQs in port_configure().
 895          * In such cases, queues can be functional after start as the
 896          * queues are already setup in port_configure().
 897          */
 898         for (i = 0; i < nb_txq; i++) {
 899                 if (!tx_qconf[i].valid)
 900                         continue;
 901                 rc = dev_ops->tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc, 0,
 902                                              &tx_qconf[i].conf.tx);
 903                 if (rc) {
 904                         plt_err("Failed to setup tx queue rc=%d", rc);
 905                         for (i -= 1; i >= 0; i--)
 906                                 dev_ops->tx_queue_release(eth_dev, i);
 907                         goto fail;
 908                 }
 909         }
 910
 911         free(tx_qconf);
 912         tx_qconf = NULL;
 913
 914         for (i = 0; i < nb_rxq; i++) {
 915                 if (!rx_qconf[i].valid)
 916                         continue;
 917                 rc = dev_ops->rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc, 0,
 918                                              &rx_qconf[i].conf.rx,
 919                                              rx_qconf[i].mp);
 920                 if (rc) {
 921                         plt_err("Failed to setup rx queue rc=%d", rc);
 922                         for (i -= 1; i >= 0; i--)
 923                                 dev_ops->rx_queue_release(eth_dev, i);
 924                         goto tx_queue_release;
 925                 }
 926         }
 927
 928         free(rx_qconf);
 929         rx_qconf = NULL;
 930
 931         return 0;
 932
 933 tx_queue_release:
 934         for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
 935                 dev_ops->tx_queue_release(eth_dev, i);
 936 fail:
 937         free(tx_qconf);
 938         free(rx_qconf);
 939
 940         return rc;
 941 }
 942
 943 static uint16_t
 944 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
 945 {
 946         RTE_SET_USED(queue);
 947         RTE_SET_USED(mbufs);
 948         RTE_SET_USED(pkts);
 949
 950         return 0;
 951 }
 952
 953 static void
 954 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
 955 {
 956         /* These dummy functions are required for supporting
 957          * some applications which reconfigure queues without
 958          * stopping tx burst and rx burst threads(eg kni app)
 959          * When the queues context is saved, txq/rxqs are released
 960          * which caused app crash since rx/tx burst is still
 961          * on different lcores
 962          */
 963         eth_dev->tx_pkt_burst = nix_eth_nop_burst;
 964         eth_dev->rx_pkt_burst = nix_eth_nop_burst;
 965         rte_mb();
 966 }
 967
 968 static int
 969 nix_lso_tun_fmt_update(struct cnxk_eth_dev *dev)
 970 {
 971         uint8_t udp_tun[ROC_NIX_LSO_TUN_MAX];
 972         uint8_t tun[ROC_NIX_LSO_TUN_MAX];
 973         struct roc_nix *nix = &dev->nix;
 974         int rc;
 975
 976         rc = roc_nix_lso_fmt_get(nix, udp_tun, tun);
 977         if (rc)
 978                 return rc;
 979
 980         dev->lso_tun_fmt = ((uint64_t)tun[ROC_NIX_LSO_TUN_V4V4] |
 981                             (uint64_t)tun[ROC_NIX_LSO_TUN_V4V6] << 8 |
 982                             (uint64_t)tun[ROC_NIX_LSO_TUN_V6V4] << 16 |
 983                             (uint64_t)tun[ROC_NIX_LSO_TUN_V6V6] << 24);
 984
 985         dev->lso_tun_fmt |= ((uint64_t)udp_tun[ROC_NIX_LSO_TUN_V4V4] << 32 |
 986                              (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V4V6] << 40 |
 987                              (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V6V4] << 48 |
 988                              (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V6V6] << 56);
 989         return 0;
 990 }
 991
 992 static int
 993 nix_lso_fmt_setup(struct cnxk_eth_dev *dev)
 994 {
 995         struct roc_nix *nix = &dev->nix;
 996         int rc;
 997
 998         /* Nothing much to do if offload is not enabled */
 999         if (!(dev->tx_offloads &
1000               (RTE_ETH_TX_OFFLOAD_TCP_TSO | RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
1001                RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO | RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO)))
1002                 return 0;
1003
1004         /* Setup LSO formats in AF. Its a no-op if other ethdev has
1005          * already set it up
1006          */
1007         rc = roc_nix_lso_fmt_setup(nix);
1008         if (rc)
1009                 return rc;
1010
1011         return nix_lso_tun_fmt_update(dev);
1012 }
1013
1014 int
1015 cnxk_nix_configure(struct rte_eth_dev *eth_dev)
1016 {
1017         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1018         struct rte_eth_dev_data *data = eth_dev->data;
1019         struct rte_eth_conf *conf = &data->dev_conf;
1020         struct rte_eth_rxmode *rxmode = &conf->rxmode;
1021         struct rte_eth_txmode *txmode = &conf->txmode;
1022         char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
1023         struct roc_nix_fc_cfg fc_cfg = {0};
1024         struct roc_nix *nix = &dev->nix;
1025         struct rte_ether_addr *ea;
1026         uint8_t nb_rxq, nb_txq;
1027         uint64_t rx_cfg;
1028         void *qs;
1029         int rc;
1030
1031         rc = -EINVAL;
1032
1033         /* Sanity checks */
1034         if (rte_eal_has_hugepages() == 0) {
1035                 plt_err("Huge page is not configured");
1036                 goto fail_configure;
1037         }
1038
1039         if (conf->dcb_capability_en == 1) {
1040                 plt_err("dcb enable is not supported");
1041                 goto fail_configure;
1042         }
1043
1044         if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1045                 plt_err("Flow director is not supported");
1046                 goto fail_configure;
1047         }
1048
1049         if (rxmode->mq_mode != RTE_ETH_MQ_RX_NONE &&
1050             rxmode->mq_mode != RTE_ETH_MQ_RX_RSS) {
1051                 plt_err("Unsupported mq rx mode %d", rxmode->mq_mode);
1052                 goto fail_configure;
1053         }
1054
1055         if (txmode->mq_mode != RTE_ETH_MQ_TX_NONE) {
1056                 plt_err("Unsupported mq tx mode %d", txmode->mq_mode);
1057                 goto fail_configure;
1058         }
1059
1060         /* Free the resources allocated from the previous configure */
1061         if (dev->configured == 1) {
1062                 /* Unregister queue irq's */
1063                 roc_nix_unregister_queue_irqs(nix);
1064
1065                 /* Unregister CQ irqs if present */
1066                 if (eth_dev->data->dev_conf.intr_conf.rxq)
1067                         roc_nix_unregister_cq_irqs(nix);
1068
1069                 /* Set no-op functions */
1070                 nix_set_nop_rxtx_function(eth_dev);
1071                 /* Store queue config for later */
1072                 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1073                 if (rc)
1074                         goto fail_configure;
1075
1076                 /* Disable and free rte_meter entries */
1077                 rc = nix_meter_fini(dev);
1078                 if (rc)
1079                         goto fail_configure;
1080
1081                 /* Cleanup security support */
1082                 rc = nix_security_release(dev);
1083                 if (rc)
1084                         goto fail_configure;
1085
1086                 roc_nix_tm_fini(nix);
1087                 roc_nix_lf_free(nix);
1088         }
1089
1090         dev->rx_offloads = rxmode->offloads;
1091         dev->tx_offloads = txmode->offloads;
1092
1093         /* Prepare rx cfg */
1094         rx_cfg = ROC_NIX_LF_RX_CFG_DIS_APAD;
1095         if (dev->rx_offloads &
1096             (RTE_ETH_RX_OFFLOAD_TCP_CKSUM | RTE_ETH_RX_OFFLOAD_UDP_CKSUM)) {
1097                 rx_cfg |= ROC_NIX_LF_RX_CFG_CSUM_OL4;
1098                 rx_cfg |= ROC_NIX_LF_RX_CFG_CSUM_IL4;
1099         }
1100         rx_cfg |= (ROC_NIX_LF_RX_CFG_DROP_RE | ROC_NIX_LF_RX_CFG_L2_LEN_ERR |
1101                    ROC_NIX_LF_RX_CFG_LEN_IL4 | ROC_NIX_LF_RX_CFG_LEN_IL3 |
1102                    ROC_NIX_LF_RX_CFG_LEN_OL4 | ROC_NIX_LF_RX_CFG_LEN_OL3);
1103
1104         if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
1105                 rx_cfg |= ROC_NIX_LF_RX_CFG_IP6_UDP_OPT;
1106                 /* Disable drop re if rx offload security is enabled and
1107                  * platform does not support it.
1108                  */
1109                 if (dev->ipsecd_drop_re_dis)
1110                         rx_cfg &= ~(ROC_NIX_LF_RX_CFG_DROP_RE);
1111         }
1112
1113         nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1114         nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1115
1116         /* Alloc a nix lf */
1117         rc = roc_nix_lf_alloc(nix, nb_rxq, nb_txq, rx_cfg);
1118         if (rc) {
1119                 plt_err("Failed to init nix_lf rc=%d", rc);
1120                 goto fail_configure;
1121         }
1122
1123         dev->npc.channel = roc_nix_get_base_chan(nix);
1124
1125         nb_rxq = data->nb_rx_queues;
1126         nb_txq = data->nb_tx_queues;
1127         rc = -ENOMEM;
1128         if (nb_rxq) {
1129                 /* Allocate memory for roc rq's and cq's */
1130                 qs = plt_zmalloc(sizeof(struct roc_nix_rq) * nb_rxq, 0);
1131                 if (!qs) {
1132                         plt_err("Failed to alloc rqs");
1133                         goto free_nix_lf;
1134                 }
1135                 dev->rqs = qs;
1136
1137                 qs = plt_zmalloc(sizeof(struct roc_nix_cq) * nb_rxq, 0);
1138                 if (!qs) {
1139                         plt_err("Failed to alloc cqs");
1140                         goto free_nix_lf;
1141                 }
1142                 dev->cqs = qs;
1143         }
1144
1145         if (nb_txq) {
1146                 /* Allocate memory for roc sq's */
1147                 qs = plt_zmalloc(sizeof(struct roc_nix_sq) * nb_txq, 0);
1148                 if (!qs) {
1149                         plt_err("Failed to alloc sqs");
1150                         goto free_nix_lf;
1151                 }
1152                 dev->sqs = qs;
1153         }
1154
1155         /* Re-enable NIX LF error interrupts */
1156         roc_nix_err_intr_ena_dis(nix, true);
1157         roc_nix_ras_intr_ena_dis(nix, true);
1158
1159         if (nix->rx_ptp_ena &&
1160             dev->npc.switch_header_type == ROC_PRIV_FLAGS_HIGIG) {
1161                 plt_err("Both PTP and switch header enabled");
1162                 goto free_nix_lf;
1163         }
1164
1165         rc = roc_nix_switch_hdr_set(nix, dev->npc.switch_header_type,
1166                                     dev->npc.pre_l2_size_offset,
1167                                     dev->npc.pre_l2_size_offset_mask,
1168                                     dev->npc.pre_l2_size_shift_dir);
1169         if (rc) {
1170                 plt_err("Failed to enable switch type nix_lf rc=%d", rc);
1171                 goto free_nix_lf;
1172         }
1173
1174         /* Setup LSO if needed */
1175         rc = nix_lso_fmt_setup(dev);
1176         if (rc) {
1177                 plt_err("Failed to setup nix lso format fields, rc=%d", rc);
1178                 goto free_nix_lf;
1179         }
1180
1181         /* Configure RSS */
1182         rc = nix_rss_default_setup(dev);
1183         if (rc) {
1184                 plt_err("Failed to configure rss rc=%d", rc);
1185                 goto free_nix_lf;
1186         }
1187
1188         /* Init the default TM scheduler hierarchy */
1189         rc = roc_nix_tm_init(nix);
1190         if (rc) {
1191                 plt_err("Failed to init traffic manager, rc=%d", rc);
1192                 goto free_nix_lf;
1193         }
1194
1195         rc = nix_ingress_policer_setup(dev);
1196         if (rc) {
1197                 plt_err("Failed to setup ingress policer rc=%d", rc);
1198                 goto free_nix_lf;
1199         }
1200
1201         rc = roc_nix_tm_hierarchy_enable(nix, ROC_NIX_TM_DEFAULT, false);
1202         if (rc) {
1203                 plt_err("Failed to enable default tm hierarchy, rc=%d", rc);
1204                 goto tm_fini;
1205         }
1206
1207         /* Register queue IRQs */
1208         rc = roc_nix_register_queue_irqs(nix);
1209         if (rc) {
1210                 plt_err("Failed to register queue interrupts rc=%d", rc);
1211                 goto tm_fini;
1212         }
1213
1214         /* Register cq IRQs */
1215         if (eth_dev->data->dev_conf.intr_conf.rxq) {
1216                 if (eth_dev->data->nb_rx_queues > dev->nix.cints) {
1217                         plt_err("Rx interrupt cannot be enabled, rxq > %d",
1218                                 dev->nix.cints);
1219                         goto q_irq_fini;
1220                 }
1221                 /* Rx interrupt feature cannot work with vector mode because,
1222                  * vector mode does not process packets unless min 4 pkts are
1223                  * received, while cq interrupts are generated even for 1 pkt
1224                  * in the CQ.
1225                  */
1226                 dev->scalar_ena = true;
1227
1228                 rc = roc_nix_register_cq_irqs(nix);
1229                 if (rc) {
1230                         plt_err("Failed to register CQ interrupts rc=%d", rc);
1231                         goto q_irq_fini;
1232                 }
1233         }
1234
1235         /* Configure loop back mode */
1236         rc = roc_nix_mac_loopback_enable(nix,
1237                                          eth_dev->data->dev_conf.lpbk_mode);
1238         if (rc) {
1239                 plt_err("Failed to configure cgx loop back mode rc=%d", rc);
1240                 goto cq_fini;
1241         }
1242
1243         /* Setup Inline security support */
1244         rc = nix_security_setup(dev);
1245         if (rc)
1246                 goto cq_fini;
1247
1248         /* Init flow control configuration */
1249         fc_cfg.type = ROC_NIX_FC_RXCHAN_CFG;
1250         fc_cfg.rxchan_cfg.enable = true;
1251         rc = roc_nix_fc_config_set(nix, &fc_cfg);
1252         if (rc) {
1253                 plt_err("Failed to initialize flow control rc=%d", rc);
1254                 goto cq_fini;
1255         }
1256
1257         /* Update flow control configuration to PMD */
1258         rc = nix_init_flow_ctrl_config(eth_dev);
1259         if (rc) {
1260                 plt_err("Failed to initialize flow control rc=%d", rc);
1261                 goto cq_fini;
1262         }
1263
1264         /*
1265          * Restore queue config when reconfigure followed by
1266          * reconfigure and no queue configure invoked from application case.
1267          */
1268         if (dev->configured == 1) {
1269                 rc = nix_restore_queue_cfg(eth_dev);
1270                 if (rc)
1271                         goto sec_release;
1272         }
1273
1274         /* Update the mac address */
1275         ea = eth_dev->data->mac_addrs;
1276         memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1277         if (rte_is_zero_ether_addr(ea))
1278                 rte_eth_random_addr((uint8_t *)ea);
1279
1280         rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
1281
1282         plt_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
1283                     " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 "",
1284                     eth_dev->data->port_id, ea_fmt, nb_rxq, nb_txq,
1285                     dev->rx_offloads, dev->tx_offloads);
1286
1287         /* All good */
1288         dev->configured = 1;
1289         dev->nb_rxq = data->nb_rx_queues;
1290         dev->nb_txq = data->nb_tx_queues;
1291         return 0;
1292
1293 sec_release:
1294         rc |= nix_security_release(dev);
1295 cq_fini:
1296         roc_nix_unregister_cq_irqs(nix);
1297 q_irq_fini:
1298         roc_nix_unregister_queue_irqs(nix);
1299 tm_fini:
1300         roc_nix_tm_fini(nix);
1301 free_nix_lf:
1302         nix_free_queue_mem(dev);
1303         rc |= roc_nix_lf_free(nix);
1304 fail_configure:
1305         dev->configured = 0;
1306         return rc;
1307 }
1308
1309 int
1310 cnxk_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid)
1311 {
1312         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1313         struct rte_eth_dev_data *data = eth_dev->data;
1314         struct roc_nix_sq *sq = &dev->sqs[qid];
1315         int rc = -EINVAL;
1316
1317         if (data->tx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STARTED)
1318                 return 0;
1319
1320         rc = roc_nix_tm_sq_aura_fc(sq, true);
1321         if (rc) {
1322                 plt_err("Failed to enable sq aura fc, txq=%u, rc=%d", qid, rc);
1323                 goto done;
1324         }
1325
1326         data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STARTED;
1327 done:
1328         return rc;
1329 }
1330
1331 int
1332 cnxk_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid)
1333 {
1334         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1335         struct rte_eth_dev_data *data = eth_dev->data;
1336         struct roc_nix_sq *sq = &dev->sqs[qid];
1337         int rc;
1338
1339         if (data->tx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STOPPED)
1340                 return 0;
1341
1342         rc = roc_nix_tm_sq_aura_fc(sq, false);
1343         if (rc) {
1344                 plt_err("Failed to disable sqb aura fc, txq=%u, rc=%d", qid,
1345                         rc);
1346                 goto done;
1347         }
1348
1349         data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
1350 done:
1351         return rc;
1352 }
1353
1354 static int
1355 cnxk_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid)
1356 {
1357         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1358         struct rte_eth_dev_data *data = eth_dev->data;
1359         struct roc_nix_rq *rq = &dev->rqs[qid];
1360         int rc;
1361
1362         if (data->rx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STARTED)
1363                 return 0;
1364
1365         rc = roc_nix_rq_ena_dis(rq, true);
1366         if (rc) {
1367                 plt_err("Failed to enable rxq=%u, rc=%d", qid, rc);
1368                 goto done;
1369         }
1370
1371         data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STARTED;
1372 done:
1373         return rc;
1374 }
1375
1376 static int
1377 cnxk_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid)
1378 {
1379         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1380         struct rte_eth_dev_data *data = eth_dev->data;
1381         struct roc_nix_rq *rq = &dev->rqs[qid];
1382         int rc;
1383
1384         if (data->rx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STOPPED)
1385                 return 0;
1386
1387         rc = roc_nix_rq_ena_dis(rq, false);
1388         if (rc) {
1389                 plt_err("Failed to disable rxq=%u, rc=%d", qid, rc);
1390                 goto done;
1391         }
1392
1393         data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
1394 done:
1395         return rc;
1396 }
1397
1398 static int
1399 cnxk_nix_dev_stop(struct rte_eth_dev *eth_dev)
1400 {
1401         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1402         const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
1403         struct rte_mbuf *rx_pkts[32];
1404         struct rte_eth_link link;
1405         int count, i, j, rc;
1406         void *rxq;
1407
1408         /* Disable switch hdr pkind */
1409         roc_nix_switch_hdr_set(&dev->nix, 0, 0, 0, 0);
1410
1411         /* Stop link change events */
1412         if (!roc_nix_is_vf_or_sdp(&dev->nix))
1413                 roc_nix_mac_link_event_start_stop(&dev->nix, false);
1414
1415         /* Disable Rx via NPC */
1416         roc_nix_npc_rx_ena_dis(&dev->nix, false);
1417
1418         /* Stop rx queues and free up pkts pending */
1419         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1420                 rc = dev_ops->rx_queue_stop(eth_dev, i);
1421                 if (rc)
1422                         continue;
1423
1424                 rxq = eth_dev->data->rx_queues[i];
1425                 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1426                 while (count) {
1427                         for (j = 0; j < count; j++)
1428                                 rte_pktmbuf_free(rx_pkts[j]);
1429                         count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1430                 }
1431         }
1432
1433         /* Stop tx queues  */
1434         for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1435                 dev_ops->tx_queue_stop(eth_dev, i);
1436
1437         /* Bring down link status internally */
1438         memset(&link, 0, sizeof(link));
1439         rte_eth_linkstatus_set(eth_dev, &link);
1440
1441         return 0;
1442 }
1443
1444 int
1445 cnxk_nix_dev_start(struct rte_eth_dev *eth_dev)
1446 {
1447         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1448         int rc, i;
1449
1450         if (eth_dev->data->nb_rx_queues != 0 && !dev->ptp_en) {
1451                 rc = nix_recalc_mtu(eth_dev);
1452                 if (rc)
1453                         return rc;
1454         }
1455
1456         /* Start rx queues */
1457         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1458                 rc = cnxk_nix_rx_queue_start(eth_dev, i);
1459                 if (rc)
1460                         return rc;
1461         }
1462
1463         /* Start tx queues  */
1464         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1465                 rc = cnxk_nix_tx_queue_start(eth_dev, i);
1466                 if (rc)
1467                         return rc;
1468         }
1469
1470         /* Update Flow control configuration */
1471         rc = nix_update_flow_ctrl_config(eth_dev);
1472         if (rc) {
1473                 plt_err("Failed to enable flow control. error code(%d)", rc);
1474                 return rc;
1475         }
1476
1477         /* Enable Rx in NPC */
1478         rc = roc_nix_npc_rx_ena_dis(&dev->nix, true);
1479         if (rc) {
1480                 plt_err("Failed to enable NPC rx %d", rc);
1481                 return rc;
1482         }
1483
1484         cnxk_nix_toggle_flag_link_cfg(dev, true);
1485
1486         /* Start link change events */
1487         if (!roc_nix_is_vf_or_sdp(&dev->nix)) {
1488                 rc = roc_nix_mac_link_event_start_stop(&dev->nix, true);
1489                 if (rc) {
1490                         plt_err("Failed to start cgx link event %d", rc);
1491                         goto rx_disable;
1492                 }
1493         }
1494
1495         /* Enable PTP if it is requested by the user or already
1496          * enabled on PF owning this VF
1497          */
1498         memset(&dev->tstamp, 0, sizeof(struct cnxk_timesync_info));
1499         if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) || dev->ptp_en)
1500                 cnxk_eth_dev_ops.timesync_enable(eth_dev);
1501         else
1502                 cnxk_eth_dev_ops.timesync_disable(eth_dev);
1503
1504         if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
1505                 rc = rte_mbuf_dyn_rx_timestamp_register
1506                         (&dev->tstamp.tstamp_dynfield_offset,
1507                          &dev->tstamp.rx_tstamp_dynflag);
1508                 if (rc != 0) {
1509                         plt_err("Failed to register Rx timestamp field/flag");
1510                         goto rx_disable;
1511                 }
1512         }
1513
1514         cnxk_nix_toggle_flag_link_cfg(dev, false);
1515
1516         return 0;
1517
1518 rx_disable:
1519         roc_nix_npc_rx_ena_dis(&dev->nix, false);
1520         cnxk_nix_toggle_flag_link_cfg(dev, false);
1521         return rc;
1522 }
1523
1524 static int cnxk_nix_dev_reset(struct rte_eth_dev *eth_dev);
1525 static int cnxk_nix_dev_close(struct rte_eth_dev *eth_dev);
1526
1527 /* CNXK platform independent eth dev ops */
1528 struct eth_dev_ops cnxk_eth_dev_ops = {
1529         .mtu_set = cnxk_nix_mtu_set,
1530         .mac_addr_add = cnxk_nix_mac_addr_add,
1531         .mac_addr_remove = cnxk_nix_mac_addr_del,
1532         .mac_addr_set = cnxk_nix_mac_addr_set,
1533         .dev_infos_get = cnxk_nix_info_get,
1534         .link_update = cnxk_nix_link_update,
1535         .tx_queue_release = cnxk_nix_tx_queue_release,
1536         .rx_queue_release = cnxk_nix_rx_queue_release,
1537         .dev_stop = cnxk_nix_dev_stop,
1538         .dev_close = cnxk_nix_dev_close,
1539         .dev_reset = cnxk_nix_dev_reset,
1540         .tx_queue_start = cnxk_nix_tx_queue_start,
1541         .rx_queue_start = cnxk_nix_rx_queue_start,
1542         .rx_queue_stop = cnxk_nix_rx_queue_stop,
1543         .dev_supported_ptypes_get = cnxk_nix_supported_ptypes_get,
1544         .promiscuous_enable = cnxk_nix_promisc_enable,
1545         .promiscuous_disable = cnxk_nix_promisc_disable,
1546         .allmulticast_enable = cnxk_nix_allmulticast_enable,
1547         .allmulticast_disable = cnxk_nix_allmulticast_disable,
1548         .rx_burst_mode_get = cnxk_nix_rx_burst_mode_get,
1549         .tx_burst_mode_get = cnxk_nix_tx_burst_mode_get,
1550         .flow_ctrl_get = cnxk_nix_flow_ctrl_get,
1551         .flow_ctrl_set = cnxk_nix_flow_ctrl_set,
1552         .dev_set_link_up = cnxk_nix_set_link_up,
1553         .dev_set_link_down = cnxk_nix_set_link_down,
1554         .get_module_info = cnxk_nix_get_module_info,
1555         .get_module_eeprom = cnxk_nix_get_module_eeprom,
1556         .rx_queue_intr_enable = cnxk_nix_rx_queue_intr_enable,
1557         .rx_queue_intr_disable = cnxk_nix_rx_queue_intr_disable,
1558         .pool_ops_supported = cnxk_nix_pool_ops_supported,
1559         .queue_stats_mapping_set = cnxk_nix_queue_stats_mapping,
1560         .stats_get = cnxk_nix_stats_get,
1561         .stats_reset = cnxk_nix_stats_reset,
1562         .xstats_get = cnxk_nix_xstats_get,
1563         .xstats_get_names = cnxk_nix_xstats_get_names,
1564         .xstats_reset = cnxk_nix_xstats_reset,
1565         .xstats_get_by_id = cnxk_nix_xstats_get_by_id,
1566         .xstats_get_names_by_id = cnxk_nix_xstats_get_names_by_id,
1567         .fw_version_get = cnxk_nix_fw_version_get,
1568         .rxq_info_get = cnxk_nix_rxq_info_get,
1569         .txq_info_get = cnxk_nix_txq_info_get,
1570         .tx_done_cleanup = cnxk_nix_tx_done_cleanup,
1571         .flow_ops_get = cnxk_nix_flow_ops_get,
1572         .get_reg = cnxk_nix_dev_get_reg,
1573         .timesync_read_rx_timestamp = cnxk_nix_timesync_read_rx_timestamp,
1574         .timesync_read_tx_timestamp = cnxk_nix_timesync_read_tx_timestamp,
1575         .timesync_read_time = cnxk_nix_timesync_read_time,
1576         .timesync_write_time = cnxk_nix_timesync_write_time,
1577         .timesync_adjust_time = cnxk_nix_timesync_adjust_time,
1578         .read_clock = cnxk_nix_read_clock,
1579         .reta_update = cnxk_nix_reta_update,
1580         .reta_query = cnxk_nix_reta_query,
1581         .rss_hash_update = cnxk_nix_rss_hash_update,
1582         .rss_hash_conf_get = cnxk_nix_rss_hash_conf_get,
1583         .set_mc_addr_list = cnxk_nix_mc_addr_list_configure,
1584         .set_queue_rate_limit = cnxk_nix_tm_set_queue_rate_limit,
1585         .tm_ops_get = cnxk_nix_tm_ops_get,
1586         .mtr_ops_get = cnxk_nix_mtr_ops_get,
1587 };
1588
1589 static int
1590 cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)
1591 {
1592         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1593         struct rte_security_ctx *sec_ctx;
1594         struct roc_nix *nix = &dev->nix;
1595         struct rte_pci_device *pci_dev;
1596         int rc, max_entries;
1597
1598         eth_dev->dev_ops = &cnxk_eth_dev_ops;
1599         eth_dev->rx_queue_count = cnxk_nix_rx_queue_count;
1600         eth_dev->rx_descriptor_status = cnxk_nix_rx_descriptor_status;
1601         eth_dev->tx_descriptor_status = cnxk_nix_tx_descriptor_status;
1602
1603         /* Alloc security context */
1604         sec_ctx = plt_zmalloc(sizeof(struct rte_security_ctx), 0);
1605         if (!sec_ctx)
1606                 return -ENOMEM;
1607         sec_ctx->device = eth_dev;
1608         sec_ctx->ops = &cnxk_eth_sec_ops;
1609         sec_ctx->flags =
1610                 (RTE_SEC_CTX_F_FAST_SET_MDATA | RTE_SEC_CTX_F_FAST_GET_UDATA);
1611         eth_dev->security_ctx = sec_ctx;
1612
1613         /* For secondary processes, the primary has done all the work */
1614         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1615                 return 0;
1616
1617         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1618         rte_eth_copy_pci_info(eth_dev, pci_dev);
1619
1620         /* Parse devargs string */
1621         rc = cnxk_ethdev_parse_devargs(eth_dev->device->devargs, dev);
1622         if (rc) {
1623                 plt_err("Failed to parse devargs rc=%d", rc);
1624                 goto error;
1625         }
1626
1627         /* Initialize base roc nix */
1628         nix->pci_dev = pci_dev;
1629         nix->hw_vlan_ins = true;
1630         rc = roc_nix_dev_init(nix);
1631         if (rc) {
1632                 plt_err("Failed to initialize roc nix rc=%d", rc);
1633                 goto error;
1634         }
1635
1636         /* Register up msg callbacks */
1637         roc_nix_mac_link_cb_register(nix, cnxk_eth_dev_link_status_cb);
1638
1639         /* Register up msg callbacks */
1640         roc_nix_mac_link_info_get_cb_register(nix,
1641                                               cnxk_eth_dev_link_status_get_cb);
1642
1643         dev->eth_dev = eth_dev;
1644         dev->configured = 0;
1645         dev->ptype_disable = 0;
1646
1647         TAILQ_INIT(&dev->inb.list);
1648         TAILQ_INIT(&dev->outb.list);
1649         rte_spinlock_init(&dev->inb.lock);
1650         rte_spinlock_init(&dev->outb.lock);
1651
1652         /* For vfs, returned max_entries will be 0. but to keep default mac
1653          * address, one entry must be allocated. so setting up to 1.
1654          */
1655         if (roc_nix_is_vf_or_sdp(nix))
1656                 max_entries = 1;
1657         else
1658                 max_entries = roc_nix_mac_max_entries_get(nix);
1659
1660         if (max_entries <= 0) {
1661                 plt_err("Failed to get max entries for mac addr");
1662                 rc = -ENOTSUP;
1663                 goto dev_fini;
1664         }
1665
1666         eth_dev->data->mac_addrs =
1667                 rte_zmalloc("mac_addr", max_entries * RTE_ETHER_ADDR_LEN, 0);
1668         if (eth_dev->data->mac_addrs == NULL) {
1669                 plt_err("Failed to allocate memory for mac addr");
1670                 rc = -ENOMEM;
1671                 goto dev_fini;
1672         }
1673
1674         dev->max_mac_entries = max_entries;
1675         dev->dmac_filter_count = 1;
1676
1677         /* Get mac address */
1678         rc = roc_nix_npc_mac_addr_get(nix, dev->mac_addr);
1679         if (rc) {
1680                 plt_err("Failed to get mac addr, rc=%d", rc);
1681                 goto free_mac_addrs;
1682         }
1683
1684         /* Update the mac address */
1685         memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1686
1687         if (!roc_nix_is_vf_or_sdp(nix)) {
1688                 /* Sync same MAC address to CGX/RPM table */
1689                 rc = roc_nix_mac_addr_set(nix, dev->mac_addr);
1690                 if (rc) {
1691                         plt_err("Failed to set mac addr, rc=%d", rc);
1692                         goto free_mac_addrs;
1693                 }
1694         }
1695
1696         /* Union of all capabilities supported by CNXK.
1697          * Platform specific capabilities will be
1698          * updated later.
1699          */
1700         dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
1701         dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
1702         dev->speed_capa = nix_get_speed_capa(dev);
1703
1704         /* Initialize roc npc */
1705         dev->npc.roc_nix = nix;
1706         rc = roc_npc_init(&dev->npc);
1707         if (rc)
1708                 goto free_mac_addrs;
1709
1710         plt_nix_dbg("Port=%d pf=%d vf=%d ver=%s hwcap=0x%" PRIx64
1711                     " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
1712                     eth_dev->data->port_id, roc_nix_get_pf(nix),
1713                     roc_nix_get_vf(nix), CNXK_ETH_DEV_PMD_VERSION, dev->hwcap,
1714                     dev->rx_offload_capa, dev->tx_offload_capa);
1715         return 0;
1716
1717 free_mac_addrs:
1718         rte_free(eth_dev->data->mac_addrs);
1719 dev_fini:
1720         roc_nix_dev_fini(nix);
1721 error:
1722         plt_err("Failed to init nix eth_dev rc=%d", rc);
1723         return rc;
1724 }
1725
1726 static int
1727 cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool reset)
1728 {
1729         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1730         const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
1731         struct roc_nix *nix = &dev->nix;
1732         int rc, i;
1733
1734         plt_free(eth_dev->security_ctx);
1735         eth_dev->security_ctx = NULL;
1736
1737         /* Nothing to be done for secondary processes */
1738         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1739                 return 0;
1740
1741         /* Clear the flag since we are closing down */
1742         dev->configured = 0;
1743
1744         roc_nix_npc_rx_ena_dis(nix, false);
1745
1746         /* Disable and free rte_meter entries */
1747         nix_meter_fini(dev);
1748
1749         /* Disable and free rte_flow entries */
1750         roc_npc_fini(&dev->npc);
1751
1752         /* Disable link status events */
1753         roc_nix_mac_link_event_start_stop(nix, false);
1754
1755         /* Unregister the link update op, this is required to stop VFs from
1756          * receiving link status updates on exit path.
1757          */
1758         roc_nix_mac_link_cb_unregister(nix);
1759
1760         /* Free up SQs */
1761         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1762                 dev_ops->tx_queue_release(eth_dev, i);
1763                 eth_dev->data->tx_queues[i] = NULL;
1764         }
1765         eth_dev->data->nb_tx_queues = 0;
1766
1767         /* Free up RQ's and CQ's */
1768         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1769                 dev_ops->rx_queue_release(eth_dev, i);
1770                 eth_dev->data->rx_queues[i] = NULL;
1771         }
1772         eth_dev->data->nb_rx_queues = 0;
1773
1774         /* Free security resources */
1775         nix_security_release(dev);
1776
1777         /* Free tm resources */
1778         roc_nix_tm_fini(nix);
1779
1780         /* Unregister queue irqs */
1781         roc_nix_unregister_queue_irqs(nix);
1782
1783         /* Unregister cq irqs */
1784         if (eth_dev->data->dev_conf.intr_conf.rxq)
1785                 roc_nix_unregister_cq_irqs(nix);
1786
1787         /* Free ROC RQ's, SQ's and CQ's memory */
1788         nix_free_queue_mem(dev);
1789
1790         /* Free nix lf resources */
1791         rc = roc_nix_lf_free(nix);
1792         if (rc)
1793                 plt_err("Failed to free nix lf, rc=%d", rc);
1794
1795         rte_free(eth_dev->data->mac_addrs);
1796         eth_dev->data->mac_addrs = NULL;
1797
1798         rc = roc_nix_dev_fini(nix);
1799         /* Can be freed later by PMD if NPA LF is in use */
1800         if (rc == -EAGAIN) {
1801                 if (!reset)
1802                         eth_dev->data->dev_private = NULL;
1803                 return 0;
1804         } else if (rc) {
1805                 plt_err("Failed in nix dev fini, rc=%d", rc);
1806         }
1807
1808         return rc;
1809 }
1810
1811 static int
1812 cnxk_nix_dev_close(struct rte_eth_dev *eth_dev)
1813 {
1814         cnxk_eth_dev_uninit(eth_dev, false);
1815         return 0;
1816 }
1817
1818 static int
1819 cnxk_nix_dev_reset(struct rte_eth_dev *eth_dev)
1820 {
1821         int rc;
1822
1823         rc = cnxk_eth_dev_uninit(eth_dev, true);
1824         if (rc)
1825                 return rc;
1826
1827         return cnxk_eth_dev_init(eth_dev);
1828 }
1829
1830 int
1831 cnxk_nix_remove(struct rte_pci_device *pci_dev)
1832 {
1833         struct rte_eth_dev *eth_dev;
1834         struct roc_nix *nix;
1835         int rc = -EINVAL;
1836
1837         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
1838         if (eth_dev) {
1839                 /* Cleanup eth dev */
1840                 rc = cnxk_eth_dev_uninit(eth_dev, false);
1841                 if (rc)
1842                         return rc;
1843
1844                 rte_eth_dev_release_port(eth_dev);
1845         }
1846
1847         /* Nothing to be done for secondary processes */
1848         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1849                 return 0;
1850
1851         /* Check if this device is hosting common resource */
1852         nix = roc_idev_npa_nix_get();
1853         if (nix->pci_dev != pci_dev)
1854                 return 0;
1855
1856         /* Try nix fini now */
1857         rc = roc_nix_dev_fini(nix);
1858         if (rc == -EAGAIN) {
1859                 plt_info("%s: common resource in use by other devices",
1860                          pci_dev->name);
1861                 goto exit;
1862         } else if (rc) {
1863                 plt_err("Failed in nix dev fini, rc=%d", rc);
1864                 goto exit;
1865         }
1866
1867         /* Free device pointer as rte_ethdev does not have it anymore */
1868         rte_free(nix);
1869 exit:
1870         return rc;
1871 }
1872
1873 int
1874 cnxk_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1875 {
1876         int rc;
1877
1878         RTE_SET_USED(pci_drv);
1879
1880         rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct cnxk_eth_dev),
1881                                            cnxk_eth_dev_init);
1882
1883         /* On error on secondary, recheck if port exists in primary or
1884          * in mid of detach state.
1885          */
1886         if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
1887                 if (!rte_eth_dev_allocated(pci_dev->device.name))
1888                         return 0;
1889         return rc;
1890 }