1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
4 #include <cnxk_ethdev.h>
7 nix_get_rx_offload_capa(struct cnxk_eth_dev *dev)
9 uint64_t capa = CNXK_NIX_RX_OFFLOAD_CAPA;
11 if (roc_nix_is_vf_or_sdp(&dev->nix) ||
12 dev->npc.switch_header_type == ROC_PRIV_FLAGS_HIGIG)
13 capa &= ~RTE_ETH_RX_OFFLOAD_TIMESTAMP;
18 static inline uint64_t
19 nix_get_tx_offload_capa(struct cnxk_eth_dev *dev)
22 return CNXK_NIX_TX_OFFLOAD_CAPA;
25 static inline uint32_t
26 nix_get_speed_capa(struct cnxk_eth_dev *dev)
30 /* Auto negotiation disabled */
31 speed_capa = RTE_ETH_LINK_SPEED_FIXED;
32 if (!roc_nix_is_vf_or_sdp(&dev->nix) && !roc_nix_is_lbk(&dev->nix)) {
33 speed_capa |= RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G |
34 RTE_ETH_LINK_SPEED_25G | RTE_ETH_LINK_SPEED_40G |
35 RTE_ETH_LINK_SPEED_50G | RTE_ETH_LINK_SPEED_100G;
42 cnxk_nix_inb_mode_set(struct cnxk_eth_dev *dev, bool use_inl_dev)
44 struct roc_nix *nix = &dev->nix;
46 if (dev->inb.inl_dev == use_inl_dev)
49 plt_nix_dbg("Security sessions(%u) still active, inl=%u!!!",
50 dev->inb.nb_sess, !!dev->inb.inl_dev);
53 dev->inb.inl_dev = use_inl_dev;
55 /* Update RoC for NPC rule insertion */
56 roc_nix_inb_mode_set(nix, use_inl_dev);
58 /* Setup lookup mem */
59 return cnxk_nix_lookup_mem_sa_base_set(dev);
63 nix_security_setup(struct cnxk_eth_dev *dev)
65 struct roc_nix *nix = &dev->nix;
68 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
69 /* Setup Inline Inbound */
70 rc = roc_nix_inl_inb_init(nix);
72 plt_err("Failed to initialize nix inline inb, rc=%d",
77 /* By default pick using inline device for poll mode.
78 * Will be overridden when event mode rq's are setup.
80 cnxk_nix_inb_mode_set(dev, true);
82 /* Allocate memory to be used as dptr for CPT ucode
86 plt_zmalloc(ROC_NIX_INL_OT_IPSEC_INB_HW_SZ, 0);
87 if (!dev->inb.sa_dptr) {
88 plt_err("Couldn't allocate memory for SA dptr");
94 if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY ||
95 dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
96 struct plt_bitmap *bmap;
100 /* Setup enough descriptors for all tx queues */
101 nix->outb_nb_desc = dev->outb.nb_desc;
102 nix->outb_nb_crypto_qs = dev->outb.nb_crypto_qs;
104 /* Setup Inline Outbound */
105 rc = roc_nix_inl_outb_init(nix);
107 plt_err("Failed to initialize nix inline outb, rc=%d",
112 dev->outb.lf_base = roc_nix_inl_outb_lf_base_get(nix);
114 /* Skip the rest if DEV_TX_OFFLOAD_SECURITY is not enabled */
115 if (!(dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY))
118 /* Allocate memory to be used as dptr for CPT ucode
122 plt_zmalloc(ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ, 0);
123 if (!dev->outb.sa_dptr) {
124 plt_err("Couldn't allocate memory for SA dptr");
130 /* Allocate a bitmap to alloc and free sa indexes */
131 bmap_sz = plt_bitmap_get_memory_footprint(dev->outb.max_sa);
132 mem = plt_zmalloc(bmap_sz, PLT_CACHE_LINE_SIZE);
134 plt_err("Outbound SA bmap alloc failed");
136 rc |= roc_nix_inl_outb_fini(nix);
141 bmap = plt_bitmap_init(dev->outb.max_sa, mem, bmap_sz);
143 plt_err("Outbound SA bmap init failed");
145 rc |= roc_nix_inl_outb_fini(nix);
150 for (i = 0; i < dev->outb.max_sa; i++)
151 plt_bitmap_set(bmap, i);
153 dev->outb.sa_base = roc_nix_inl_outb_sa_base_get(nix);
154 dev->outb.sa_bmap_mem = mem;
155 dev->outb.sa_bmap = bmap;
160 if (dev->inb.sa_dptr)
161 plt_free(dev->inb.sa_dptr);
162 if (dev->outb.sa_dptr)
163 plt_free(dev->outb.sa_dptr);
165 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)
166 rc |= roc_nix_inl_inb_fini(nix);
171 nix_meter_fini(struct cnxk_eth_dev *dev)
173 struct cnxk_meter_node *next_mtr = NULL;
174 struct roc_nix_bpf_objs profs = {0};
175 struct cnxk_meter_node *mtr = NULL;
176 struct cnxk_mtr *fms = &dev->mtr;
177 struct roc_nix *nix = &dev->nix;
178 struct roc_nix_rq *rq;
182 RTE_TAILQ_FOREACH_SAFE(mtr, fms, next, next_mtr) {
183 for (i = 0; i < mtr->rq_num; i++) {
184 rq = &dev->rqs[mtr->rq_id[i]];
185 rc |= roc_nix_bpf_ena_dis(nix, mtr->bpf_id, rq, false);
188 profs.level = mtr->level;
190 profs.ids[0] = mtr->bpf_id;
191 rc = roc_nix_bpf_free(nix, &profs, 1);
196 TAILQ_REMOVE(fms, mtr, next);
203 nix_security_release(struct cnxk_eth_dev *dev)
205 struct rte_eth_dev *eth_dev = dev->eth_dev;
206 struct cnxk_eth_sec_sess *eth_sec, *tvar;
207 struct roc_nix *nix = &dev->nix;
210 /* Cleanup Inline inbound */
211 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
212 /* Destroy inbound sessions */
214 RTE_TAILQ_FOREACH_SAFE(eth_sec, &dev->inb.list, entry, tvar)
215 cnxk_eth_sec_ops.session_destroy(eth_dev,
218 /* Clear lookup mem */
219 cnxk_nix_lookup_mem_sa_base_clear(dev);
221 rc = roc_nix_inl_inb_fini(nix);
223 plt_err("Failed to cleanup nix inline inb, rc=%d", rc);
226 if (dev->inb.sa_dptr) {
227 plt_free(dev->inb.sa_dptr);
228 dev->inb.sa_dptr = NULL;
232 /* Cleanup Inline outbound */
233 if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY ||
234 dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
235 /* Destroy outbound sessions */
237 RTE_TAILQ_FOREACH_SAFE(eth_sec, &dev->outb.list, entry, tvar)
238 cnxk_eth_sec_ops.session_destroy(eth_dev,
241 rc = roc_nix_inl_outb_fini(nix);
243 plt_err("Failed to cleanup nix inline outb, rc=%d", rc);
246 plt_bitmap_free(dev->outb.sa_bmap);
247 plt_free(dev->outb.sa_bmap_mem);
248 dev->outb.sa_bmap = NULL;
249 dev->outb.sa_bmap_mem = NULL;
250 if (dev->outb.sa_dptr) {
251 plt_free(dev->outb.sa_dptr);
252 dev->outb.sa_dptr = NULL;
256 dev->inb.inl_dev = false;
257 roc_nix_inb_mode_set(nix, false);
259 dev->inb.nb_sess = 0;
260 dev->outb.nb_sess = 0;
265 nix_enable_mseg_on_jumbo(struct cnxk_eth_rxq_sp *rxq)
267 struct rte_pktmbuf_pool_private *mbp_priv;
268 struct rte_eth_dev *eth_dev;
269 struct cnxk_eth_dev *dev;
273 eth_dev = dev->eth_dev;
275 /* Get rx buffer size */
276 mbp_priv = rte_mempool_get_priv(rxq->qconf.mp);
277 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
279 if (eth_dev->data->mtu + (uint32_t)CNXK_NIX_L2_OVERHEAD > buffsz) {
280 dev->rx_offloads |= RTE_ETH_RX_OFFLOAD_SCATTER;
281 dev->tx_offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
286 nix_recalc_mtu(struct rte_eth_dev *eth_dev)
288 struct rte_eth_dev_data *data = eth_dev->data;
289 struct cnxk_eth_rxq_sp *rxq;
292 rxq = ((struct cnxk_eth_rxq_sp *)data->rx_queues[0]) - 1;
293 /* Setup scatter mode if needed by jumbo */
294 nix_enable_mseg_on_jumbo(rxq);
296 rc = cnxk_nix_mtu_set(eth_dev, data->mtu);
298 plt_err("Failed to set default MTU size, rc=%d", rc);
304 nix_init_flow_ctrl_config(struct rte_eth_dev *eth_dev)
306 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
307 struct cnxk_fc_cfg *fc = &dev->fc_cfg;
308 struct rte_eth_fc_conf fc_conf = {0};
311 /* Both Rx & Tx flow ctrl get enabled(RTE_ETH_FC_FULL) in HW
312 * by AF driver, update those info in PMD structure.
314 rc = cnxk_nix_flow_ctrl_get(eth_dev, &fc_conf);
318 fc->mode = fc_conf.mode;
319 fc->rx_pause = (fc_conf.mode == RTE_ETH_FC_FULL) ||
320 (fc_conf.mode == RTE_ETH_FC_RX_PAUSE);
321 fc->tx_pause = (fc_conf.mode == RTE_ETH_FC_FULL) ||
322 (fc_conf.mode == RTE_ETH_FC_TX_PAUSE);
329 nix_update_flow_ctrl_config(struct rte_eth_dev *eth_dev)
331 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
332 struct cnxk_fc_cfg *fc = &dev->fc_cfg;
333 struct rte_eth_fc_conf fc_cfg = {0};
335 if (roc_nix_is_vf_or_sdp(&dev->nix) && !roc_nix_is_lbk(&dev->nix))
338 fc_cfg.mode = fc->mode;
340 /* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */
341 if (roc_model_is_cn96_ax() &&
342 dev->npc.switch_header_type != ROC_PRIV_FLAGS_HIGIG &&
343 (fc_cfg.mode == RTE_ETH_FC_FULL || fc_cfg.mode == RTE_ETH_FC_RX_PAUSE)) {
345 (fc_cfg.mode == RTE_ETH_FC_FULL ||
346 fc_cfg.mode == RTE_ETH_FC_TX_PAUSE) ?
347 RTE_ETH_FC_TX_PAUSE : RTE_ETH_FC_NONE;
350 return cnxk_nix_flow_ctrl_set(eth_dev, &fc_cfg);
354 cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev)
356 uint16_t port_id = dev->eth_dev->data->port_id;
357 struct rte_mbuf mb_def;
360 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
361 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
362 offsetof(struct rte_mbuf, data_off) !=
364 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
365 offsetof(struct rte_mbuf, data_off) !=
367 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
368 offsetof(struct rte_mbuf, data_off) !=
371 mb_def.data_off = RTE_PKTMBUF_HEADROOM +
372 (dev->ptp_en * CNXK_NIX_TIMESYNC_RX_OFFSET);
373 mb_def.port = port_id;
374 rte_mbuf_refcnt_set(&mb_def, 1);
376 /* Prevent compiler reordering: rearm_data covers previous fields */
377 rte_compiler_barrier();
378 tmp = (uint64_t *)&mb_def.rearm_data;
383 static inline uint8_t
384 nix_sq_max_sqe_sz(struct cnxk_eth_dev *dev)
387 * Maximum three segments can be supported with W8, Choose
388 * NIX_MAXSQESZ_W16 for multi segment offload.
390 if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_MULTI_SEGS)
391 return NIX_MAXSQESZ_W16;
393 return NIX_MAXSQESZ_W8;
397 cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
398 uint16_t nb_desc, uint16_t fp_tx_q_sz,
399 const struct rte_eth_txconf *tx_conf)
401 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
402 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
403 struct cnxk_eth_txq_sp *txq_sp;
404 struct roc_nix_sq *sq;
408 /* Free memory prior to re-allocation if needed. */
409 if (eth_dev->data->tx_queues[qid] != NULL) {
410 plt_nix_dbg("Freeing memory prior to re-allocation %d", qid);
411 dev_ops->tx_queue_release(eth_dev, qid);
412 eth_dev->data->tx_queues[qid] = NULL;
415 /* When Tx Security offload is enabled, increase tx desc count by
416 * max possible outbound desc count.
418 if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY)
419 nb_desc += dev->outb.nb_desc;
424 sq->nb_desc = nb_desc;
425 sq->max_sqe_sz = nix_sq_max_sqe_sz(dev);
427 rc = roc_nix_sq_init(&dev->nix, sq);
429 plt_err("Failed to init sq=%d, rc=%d", qid, rc);
434 txq_sz = sizeof(struct cnxk_eth_txq_sp) + fp_tx_q_sz;
435 txq_sp = plt_zmalloc(txq_sz, PLT_CACHE_LINE_SIZE);
437 plt_err("Failed to alloc tx queue mem");
438 rc |= roc_nix_sq_fini(sq);
444 txq_sp->qconf.conf.tx = *tx_conf;
445 /* Queue config should reflect global offloads */
446 txq_sp->qconf.conf.tx.offloads = dev->tx_offloads;
447 txq_sp->qconf.nb_desc = nb_desc;
449 plt_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " lmt_addr=%p"
450 " nb_sqb_bufs=%d sqes_per_sqb_log2=%d",
451 qid, sq->fc, dev->tx_offloads, sq->lmt_addr,
452 sq->nb_sqb_bufs, sq->sqes_per_sqb_log2);
454 /* Store start of fast path area */
455 eth_dev->data->tx_queues[qid] = txq_sp + 1;
456 eth_dev->data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
461 cnxk_nix_tx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)
463 void *txq = eth_dev->data->tx_queues[qid];
464 struct cnxk_eth_txq_sp *txq_sp;
465 struct cnxk_eth_dev *dev;
466 struct roc_nix_sq *sq;
472 txq_sp = cnxk_eth_txq_to_sp(txq);
476 plt_nix_dbg("Releasing txq %u", qid);
480 rc = roc_nix_sq_fini(sq);
482 plt_err("Failed to cleanup sq, rc=%d", rc);
489 cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
490 uint16_t nb_desc, uint16_t fp_rx_q_sz,
491 const struct rte_eth_rxconf *rx_conf,
492 struct rte_mempool *mp)
494 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
495 struct roc_nix *nix = &dev->nix;
496 struct cnxk_eth_rxq_sp *rxq_sp;
497 struct rte_mempool_ops *ops;
498 const char *platform_ops;
499 struct roc_nix_rq *rq;
500 struct roc_nix_cq *cq;
506 if (rx_conf->rx_deferred_start == 1) {
507 plt_err("Deferred Rx start is not supported");
511 platform_ops = rte_mbuf_platform_mempool_ops();
512 /* This driver needs cnxk_npa mempool ops to work */
513 ops = rte_mempool_get_ops(mp->ops_index);
514 if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
515 plt_err("mempool ops should be of cnxk_npa type");
519 if (mp->pool_id == 0) {
520 plt_err("Invalid pool_id");
524 /* Free memory prior to re-allocation if needed */
525 if (eth_dev->data->rx_queues[qid] != NULL) {
526 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
528 plt_nix_dbg("Freeing memory prior to re-allocation %d", qid);
529 dev_ops->rx_queue_release(eth_dev, qid);
530 eth_dev->data->rx_queues[qid] = NULL;
533 /* Clam up cq limit to size of packet pool aura for LBK
534 * to avoid meta packet drop as LBK does not currently support
537 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY && roc_nix_is_lbk(nix)) {
538 uint64_t pkt_pool_limit = roc_nix_inl_dev_rq_limit_get();
540 /* Use current RQ's aura limit if inl rq is not available */
542 pkt_pool_limit = roc_npa_aura_op_limit_get(mp->pool_id);
543 nb_desc = RTE_MAX(nb_desc, pkt_pool_limit);
549 cq->nb_desc = nb_desc;
550 rc = roc_nix_cq_init(&dev->nix, cq);
552 plt_err("Failed to init roc cq for rq=%d, rc=%d", qid, rc);
559 rq->aura_handle = mp->pool_id;
560 rq->flow_tag_width = 32;
563 /* Calculate first mbuf skip */
564 first_skip = (sizeof(struct rte_mbuf));
565 first_skip += RTE_PKTMBUF_HEADROOM;
566 first_skip += rte_pktmbuf_priv_size(mp);
567 rq->first_skip = first_skip;
568 rq->later_skip = sizeof(struct rte_mbuf);
569 rq->lpb_size = mp->elt_size;
571 /* Enable Inline IPSec on RQ, will not be used for Poll mode */
572 if (roc_nix_inl_inb_is_enabled(nix))
573 rq->ipsech_ena = true;
575 rc = roc_nix_rq_init(&dev->nix, rq, !!eth_dev->data->dev_started);
577 plt_err("Failed to init roc rq for rq=%d, rc=%d", qid, rc);
581 /* Allocate and setup fast path rx queue */
583 rxq_sz = sizeof(struct cnxk_eth_rxq_sp) + fp_rx_q_sz;
584 rxq_sp = plt_zmalloc(rxq_sz, PLT_CACHE_LINE_SIZE);
586 plt_err("Failed to alloc rx queue for rq=%d", qid);
590 /* Setup slow path fields */
593 rxq_sp->qconf.conf.rx = *rx_conf;
594 /* Queue config should reflect global offloads */
595 rxq_sp->qconf.conf.rx.offloads = dev->rx_offloads;
596 rxq_sp->qconf.nb_desc = nb_desc;
597 rxq_sp->qconf.mp = mp;
599 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
600 /* Setup rq reference for inline dev if present */
601 rc = roc_nix_inl_dev_rq_get(rq);
606 plt_nix_dbg("rq=%d pool=%s nb_desc=%d->%d", qid, mp->name, nb_desc,
609 /* Store start of fast path area */
610 eth_dev->data->rx_queues[qid] = rxq_sp + 1;
611 eth_dev->data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
613 /* Calculating delta and freq mult between PTP HI clock and tsc.
614 * These are needed in deriving raw clock value from tsc counter.
615 * read_clock eth op returns raw clock value.
617 if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) || dev->ptp_en) {
618 rc = cnxk_nix_tsc_convert(dev);
620 plt_err("Failed to calculate delta and freq mult");
629 rc |= roc_nix_rq_fini(rq);
631 rc |= roc_nix_cq_fini(cq);
637 cnxk_nix_rx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)
639 void *rxq = eth_dev->data->rx_queues[qid];
640 struct cnxk_eth_rxq_sp *rxq_sp;
641 struct cnxk_eth_dev *dev;
642 struct roc_nix_rq *rq;
643 struct roc_nix_cq *cq;
649 rxq_sp = cnxk_eth_rxq_to_sp(rxq);
653 plt_nix_dbg("Releasing rxq %u", qid);
655 /* Release rq reference for inline dev if present */
656 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)
657 roc_nix_inl_dev_rq_put(rq);
660 rc = roc_nix_rq_fini(rq);
662 plt_err("Failed to cleanup rq, rc=%d", rc);
666 rc = roc_nix_cq_fini(cq);
668 plt_err("Failed to cleanup cq, rc=%d", rc);
670 /* Finally free fast path area */
675 cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
678 uint32_t flow_key_type[RSS_MAX_LEVELS][6] = {
679 {FLOW_KEY_TYPE_IPV4, FLOW_KEY_TYPE_IPV6, FLOW_KEY_TYPE_TCP,
680 FLOW_KEY_TYPE_UDP, FLOW_KEY_TYPE_SCTP, FLOW_KEY_TYPE_ETH_DMAC},
681 {FLOW_KEY_TYPE_INNR_IPV4, FLOW_KEY_TYPE_INNR_IPV6,
682 FLOW_KEY_TYPE_INNR_TCP, FLOW_KEY_TYPE_INNR_UDP,
683 FLOW_KEY_TYPE_INNR_SCTP, FLOW_KEY_TYPE_INNR_ETH_DMAC},
684 {FLOW_KEY_TYPE_IPV4 | FLOW_KEY_TYPE_INNR_IPV4,
685 FLOW_KEY_TYPE_IPV6 | FLOW_KEY_TYPE_INNR_IPV6,
686 FLOW_KEY_TYPE_TCP | FLOW_KEY_TYPE_INNR_TCP,
687 FLOW_KEY_TYPE_UDP | FLOW_KEY_TYPE_INNR_UDP,
688 FLOW_KEY_TYPE_SCTP | FLOW_KEY_TYPE_INNR_SCTP,
689 FLOW_KEY_TYPE_ETH_DMAC | FLOW_KEY_TYPE_INNR_ETH_DMAC}
691 uint32_t flowkey_cfg = 0;
693 dev->ethdev_rss_hf = ethdev_rss;
695 if (ethdev_rss & RTE_ETH_RSS_L2_PAYLOAD &&
696 dev->npc.switch_header_type == ROC_PRIV_FLAGS_LEN_90B) {
697 flowkey_cfg |= FLOW_KEY_TYPE_CH_LEN_90B;
700 if (ethdev_rss & RTE_ETH_RSS_C_VLAN)
701 flowkey_cfg |= FLOW_KEY_TYPE_VLAN;
703 if (ethdev_rss & RTE_ETH_RSS_L3_SRC_ONLY)
704 flowkey_cfg |= FLOW_KEY_TYPE_L3_SRC;
706 if (ethdev_rss & RTE_ETH_RSS_L3_DST_ONLY)
707 flowkey_cfg |= FLOW_KEY_TYPE_L3_DST;
709 if (ethdev_rss & RTE_ETH_RSS_L4_SRC_ONLY)
710 flowkey_cfg |= FLOW_KEY_TYPE_L4_SRC;
712 if (ethdev_rss & RTE_ETH_RSS_L4_DST_ONLY)
713 flowkey_cfg |= FLOW_KEY_TYPE_L4_DST;
715 if (ethdev_rss & RSS_IPV4_ENABLE)
716 flowkey_cfg |= flow_key_type[rss_level][RSS_IPV4_INDEX];
718 if (ethdev_rss & RSS_IPV6_ENABLE)
719 flowkey_cfg |= flow_key_type[rss_level][RSS_IPV6_INDEX];
721 if (ethdev_rss & RTE_ETH_RSS_TCP)
722 flowkey_cfg |= flow_key_type[rss_level][RSS_TCP_INDEX];
724 if (ethdev_rss & RTE_ETH_RSS_UDP)
725 flowkey_cfg |= flow_key_type[rss_level][RSS_UDP_INDEX];
727 if (ethdev_rss & RTE_ETH_RSS_SCTP)
728 flowkey_cfg |= flow_key_type[rss_level][RSS_SCTP_INDEX];
730 if (ethdev_rss & RTE_ETH_RSS_L2_PAYLOAD)
731 flowkey_cfg |= flow_key_type[rss_level][RSS_DMAC_INDEX];
733 if (ethdev_rss & RSS_IPV6_EX_ENABLE)
734 flowkey_cfg |= FLOW_KEY_TYPE_IPV6_EXT;
736 if (ethdev_rss & RTE_ETH_RSS_PORT)
737 flowkey_cfg |= FLOW_KEY_TYPE_PORT;
739 if (ethdev_rss & RTE_ETH_RSS_NVGRE)
740 flowkey_cfg |= FLOW_KEY_TYPE_NVGRE;
742 if (ethdev_rss & RTE_ETH_RSS_VXLAN)
743 flowkey_cfg |= FLOW_KEY_TYPE_VXLAN;
745 if (ethdev_rss & RTE_ETH_RSS_GENEVE)
746 flowkey_cfg |= FLOW_KEY_TYPE_GENEVE;
748 if (ethdev_rss & RTE_ETH_RSS_GTPU)
749 flowkey_cfg |= FLOW_KEY_TYPE_GTPU;
755 nix_free_queue_mem(struct cnxk_eth_dev *dev)
766 nix_ingress_policer_setup(struct cnxk_eth_dev *dev)
768 struct rte_eth_dev *eth_dev = dev->eth_dev;
771 TAILQ_INIT(&dev->mtr_profiles);
772 TAILQ_INIT(&dev->mtr_policy);
773 TAILQ_INIT(&dev->mtr);
775 if (eth_dev->dev_ops->mtr_ops_get == NULL)
778 return nix_mtr_capabilities_init(eth_dev);
782 nix_rss_default_setup(struct cnxk_eth_dev *dev)
784 struct rte_eth_dev *eth_dev = dev->eth_dev;
785 uint8_t rss_hash_level;
786 uint32_t flowkey_cfg;
789 rss_hf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
790 rss_hash_level = RTE_ETH_RSS_LEVEL(rss_hf);
794 flowkey_cfg = cnxk_rss_ethdev_to_nix(dev, rss_hf, rss_hash_level);
795 return roc_nix_rss_default_setup(&dev->nix, flowkey_cfg);
799 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
801 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
802 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
803 struct cnxk_eth_qconf *tx_qconf = NULL;
804 struct cnxk_eth_qconf *rx_qconf = NULL;
805 struct cnxk_eth_rxq_sp *rxq_sp;
806 struct cnxk_eth_txq_sp *txq_sp;
807 int i, nb_rxq, nb_txq;
810 nb_rxq = RTE_MIN(dev->nb_rxq, eth_dev->data->nb_rx_queues);
811 nb_txq = RTE_MIN(dev->nb_txq, eth_dev->data->nb_tx_queues);
813 tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
814 if (tx_qconf == NULL) {
815 plt_err("Failed to allocate memory for tx_qconf");
819 rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
820 if (rx_qconf == NULL) {
821 plt_err("Failed to allocate memory for rx_qconf");
825 txq = eth_dev->data->tx_queues;
826 for (i = 0; i < nb_txq; i++) {
827 if (txq[i] == NULL) {
828 tx_qconf[i].valid = false;
829 plt_info("txq[%d] is already released", i);
832 txq_sp = cnxk_eth_txq_to_sp(txq[i]);
833 memcpy(&tx_qconf[i], &txq_sp->qconf, sizeof(*tx_qconf));
834 tx_qconf[i].valid = true;
835 dev_ops->tx_queue_release(eth_dev, i);
836 eth_dev->data->tx_queues[i] = NULL;
839 rxq = eth_dev->data->rx_queues;
840 for (i = 0; i < nb_rxq; i++) {
841 if (rxq[i] == NULL) {
842 rx_qconf[i].valid = false;
843 plt_info("rxq[%d] is already released", i);
846 rxq_sp = cnxk_eth_rxq_to_sp(rxq[i]);
847 memcpy(&rx_qconf[i], &rxq_sp->qconf, sizeof(*rx_qconf));
848 rx_qconf[i].valid = true;
849 dev_ops->rx_queue_release(eth_dev, i);
850 eth_dev->data->rx_queues[i] = NULL;
853 dev->tx_qconf = tx_qconf;
854 dev->rx_qconf = rx_qconf;
864 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
866 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
867 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
868 struct cnxk_eth_qconf *tx_qconf = dev->tx_qconf;
869 struct cnxk_eth_qconf *rx_qconf = dev->rx_qconf;
870 int rc, i, nb_rxq, nb_txq;
872 nb_rxq = RTE_MIN(dev->nb_rxq, eth_dev->data->nb_rx_queues);
873 nb_txq = RTE_MIN(dev->nb_txq, eth_dev->data->nb_tx_queues);
876 /* Setup tx & rx queues with previous configuration so
877 * that the queues can be functional in cases like ports
878 * are started without re configuring queues.
880 * Usual re config sequence is like below:
886 * queue_configure() {
893 * In some application's control path, queue_configure() would
894 * NOT be invoked for TXQs/RXQs in port_configure().
895 * In such cases, queues can be functional after start as the
896 * queues are already setup in port_configure().
898 for (i = 0; i < nb_txq; i++) {
899 if (!tx_qconf[i].valid)
901 rc = dev_ops->tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc, 0,
902 &tx_qconf[i].conf.tx);
904 plt_err("Failed to setup tx queue rc=%d", rc);
905 for (i -= 1; i >= 0; i--)
906 dev_ops->tx_queue_release(eth_dev, i);
914 for (i = 0; i < nb_rxq; i++) {
915 if (!rx_qconf[i].valid)
917 rc = dev_ops->rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc, 0,
918 &rx_qconf[i].conf.rx,
921 plt_err("Failed to setup rx queue rc=%d", rc);
922 for (i -= 1; i >= 0; i--)
923 dev_ops->rx_queue_release(eth_dev, i);
924 goto tx_queue_release;
934 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
935 dev_ops->tx_queue_release(eth_dev, i);
944 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
946 /* These dummy functions are required for supporting
947 * some applications which reconfigure queues without
948 * stopping tx burst and rx burst threads(eg kni app)
949 * When the queues context is saved, txq/rxqs are released
950 * which caused app crash since rx/tx burst is still
951 * on different lcores
953 eth_dev->tx_pkt_burst = rte_eth_pkt_burst_dummy;
954 eth_dev->rx_pkt_burst = rte_eth_pkt_burst_dummy;
959 nix_lso_tun_fmt_update(struct cnxk_eth_dev *dev)
961 uint8_t udp_tun[ROC_NIX_LSO_TUN_MAX];
962 uint8_t tun[ROC_NIX_LSO_TUN_MAX];
963 struct roc_nix *nix = &dev->nix;
966 rc = roc_nix_lso_fmt_get(nix, udp_tun, tun);
970 dev->lso_tun_fmt = ((uint64_t)tun[ROC_NIX_LSO_TUN_V4V4] |
971 (uint64_t)tun[ROC_NIX_LSO_TUN_V4V6] << 8 |
972 (uint64_t)tun[ROC_NIX_LSO_TUN_V6V4] << 16 |
973 (uint64_t)tun[ROC_NIX_LSO_TUN_V6V6] << 24);
975 dev->lso_tun_fmt |= ((uint64_t)udp_tun[ROC_NIX_LSO_TUN_V4V4] << 32 |
976 (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V4V6] << 40 |
977 (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V6V4] << 48 |
978 (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V6V6] << 56);
983 nix_lso_fmt_setup(struct cnxk_eth_dev *dev)
985 struct roc_nix *nix = &dev->nix;
988 /* Nothing much to do if offload is not enabled */
989 if (!(dev->tx_offloads &
990 (RTE_ETH_TX_OFFLOAD_TCP_TSO | RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
991 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO | RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO)))
994 /* Setup LSO formats in AF. Its a no-op if other ethdev has
997 rc = roc_nix_lso_fmt_setup(nix);
1001 return nix_lso_tun_fmt_update(dev);
1005 cnxk_nix_configure(struct rte_eth_dev *eth_dev)
1007 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1008 struct rte_eth_dev_data *data = eth_dev->data;
1009 struct rte_eth_conf *conf = &data->dev_conf;
1010 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1011 struct rte_eth_txmode *txmode = &conf->txmode;
1012 char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
1013 struct roc_nix_fc_cfg fc_cfg = {0};
1014 struct roc_nix *nix = &dev->nix;
1015 struct rte_ether_addr *ea;
1016 uint8_t nb_rxq, nb_txq;
1024 if (rte_eal_has_hugepages() == 0) {
1025 plt_err("Huge page is not configured");
1026 goto fail_configure;
1029 if (conf->dcb_capability_en == 1) {
1030 plt_err("dcb enable is not supported");
1031 goto fail_configure;
1034 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1035 plt_err("Flow director is not supported");
1036 goto fail_configure;
1039 if (rxmode->mq_mode != RTE_ETH_MQ_RX_NONE &&
1040 rxmode->mq_mode != RTE_ETH_MQ_RX_RSS) {
1041 plt_err("Unsupported mq rx mode %d", rxmode->mq_mode);
1042 goto fail_configure;
1045 if (txmode->mq_mode != RTE_ETH_MQ_TX_NONE) {
1046 plt_err("Unsupported mq tx mode %d", txmode->mq_mode);
1047 goto fail_configure;
1050 /* Free the resources allocated from the previous configure */
1051 if (dev->configured == 1) {
1052 /* Unregister queue irq's */
1053 roc_nix_unregister_queue_irqs(nix);
1055 /* Unregister CQ irqs if present */
1056 if (eth_dev->data->dev_conf.intr_conf.rxq)
1057 roc_nix_unregister_cq_irqs(nix);
1059 /* Set no-op functions */
1060 nix_set_nop_rxtx_function(eth_dev);
1061 /* Store queue config for later */
1062 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1064 goto fail_configure;
1066 /* Disable and free rte_meter entries */
1067 rc = nix_meter_fini(dev);
1069 goto fail_configure;
1071 /* Cleanup security support */
1072 rc = nix_security_release(dev);
1074 goto fail_configure;
1076 roc_nix_tm_fini(nix);
1077 roc_nix_lf_free(nix);
1080 dev->rx_offloads = rxmode->offloads;
1081 dev->tx_offloads = txmode->offloads;
1083 /* Prepare rx cfg */
1084 rx_cfg = ROC_NIX_LF_RX_CFG_DIS_APAD;
1085 if (dev->rx_offloads &
1086 (RTE_ETH_RX_OFFLOAD_TCP_CKSUM | RTE_ETH_RX_OFFLOAD_UDP_CKSUM)) {
1087 rx_cfg |= ROC_NIX_LF_RX_CFG_CSUM_OL4;
1088 rx_cfg |= ROC_NIX_LF_RX_CFG_CSUM_IL4;
1090 rx_cfg |= (ROC_NIX_LF_RX_CFG_DROP_RE | ROC_NIX_LF_RX_CFG_L2_LEN_ERR |
1091 ROC_NIX_LF_RX_CFG_LEN_IL4 | ROC_NIX_LF_RX_CFG_LEN_IL3 |
1092 ROC_NIX_LF_RX_CFG_LEN_OL4 | ROC_NIX_LF_RX_CFG_LEN_OL3);
1094 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
1095 rx_cfg |= ROC_NIX_LF_RX_CFG_IP6_UDP_OPT;
1096 /* Disable drop re if rx offload security is enabled and
1097 * platform does not support it.
1099 if (dev->ipsecd_drop_re_dis)
1100 rx_cfg &= ~(ROC_NIX_LF_RX_CFG_DROP_RE);
1103 nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1104 nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1106 /* Alloc a nix lf */
1107 rc = roc_nix_lf_alloc(nix, nb_rxq, nb_txq, rx_cfg);
1109 plt_err("Failed to init nix_lf rc=%d", rc);
1110 goto fail_configure;
1113 dev->npc.channel = roc_nix_get_base_chan(nix);
1115 nb_rxq = data->nb_rx_queues;
1116 nb_txq = data->nb_tx_queues;
1119 /* Allocate memory for roc rq's and cq's */
1120 qs = plt_zmalloc(sizeof(struct roc_nix_rq) * nb_rxq, 0);
1122 plt_err("Failed to alloc rqs");
1127 qs = plt_zmalloc(sizeof(struct roc_nix_cq) * nb_rxq, 0);
1129 plt_err("Failed to alloc cqs");
1136 /* Allocate memory for roc sq's */
1137 qs = plt_zmalloc(sizeof(struct roc_nix_sq) * nb_txq, 0);
1139 plt_err("Failed to alloc sqs");
1145 /* Re-enable NIX LF error interrupts */
1146 roc_nix_err_intr_ena_dis(nix, true);
1147 roc_nix_ras_intr_ena_dis(nix, true);
1149 if (nix->rx_ptp_ena &&
1150 dev->npc.switch_header_type == ROC_PRIV_FLAGS_HIGIG) {
1151 plt_err("Both PTP and switch header enabled");
1155 rc = roc_nix_switch_hdr_set(nix, dev->npc.switch_header_type,
1156 dev->npc.pre_l2_size_offset,
1157 dev->npc.pre_l2_size_offset_mask,
1158 dev->npc.pre_l2_size_shift_dir);
1160 plt_err("Failed to enable switch type nix_lf rc=%d", rc);
1164 /* Setup LSO if needed */
1165 rc = nix_lso_fmt_setup(dev);
1167 plt_err("Failed to setup nix lso format fields, rc=%d", rc);
1172 rc = nix_rss_default_setup(dev);
1174 plt_err("Failed to configure rss rc=%d", rc);
1178 /* Init the default TM scheduler hierarchy */
1179 rc = roc_nix_tm_init(nix);
1181 plt_err("Failed to init traffic manager, rc=%d", rc);
1185 rc = nix_ingress_policer_setup(dev);
1187 plt_err("Failed to setup ingress policer rc=%d", rc);
1191 rc = roc_nix_tm_hierarchy_enable(nix, ROC_NIX_TM_DEFAULT, false);
1193 plt_err("Failed to enable default tm hierarchy, rc=%d", rc);
1197 /* Register queue IRQs */
1198 rc = roc_nix_register_queue_irqs(nix);
1200 plt_err("Failed to register queue interrupts rc=%d", rc);
1204 /* Register cq IRQs */
1205 if (eth_dev->data->dev_conf.intr_conf.rxq) {
1206 if (eth_dev->data->nb_rx_queues > dev->nix.cints) {
1207 plt_err("Rx interrupt cannot be enabled, rxq > %d",
1211 /* Rx interrupt feature cannot work with vector mode because,
1212 * vector mode does not process packets unless min 4 pkts are
1213 * received, while cq interrupts are generated even for 1 pkt
1216 dev->scalar_ena = true;
1218 rc = roc_nix_register_cq_irqs(nix);
1220 plt_err("Failed to register CQ interrupts rc=%d", rc);
1225 /* Configure loop back mode */
1226 rc = roc_nix_mac_loopback_enable(nix,
1227 eth_dev->data->dev_conf.lpbk_mode);
1229 plt_err("Failed to configure cgx loop back mode rc=%d", rc);
1233 /* Setup Inline security support */
1234 rc = nix_security_setup(dev);
1238 /* Init flow control configuration */
1239 fc_cfg.type = ROC_NIX_FC_RXCHAN_CFG;
1240 fc_cfg.rxchan_cfg.enable = true;
1241 rc = roc_nix_fc_config_set(nix, &fc_cfg);
1243 plt_err("Failed to initialize flow control rc=%d", rc);
1247 /* Update flow control configuration to PMD */
1248 rc = nix_init_flow_ctrl_config(eth_dev);
1250 plt_err("Failed to initialize flow control rc=%d", rc);
1254 /* Initialize TC to SQ mapping as invalid */
1255 memset(dev->pfc_tc_sq_map, 0xFF, sizeof(dev->pfc_tc_sq_map));
1257 * Restore queue config when reconfigure followed by
1258 * reconfigure and no queue configure invoked from application case.
1260 if (dev->configured == 1) {
1261 rc = nix_restore_queue_cfg(eth_dev);
1266 /* Update the mac address */
1267 ea = eth_dev->data->mac_addrs;
1268 memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1269 if (rte_is_zero_ether_addr(ea))
1270 rte_eth_random_addr((uint8_t *)ea);
1272 rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
1274 plt_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
1275 " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 "",
1276 eth_dev->data->port_id, ea_fmt, nb_rxq, nb_txq,
1277 dev->rx_offloads, dev->tx_offloads);
1280 dev->configured = 1;
1281 dev->nb_rxq = data->nb_rx_queues;
1282 dev->nb_txq = data->nb_tx_queues;
1286 rc |= nix_security_release(dev);
1288 roc_nix_unregister_cq_irqs(nix);
1290 roc_nix_unregister_queue_irqs(nix);
1292 roc_nix_tm_fini(nix);
1294 nix_free_queue_mem(dev);
1295 rc |= roc_nix_lf_free(nix);
1297 dev->configured = 0;
1302 cnxk_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid)
1304 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1305 struct rte_eth_dev_data *data = eth_dev->data;
1306 struct roc_nix_sq *sq = &dev->sqs[qid];
1309 if (data->tx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STARTED)
1312 rc = roc_nix_tm_sq_aura_fc(sq, true);
1314 plt_err("Failed to enable sq aura fc, txq=%u, rc=%d", qid, rc);
1318 data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STARTED;
1324 cnxk_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid)
1326 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1327 struct rte_eth_dev_data *data = eth_dev->data;
1328 struct roc_nix_sq *sq = &dev->sqs[qid];
1331 if (data->tx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STOPPED)
1334 rc = roc_nix_tm_sq_aura_fc(sq, false);
1336 plt_err("Failed to disable sqb aura fc, txq=%u, rc=%d", qid,
1341 data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
1347 cnxk_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid)
1349 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1350 struct rte_eth_dev_data *data = eth_dev->data;
1351 struct roc_nix_rq *rq = &dev->rqs[qid];
1354 if (data->rx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STARTED)
1357 rc = roc_nix_rq_ena_dis(rq, true);
1359 plt_err("Failed to enable rxq=%u, rc=%d", qid, rc);
1363 data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STARTED;
1369 cnxk_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid)
1371 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1372 struct rte_eth_dev_data *data = eth_dev->data;
1373 struct roc_nix_rq *rq = &dev->rqs[qid];
1376 if (data->rx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STOPPED)
1379 rc = roc_nix_rq_ena_dis(rq, false);
1381 plt_err("Failed to disable rxq=%u, rc=%d", qid, rc);
1385 data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
1391 cnxk_nix_dev_stop(struct rte_eth_dev *eth_dev)
1393 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1394 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
1395 struct rte_mbuf *rx_pkts[32];
1396 struct rte_eth_link link;
1397 int count, i, j, rc;
1400 /* Disable all the NPC entries */
1401 rc = roc_npc_mcam_enable_all_entries(&dev->npc, 0);
1405 /* Stop link change events */
1406 if (!roc_nix_is_vf_or_sdp(&dev->nix))
1407 roc_nix_mac_link_event_start_stop(&dev->nix, false);
1409 /* Disable Rx via NPC */
1410 roc_nix_npc_rx_ena_dis(&dev->nix, false);
1412 /* Stop rx queues and free up pkts pending */
1413 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1414 rc = dev_ops->rx_queue_stop(eth_dev, i);
1418 rxq = eth_dev->data->rx_queues[i];
1419 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1421 for (j = 0; j < count; j++)
1422 rte_pktmbuf_free(rx_pkts[j]);
1423 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1427 /* Stop tx queues */
1428 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1429 dev_ops->tx_queue_stop(eth_dev, i);
1431 /* Bring down link status internally */
1432 memset(&link, 0, sizeof(link));
1433 rte_eth_linkstatus_set(eth_dev, &link);
1439 cnxk_nix_dev_start(struct rte_eth_dev *eth_dev)
1441 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1444 if (eth_dev->data->nb_rx_queues != 0 && !dev->ptp_en) {
1445 rc = nix_recalc_mtu(eth_dev);
1450 /* Start rx queues */
1451 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1452 rc = cnxk_nix_rx_queue_start(eth_dev, i);
1457 /* Start tx queues */
1458 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1459 rc = cnxk_nix_tx_queue_start(eth_dev, i);
1464 /* Update Flow control configuration */
1465 rc = nix_update_flow_ctrl_config(eth_dev);
1467 plt_err("Failed to enable flow control. error code(%d)", rc);
1471 /* Enable Rx in NPC */
1472 rc = roc_nix_npc_rx_ena_dis(&dev->nix, true);
1474 plt_err("Failed to enable NPC rx %d", rc);
1478 rc = roc_npc_mcam_enable_all_entries(&dev->npc, 1);
1480 plt_err("Failed to enable NPC entries %d", rc);
1484 cnxk_nix_toggle_flag_link_cfg(dev, true);
1486 /* Start link change events */
1487 if (!roc_nix_is_vf_or_sdp(&dev->nix)) {
1488 rc = roc_nix_mac_link_event_start_stop(&dev->nix, true);
1490 plt_err("Failed to start cgx link event %d", rc);
1495 /* Enable PTP if it is requested by the user or already
1496 * enabled on PF owning this VF
1498 memset(&dev->tstamp, 0, sizeof(struct cnxk_timesync_info));
1499 if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) || dev->ptp_en)
1500 cnxk_eth_dev_ops.timesync_enable(eth_dev);
1502 cnxk_eth_dev_ops.timesync_disable(eth_dev);
1504 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
1505 rc = rte_mbuf_dyn_rx_timestamp_register
1506 (&dev->tstamp.tstamp_dynfield_offset,
1507 &dev->tstamp.rx_tstamp_dynflag);
1509 plt_err("Failed to register Rx timestamp field/flag");
1514 cnxk_nix_toggle_flag_link_cfg(dev, false);
1519 roc_nix_npc_rx_ena_dis(&dev->nix, false);
1520 cnxk_nix_toggle_flag_link_cfg(dev, false);
1524 static int cnxk_nix_dev_reset(struct rte_eth_dev *eth_dev);
1525 static int cnxk_nix_dev_close(struct rte_eth_dev *eth_dev);
1527 /* CNXK platform independent eth dev ops */
1528 struct eth_dev_ops cnxk_eth_dev_ops = {
1529 .mtu_set = cnxk_nix_mtu_set,
1530 .mac_addr_add = cnxk_nix_mac_addr_add,
1531 .mac_addr_remove = cnxk_nix_mac_addr_del,
1532 .mac_addr_set = cnxk_nix_mac_addr_set,
1533 .dev_infos_get = cnxk_nix_info_get,
1534 .link_update = cnxk_nix_link_update,
1535 .tx_queue_release = cnxk_nix_tx_queue_release,
1536 .rx_queue_release = cnxk_nix_rx_queue_release,
1537 .dev_stop = cnxk_nix_dev_stop,
1538 .dev_close = cnxk_nix_dev_close,
1539 .dev_reset = cnxk_nix_dev_reset,
1540 .tx_queue_start = cnxk_nix_tx_queue_start,
1541 .rx_queue_start = cnxk_nix_rx_queue_start,
1542 .rx_queue_stop = cnxk_nix_rx_queue_stop,
1543 .dev_supported_ptypes_get = cnxk_nix_supported_ptypes_get,
1544 .promiscuous_enable = cnxk_nix_promisc_enable,
1545 .promiscuous_disable = cnxk_nix_promisc_disable,
1546 .allmulticast_enable = cnxk_nix_allmulticast_enable,
1547 .allmulticast_disable = cnxk_nix_allmulticast_disable,
1548 .rx_burst_mode_get = cnxk_nix_rx_burst_mode_get,
1549 .tx_burst_mode_get = cnxk_nix_tx_burst_mode_get,
1550 .flow_ctrl_get = cnxk_nix_flow_ctrl_get,
1551 .flow_ctrl_set = cnxk_nix_flow_ctrl_set,
1552 .priority_flow_ctrl_queue_config =
1553 cnxk_nix_priority_flow_ctrl_queue_config,
1554 .priority_flow_ctrl_queue_info_get =
1555 cnxk_nix_priority_flow_ctrl_queue_info_get,
1556 .dev_set_link_up = cnxk_nix_set_link_up,
1557 .dev_set_link_down = cnxk_nix_set_link_down,
1558 .get_module_info = cnxk_nix_get_module_info,
1559 .get_module_eeprom = cnxk_nix_get_module_eeprom,
1560 .rx_queue_intr_enable = cnxk_nix_rx_queue_intr_enable,
1561 .rx_queue_intr_disable = cnxk_nix_rx_queue_intr_disable,
1562 .pool_ops_supported = cnxk_nix_pool_ops_supported,
1563 .queue_stats_mapping_set = cnxk_nix_queue_stats_mapping,
1564 .stats_get = cnxk_nix_stats_get,
1565 .stats_reset = cnxk_nix_stats_reset,
1566 .xstats_get = cnxk_nix_xstats_get,
1567 .xstats_get_names = cnxk_nix_xstats_get_names,
1568 .xstats_reset = cnxk_nix_xstats_reset,
1569 .xstats_get_by_id = cnxk_nix_xstats_get_by_id,
1570 .xstats_get_names_by_id = cnxk_nix_xstats_get_names_by_id,
1571 .fw_version_get = cnxk_nix_fw_version_get,
1572 .rxq_info_get = cnxk_nix_rxq_info_get,
1573 .txq_info_get = cnxk_nix_txq_info_get,
1574 .tx_done_cleanup = cnxk_nix_tx_done_cleanup,
1575 .flow_ops_get = cnxk_nix_flow_ops_get,
1576 .get_reg = cnxk_nix_dev_get_reg,
1577 .timesync_read_rx_timestamp = cnxk_nix_timesync_read_rx_timestamp,
1578 .timesync_read_tx_timestamp = cnxk_nix_timesync_read_tx_timestamp,
1579 .timesync_read_time = cnxk_nix_timesync_read_time,
1580 .timesync_write_time = cnxk_nix_timesync_write_time,
1581 .timesync_adjust_time = cnxk_nix_timesync_adjust_time,
1582 .read_clock = cnxk_nix_read_clock,
1583 .reta_update = cnxk_nix_reta_update,
1584 .reta_query = cnxk_nix_reta_query,
1585 .rss_hash_update = cnxk_nix_rss_hash_update,
1586 .rss_hash_conf_get = cnxk_nix_rss_hash_conf_get,
1587 .set_mc_addr_list = cnxk_nix_mc_addr_list_configure,
1588 .set_queue_rate_limit = cnxk_nix_tm_set_queue_rate_limit,
1589 .tm_ops_get = cnxk_nix_tm_ops_get,
1590 .mtr_ops_get = cnxk_nix_mtr_ops_get,
1594 cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)
1596 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1597 struct rte_security_ctx *sec_ctx;
1598 struct roc_nix *nix = &dev->nix;
1599 struct rte_pci_device *pci_dev;
1600 int rc, max_entries;
1602 eth_dev->dev_ops = &cnxk_eth_dev_ops;
1603 eth_dev->rx_queue_count = cnxk_nix_rx_queue_count;
1604 eth_dev->rx_descriptor_status = cnxk_nix_rx_descriptor_status;
1605 eth_dev->tx_descriptor_status = cnxk_nix_tx_descriptor_status;
1607 /* Alloc security context */
1608 sec_ctx = plt_zmalloc(sizeof(struct rte_security_ctx), 0);
1611 sec_ctx->device = eth_dev;
1612 sec_ctx->ops = &cnxk_eth_sec_ops;
1614 (RTE_SEC_CTX_F_FAST_SET_MDATA | RTE_SEC_CTX_F_FAST_GET_UDATA);
1615 eth_dev->security_ctx = sec_ctx;
1617 /* For secondary processes, the primary has done all the work */
1618 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1621 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1622 rte_eth_copy_pci_info(eth_dev, pci_dev);
1624 /* Parse devargs string */
1625 rc = cnxk_ethdev_parse_devargs(eth_dev->device->devargs, dev);
1627 plt_err("Failed to parse devargs rc=%d", rc);
1631 /* Initialize base roc nix */
1632 nix->pci_dev = pci_dev;
1633 nix->hw_vlan_ins = true;
1634 rc = roc_nix_dev_init(nix);
1636 plt_err("Failed to initialize roc nix rc=%d", rc);
1640 /* Register up msg callbacks */
1641 roc_nix_mac_link_cb_register(nix, cnxk_eth_dev_link_status_cb);
1643 /* Register up msg callbacks */
1644 roc_nix_mac_link_info_get_cb_register(nix,
1645 cnxk_eth_dev_link_status_get_cb);
1647 dev->eth_dev = eth_dev;
1648 dev->configured = 0;
1649 dev->ptype_disable = 0;
1651 TAILQ_INIT(&dev->inb.list);
1652 TAILQ_INIT(&dev->outb.list);
1653 rte_spinlock_init(&dev->inb.lock);
1654 rte_spinlock_init(&dev->outb.lock);
1656 /* For vfs, returned max_entries will be 0. but to keep default mac
1657 * address, one entry must be allocated. so setting up to 1.
1659 if (roc_nix_is_vf_or_sdp(nix))
1662 max_entries = roc_nix_mac_max_entries_get(nix);
1664 if (max_entries <= 0) {
1665 plt_err("Failed to get max entries for mac addr");
1670 eth_dev->data->mac_addrs =
1671 rte_zmalloc("mac_addr", max_entries * RTE_ETHER_ADDR_LEN, 0);
1672 if (eth_dev->data->mac_addrs == NULL) {
1673 plt_err("Failed to allocate memory for mac addr");
1678 dev->max_mac_entries = max_entries;
1679 dev->dmac_filter_count = 1;
1681 /* Get mac address */
1682 rc = roc_nix_npc_mac_addr_get(nix, dev->mac_addr);
1684 plt_err("Failed to get mac addr, rc=%d", rc);
1685 goto free_mac_addrs;
1688 /* Update the mac address */
1689 memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1691 if (!roc_nix_is_vf_or_sdp(nix)) {
1692 /* Sync same MAC address to CGX/RPM table */
1693 rc = roc_nix_mac_addr_set(nix, dev->mac_addr);
1695 plt_err("Failed to set mac addr, rc=%d", rc);
1696 goto free_mac_addrs;
1700 /* Union of all capabilities supported by CNXK.
1701 * Platform specific capabilities will be
1704 dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
1705 dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
1706 dev->speed_capa = nix_get_speed_capa(dev);
1708 /* Initialize roc npc */
1709 dev->npc.roc_nix = nix;
1710 rc = roc_npc_init(&dev->npc);
1712 goto free_mac_addrs;
1714 plt_nix_dbg("Port=%d pf=%d vf=%d ver=%s hwcap=0x%" PRIx64
1715 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
1716 eth_dev->data->port_id, roc_nix_get_pf(nix),
1717 roc_nix_get_vf(nix), CNXK_ETH_DEV_PMD_VERSION, dev->hwcap,
1718 dev->rx_offload_capa, dev->tx_offload_capa);
1722 rte_free(eth_dev->data->mac_addrs);
1724 roc_nix_dev_fini(nix);
1726 plt_err("Failed to init nix eth_dev rc=%d", rc);
1731 cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool reset)
1733 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1734 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
1735 struct rte_eth_pfc_queue_conf pfc_conf;
1736 struct roc_nix *nix = &dev->nix;
1737 struct rte_eth_fc_conf fc_conf;
1740 /* Disable switch hdr pkind */
1741 roc_nix_switch_hdr_set(&dev->nix, 0, 0, 0, 0);
1743 plt_free(eth_dev->security_ctx);
1744 eth_dev->security_ctx = NULL;
1746 /* Nothing to be done for secondary processes */
1747 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1750 /* Clear the flag since we are closing down */
1751 dev->configured = 0;
1753 roc_nix_npc_rx_ena_dis(nix, false);
1755 /* Restore 802.3 Flow control configuration */
1756 memset(&pfc_conf, 0, sizeof(struct rte_eth_pfc_queue_conf));
1757 memset(&fc_conf, 0, sizeof(struct rte_eth_fc_conf));
1758 fc_conf.mode = RTE_ETH_FC_NONE;
1759 rc = cnxk_nix_flow_ctrl_set(eth_dev, &fc_conf);
1761 pfc_conf.mode = RTE_ETH_FC_NONE;
1762 for (i = 0; i < CNXK_NIX_PFC_CHAN_COUNT; i++) {
1763 if (dev->pfc_tc_sq_map[i] != 0xFFFF) {
1764 pfc_conf.rx_pause.tx_qid = dev->pfc_tc_sq_map[i];
1765 pfc_conf.rx_pause.tc = i;
1766 pfc_conf.tx_pause.rx_qid = i;
1767 pfc_conf.tx_pause.tc = i;
1768 rc = cnxk_nix_priority_flow_ctrl_queue_config(eth_dev,
1771 plt_err("Failed to reset PFC. error code(%d)",
1776 fc_conf.mode = RTE_ETH_FC_FULL;
1777 rc = cnxk_nix_flow_ctrl_set(eth_dev, &fc_conf);
1779 /* Disable and free rte_meter entries */
1780 nix_meter_fini(dev);
1782 /* Disable and free rte_flow entries */
1783 roc_npc_fini(&dev->npc);
1785 /* Disable link status events */
1786 roc_nix_mac_link_event_start_stop(nix, false);
1788 /* Unregister the link update op, this is required to stop VFs from
1789 * receiving link status updates on exit path.
1791 roc_nix_mac_link_cb_unregister(nix);
1794 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1795 dev_ops->tx_queue_release(eth_dev, i);
1796 eth_dev->data->tx_queues[i] = NULL;
1798 eth_dev->data->nb_tx_queues = 0;
1800 /* Free up RQ's and CQ's */
1801 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1802 dev_ops->rx_queue_release(eth_dev, i);
1803 eth_dev->data->rx_queues[i] = NULL;
1805 eth_dev->data->nb_rx_queues = 0;
1807 /* Free security resources */
1808 nix_security_release(dev);
1810 /* Free tm resources */
1811 roc_nix_tm_fini(nix);
1813 /* Unregister queue irqs */
1814 roc_nix_unregister_queue_irqs(nix);
1816 /* Unregister cq irqs */
1817 if (eth_dev->data->dev_conf.intr_conf.rxq)
1818 roc_nix_unregister_cq_irqs(nix);
1820 /* Free ROC RQ's, SQ's and CQ's memory */
1821 nix_free_queue_mem(dev);
1823 /* Free nix lf resources */
1824 rc = roc_nix_lf_free(nix);
1826 plt_err("Failed to free nix lf, rc=%d", rc);
1828 rte_free(eth_dev->data->mac_addrs);
1829 eth_dev->data->mac_addrs = NULL;
1831 rc = roc_nix_dev_fini(nix);
1832 /* Can be freed later by PMD if NPA LF is in use */
1833 if (rc == -EAGAIN) {
1835 eth_dev->data->dev_private = NULL;
1838 plt_err("Failed in nix dev fini, rc=%d", rc);
1845 cnxk_nix_dev_close(struct rte_eth_dev *eth_dev)
1847 cnxk_eth_dev_uninit(eth_dev, false);
1852 cnxk_nix_dev_reset(struct rte_eth_dev *eth_dev)
1856 rc = cnxk_eth_dev_uninit(eth_dev, true);
1860 return cnxk_eth_dev_init(eth_dev);
1864 cnxk_nix_remove(struct rte_pci_device *pci_dev)
1866 struct rte_eth_dev *eth_dev;
1867 struct roc_nix *nix;
1870 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
1872 /* Cleanup eth dev */
1873 rc = cnxk_eth_dev_uninit(eth_dev, false);
1877 rte_eth_dev_release_port(eth_dev);
1880 /* Nothing to be done for secondary processes */
1881 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1884 /* Check if this device is hosting common resource */
1885 nix = roc_idev_npa_nix_get();
1886 if (nix->pci_dev != pci_dev)
1889 /* Try nix fini now */
1890 rc = roc_nix_dev_fini(nix);
1891 if (rc == -EAGAIN) {
1892 plt_info("%s: common resource in use by other devices",
1896 plt_err("Failed in nix dev fini, rc=%d", rc);
1900 /* Free device pointer as rte_ethdev does not have it anymore */
1907 cnxk_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1911 RTE_SET_USED(pci_drv);
1913 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct cnxk_eth_dev),
1916 /* On error on secondary, recheck if port exists in primary or
1917 * in mid of detach state.
1919 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
1920 if (!rte_eth_dev_allocated(pci_dev->device.name))