drivers/net/cnxk/cnxk_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4 #include <cnxk_ethdev.h>
   5
   6 static inline uint64_t
   7 nix_get_rx_offload_capa(struct cnxk_eth_dev *dev)
   8 {
   9         uint64_t capa = CNXK_NIX_RX_OFFLOAD_CAPA;
  10
  11         if (roc_nix_is_vf_or_sdp(&dev->nix) ||
  12             dev->npc.switch_header_type == ROC_PRIV_FLAGS_HIGIG)
  13                 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
  14
  15         return capa;
  16 }
  17
  18 static inline uint64_t
  19 nix_get_tx_offload_capa(struct cnxk_eth_dev *dev)
  20 {
  21         RTE_SET_USED(dev);
  22         return CNXK_NIX_TX_OFFLOAD_CAPA;
  23 }
  24
  25 static inline uint32_t
  26 nix_get_speed_capa(struct cnxk_eth_dev *dev)
  27 {
  28         uint32_t speed_capa;
  29
  30         /* Auto negotiation disabled */
  31         speed_capa = ETH_LINK_SPEED_FIXED;
  32         if (!roc_nix_is_vf_or_sdp(&dev->nix) && !roc_nix_is_lbk(&dev->nix)) {
  33                 speed_capa |= ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
  34                               ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
  35                               ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
  36         }
  37
  38         return speed_capa;
  39 }
  40
  41 int
  42 cnxk_nix_inb_mode_set(struct cnxk_eth_dev *dev, bool use_inl_dev)
  43 {
  44         struct roc_nix *nix = &dev->nix;
  45
  46         if (dev->inb.inl_dev == use_inl_dev)
  47                 return 0;
  48
  49         plt_nix_dbg("Security sessions(%u) still active, inl=%u!!!",
  50                     dev->inb.nb_sess, !!dev->inb.inl_dev);
  51
  52         /* Change the mode */
  53         dev->inb.inl_dev = use_inl_dev;
  54
  55         /* Update RoC for NPC rule insertion */
  56         roc_nix_inb_mode_set(nix, use_inl_dev);
  57
  58         /* Setup lookup mem */
  59         return cnxk_nix_lookup_mem_sa_base_set(dev);
  60 }
  61
  62 static int
  63 nix_security_setup(struct cnxk_eth_dev *dev)
  64 {
  65         struct roc_nix *nix = &dev->nix;
  66         int i, rc = 0;
  67
  68         if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
  69                 /* Setup Inline Inbound */
  70                 rc = roc_nix_inl_inb_init(nix);
  71                 if (rc) {
  72                         plt_err("Failed to initialize nix inline inb, rc=%d",
  73                                 rc);
  74                         return rc;
  75                 }
  76
  77                 /* By default pick using inline device for poll mode.
  78                  * Will be overridden when event mode rq's are setup.
  79                  */
  80                 cnxk_nix_inb_mode_set(dev, true);
  81         }
  82
  83         if (dev->tx_offloads & DEV_TX_OFFLOAD_SECURITY ||
  84             dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
  85                 struct plt_bitmap *bmap;
  86                 size_t bmap_sz;
  87                 void *mem;
  88
  89                 /* Setup enough descriptors for all tx queues */
  90                 nix->outb_nb_desc = dev->outb.nb_desc;
  91                 nix->outb_nb_crypto_qs = dev->outb.nb_crypto_qs;
  92
  93                 /* Setup Inline Outbound */
  94                 rc = roc_nix_inl_outb_init(nix);
  95                 if (rc) {
  96                         plt_err("Failed to initialize nix inline outb, rc=%d",
  97                                 rc);
  98                         goto cleanup;
  99                 }
 100
 101                 dev->outb.lf_base = roc_nix_inl_outb_lf_base_get(nix);
 102
 103                 /* Skip the rest if DEV_TX_OFFLOAD_SECURITY is not enabled */
 104                 if (!(dev->tx_offloads & DEV_TX_OFFLOAD_SECURITY))
 105                         goto done;
 106
 107                 rc = -ENOMEM;
 108                 /* Allocate a bitmap to alloc and free sa indexes */
 109                 bmap_sz = plt_bitmap_get_memory_footprint(dev->outb.max_sa);
 110                 mem = plt_zmalloc(bmap_sz, PLT_CACHE_LINE_SIZE);
 111                 if (mem == NULL) {
 112                         plt_err("Outbound SA bmap alloc failed");
 113
 114                         rc |= roc_nix_inl_outb_fini(nix);
 115                         goto cleanup;
 116                 }
 117
 118                 rc = -EIO;
 119                 bmap = plt_bitmap_init(dev->outb.max_sa, mem, bmap_sz);
 120                 if (!bmap) {
 121                         plt_err("Outbound SA bmap init failed");
 122
 123                         rc |= roc_nix_inl_outb_fini(nix);
 124                         plt_free(mem);
 125                         goto cleanup;
 126                 }
 127
 128                 for (i = 0; i < dev->outb.max_sa; i++)
 129                         plt_bitmap_set(bmap, i);
 130
 131                 dev->outb.sa_base = roc_nix_inl_outb_sa_base_get(nix);
 132                 dev->outb.sa_bmap_mem = mem;
 133                 dev->outb.sa_bmap = bmap;
 134         }
 135
 136 done:
 137         return 0;
 138 cleanup:
 139         if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY)
 140                 rc |= roc_nix_inl_inb_fini(nix);
 141         return rc;
 142 }
 143
 144 static int
 145 nix_security_release(struct cnxk_eth_dev *dev)
 146 {
 147         struct rte_eth_dev *eth_dev = dev->eth_dev;
 148         struct cnxk_eth_sec_sess *eth_sec, *tvar;
 149         struct roc_nix *nix = &dev->nix;
 150         int rc, ret = 0;
 151
 152         /* Cleanup Inline inbound */
 153         if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
 154                 /* Destroy inbound sessions */
 155                 tvar = NULL;
 156                 RTE_TAILQ_FOREACH_SAFE(eth_sec, &dev->inb.list, entry, tvar)
 157                         cnxk_eth_sec_ops.session_destroy(eth_dev,
 158                                                          eth_sec->sess);
 159
 160                 /* Clear lookup mem */
 161                 cnxk_nix_lookup_mem_sa_base_clear(dev);
 162
 163                 rc = roc_nix_inl_inb_fini(nix);
 164                 if (rc)
 165                         plt_err("Failed to cleanup nix inline inb, rc=%d", rc);
 166                 ret |= rc;
 167         }
 168
 169         /* Cleanup Inline outbound */
 170         if (dev->tx_offloads & DEV_TX_OFFLOAD_SECURITY ||
 171             dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
 172                 /* Destroy outbound sessions */
 173                 tvar = NULL;
 174                 RTE_TAILQ_FOREACH_SAFE(eth_sec, &dev->outb.list, entry, tvar)
 175                         cnxk_eth_sec_ops.session_destroy(eth_dev,
 176                                                          eth_sec->sess);
 177
 178                 rc = roc_nix_inl_outb_fini(nix);
 179                 if (rc)
 180                         plt_err("Failed to cleanup nix inline outb, rc=%d", rc);
 181                 ret |= rc;
 182
 183                 plt_bitmap_free(dev->outb.sa_bmap);
 184                 plt_free(dev->outb.sa_bmap_mem);
 185                 dev->outb.sa_bmap = NULL;
 186                 dev->outb.sa_bmap_mem = NULL;
 187         }
 188
 189         dev->inb.inl_dev = false;
 190         roc_nix_inb_mode_set(nix, false);
 191         dev->nb_rxq_sso = 0;
 192         dev->inb.nb_sess = 0;
 193         dev->outb.nb_sess = 0;
 194         return ret;
 195 }
 196
 197 static void
 198 nix_enable_mseg_on_jumbo(struct cnxk_eth_rxq_sp *rxq)
 199 {
 200         struct rte_pktmbuf_pool_private *mbp_priv;
 201         struct rte_eth_dev *eth_dev;
 202         struct cnxk_eth_dev *dev;
 203         uint32_t buffsz;
 204
 205         dev = rxq->dev;
 206         eth_dev = dev->eth_dev;
 207
 208         /* Get rx buffer size */
 209         mbp_priv = rte_mempool_get_priv(rxq->qconf.mp);
 210         buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
 211
 212         if (eth_dev->data->mtu + (uint32_t)CNXK_NIX_L2_OVERHEAD > buffsz) {
 213                 dev->rx_offloads |= DEV_RX_OFFLOAD_SCATTER;
 214                 dev->tx_offloads |= DEV_TX_OFFLOAD_MULTI_SEGS;
 215         }
 216 }
 217
 218 int
 219 nix_recalc_mtu(struct rte_eth_dev *eth_dev)
 220 {
 221         struct rte_eth_dev_data *data = eth_dev->data;
 222         struct cnxk_eth_rxq_sp *rxq;
 223         int rc;
 224
 225         rxq = ((struct cnxk_eth_rxq_sp *)data->rx_queues[0]) - 1;
 226         /* Setup scatter mode if needed by jumbo */
 227         nix_enable_mseg_on_jumbo(rxq);
 228
 229         rc = cnxk_nix_mtu_set(eth_dev, data->mtu);
 230         if (rc)
 231                 plt_err("Failed to set default MTU size, rc=%d", rc);
 232
 233         return rc;
 234 }
 235
 236 static int
 237 nix_init_flow_ctrl_config(struct rte_eth_dev *eth_dev)
 238 {
 239         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 240         struct cnxk_fc_cfg *fc = &dev->fc_cfg;
 241         struct rte_eth_fc_conf fc_conf = {0};
 242         int rc;
 243
 244         /* Both Rx & Tx flow ctrl get enabled(RTE_FC_FULL) in HW
 245          * by AF driver, update those info in PMD structure.
 246          */
 247         rc = cnxk_nix_flow_ctrl_get(eth_dev, &fc_conf);
 248         if (rc)
 249                 goto exit;
 250
 251         fc->mode = fc_conf.mode;
 252         fc->rx_pause = (fc_conf.mode == RTE_FC_FULL) ||
 253                         (fc_conf.mode == RTE_FC_RX_PAUSE);
 254         fc->tx_pause = (fc_conf.mode == RTE_FC_FULL) ||
 255                         (fc_conf.mode == RTE_FC_TX_PAUSE);
 256
 257 exit:
 258         return rc;
 259 }
 260
 261 static int
 262 nix_update_flow_ctrl_config(struct rte_eth_dev *eth_dev)
 263 {
 264         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 265         struct cnxk_fc_cfg *fc = &dev->fc_cfg;
 266         struct rte_eth_fc_conf fc_cfg = {0};
 267
 268         if (roc_nix_is_vf_or_sdp(&dev->nix))
 269                 return 0;
 270
 271         fc_cfg.mode = fc->mode;
 272
 273         /* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */
 274         if (roc_model_is_cn96_ax() &&
 275             dev->npc.switch_header_type != ROC_PRIV_FLAGS_HIGIG &&
 276             (fc_cfg.mode == RTE_FC_FULL || fc_cfg.mode == RTE_FC_RX_PAUSE)) {
 277                 fc_cfg.mode =
 278                                 (fc_cfg.mode == RTE_FC_FULL ||
 279                                 fc_cfg.mode == RTE_FC_TX_PAUSE) ?
 280                                 RTE_FC_TX_PAUSE : RTE_FC_NONE;
 281         }
 282
 283         return cnxk_nix_flow_ctrl_set(eth_dev, &fc_cfg);
 284 }
 285
 286 uint64_t
 287 cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev)
 288 {
 289         uint16_t port_id = dev->eth_dev->data->port_id;
 290         struct rte_mbuf mb_def;
 291         uint64_t *tmp;
 292
 293         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
 294         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
 295                                  offsetof(struct rte_mbuf, data_off) !=
 296                          2);
 297         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
 298                                  offsetof(struct rte_mbuf, data_off) !=
 299                          4);
 300         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
 301                                  offsetof(struct rte_mbuf, data_off) !=
 302                          6);
 303         mb_def.nb_segs = 1;
 304         mb_def.data_off = RTE_PKTMBUF_HEADROOM +
 305                           (dev->ptp_en * CNXK_NIX_TIMESYNC_RX_OFFSET);
 306         mb_def.port = port_id;
 307         rte_mbuf_refcnt_set(&mb_def, 1);
 308
 309         /* Prevent compiler reordering: rearm_data covers previous fields */
 310         rte_compiler_barrier();
 311         tmp = (uint64_t *)&mb_def.rearm_data;
 312
 313         return *tmp;
 314 }
 315
 316 static inline uint8_t
 317 nix_sq_max_sqe_sz(struct cnxk_eth_dev *dev)
 318 {
 319         /*
 320          * Maximum three segments can be supported with W8, Choose
 321          * NIX_MAXSQESZ_W16 for multi segment offload.
 322          */
 323         if (dev->tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
 324                 return NIX_MAXSQESZ_W16;
 325         else
 326                 return NIX_MAXSQESZ_W8;
 327 }
 328
 329 int
 330 cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 331                         uint16_t nb_desc, uint16_t fp_tx_q_sz,
 332                         const struct rte_eth_txconf *tx_conf)
 333 {
 334         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 335         const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
 336         struct cnxk_eth_txq_sp *txq_sp;
 337         struct roc_nix_sq *sq;
 338         size_t txq_sz;
 339         int rc;
 340
 341         /* Free memory prior to re-allocation if needed. */
 342         if (eth_dev->data->tx_queues[qid] != NULL) {
 343                 plt_nix_dbg("Freeing memory prior to re-allocation %d", qid);
 344                 dev_ops->tx_queue_release(eth_dev, qid);
 345                 eth_dev->data->tx_queues[qid] = NULL;
 346         }
 347
 348         /* When Tx Security offload is enabled, increase tx desc count by
 349          * max possible outbound desc count.
 350          */
 351         if (dev->tx_offloads & DEV_TX_OFFLOAD_SECURITY)
 352                 nb_desc += dev->outb.nb_desc;
 353
 354         /* Setup ROC SQ */
 355         sq = &dev->sqs[qid];
 356         sq->qid = qid;
 357         sq->nb_desc = nb_desc;
 358         sq->max_sqe_sz = nix_sq_max_sqe_sz(dev);
 359
 360         rc = roc_nix_sq_init(&dev->nix, sq);
 361         if (rc) {
 362                 plt_err("Failed to init sq=%d, rc=%d", qid, rc);
 363                 return rc;
 364         }
 365
 366         rc = -ENOMEM;
 367         txq_sz = sizeof(struct cnxk_eth_txq_sp) + fp_tx_q_sz;
 368         txq_sp = plt_zmalloc(txq_sz, PLT_CACHE_LINE_SIZE);
 369         if (!txq_sp) {
 370                 plt_err("Failed to alloc tx queue mem");
 371                 rc |= roc_nix_sq_fini(sq);
 372                 return rc;
 373         }
 374
 375         txq_sp->dev = dev;
 376         txq_sp->qid = qid;
 377         txq_sp->qconf.conf.tx = *tx_conf;
 378         /* Queue config should reflect global offloads */
 379         txq_sp->qconf.conf.tx.offloads = dev->tx_offloads;
 380         txq_sp->qconf.nb_desc = nb_desc;
 381
 382         plt_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " lmt_addr=%p"
 383                     " nb_sqb_bufs=%d sqes_per_sqb_log2=%d",
 384                     qid, sq->fc, dev->tx_offloads, sq->lmt_addr,
 385                     sq->nb_sqb_bufs, sq->sqes_per_sqb_log2);
 386
 387         /* Store start of fast path area */
 388         eth_dev->data->tx_queues[qid] = txq_sp + 1;
 389         eth_dev->data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
 390         return 0;
 391 }
 392
 393 static void
 394 cnxk_nix_tx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)
 395 {
 396         void *txq = eth_dev->data->tx_queues[qid];
 397         struct cnxk_eth_txq_sp *txq_sp;
 398         struct cnxk_eth_dev *dev;
 399         struct roc_nix_sq *sq;
 400         int rc;
 401
 402         if (!txq)
 403                 return;
 404
 405         txq_sp = cnxk_eth_txq_to_sp(txq);
 406
 407         dev = txq_sp->dev;
 408
 409         plt_nix_dbg("Releasing txq %u", qid);
 410
 411         /* Cleanup ROC SQ */
 412         sq = &dev->sqs[qid];
 413         rc = roc_nix_sq_fini(sq);
 414         if (rc)
 415                 plt_err("Failed to cleanup sq, rc=%d", rc);
 416
 417         /* Finally free */
 418         plt_free(txq_sp);
 419 }
 420
 421 int
 422 cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 423                         uint16_t nb_desc, uint16_t fp_rx_q_sz,
 424                         const struct rte_eth_rxconf *rx_conf,
 425                         struct rte_mempool *mp)
 426 {
 427         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 428         struct roc_nix *nix = &dev->nix;
 429         struct cnxk_eth_rxq_sp *rxq_sp;
 430         struct rte_mempool_ops *ops;
 431         const char *platform_ops;
 432         struct roc_nix_rq *rq;
 433         struct roc_nix_cq *cq;
 434         uint16_t first_skip;
 435         int rc = -EINVAL;
 436         size_t rxq_sz;
 437
 438         /* Sanity checks */
 439         if (rx_conf->rx_deferred_start == 1) {
 440                 plt_err("Deferred Rx start is not supported");
 441                 goto fail;
 442         }
 443
 444         platform_ops = rte_mbuf_platform_mempool_ops();
 445         /* This driver needs cnxk_npa mempool ops to work */
 446         ops = rte_mempool_get_ops(mp->ops_index);
 447         if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
 448                 plt_err("mempool ops should be of cnxk_npa type");
 449                 goto fail;
 450         }
 451
 452         if (mp->pool_id == 0) {
 453                 plt_err("Invalid pool_id");
 454                 goto fail;
 455         }
 456
 457         /* Free memory prior to re-allocation if needed */
 458         if (eth_dev->data->rx_queues[qid] != NULL) {
 459                 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
 460
 461                 plt_nix_dbg("Freeing memory prior to re-allocation %d", qid);
 462                 dev_ops->rx_queue_release(eth_dev, qid);
 463                 eth_dev->data->rx_queues[qid] = NULL;
 464         }
 465
 466         /* Clam up cq limit to size of packet pool aura for LBK
 467          * to avoid meta packet drop as LBK does not currently support
 468          * backpressure.
 469          */
 470         if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY && roc_nix_is_lbk(nix)) {
 471                 uint64_t pkt_pool_limit = roc_nix_inl_dev_rq_limit_get();
 472
 473                 /* Use current RQ's aura limit if inl rq is not available */
 474                 if (!pkt_pool_limit)
 475                         pkt_pool_limit = roc_npa_aura_op_limit_get(mp->pool_id);
 476                 nb_desc = RTE_MAX(nb_desc, pkt_pool_limit);
 477         }
 478
 479         /* Setup ROC CQ */
 480         cq = &dev->cqs[qid];
 481         cq->qid = qid;
 482         cq->nb_desc = nb_desc;
 483         rc = roc_nix_cq_init(&dev->nix, cq);
 484         if (rc) {
 485                 plt_err("Failed to init roc cq for rq=%d, rc=%d", qid, rc);
 486                 goto fail;
 487         }
 488
 489         /* Setup ROC RQ */
 490         rq = &dev->rqs[qid];
 491         rq->qid = qid;
 492         rq->aura_handle = mp->pool_id;
 493         rq->flow_tag_width = 32;
 494         rq->sso_ena = false;
 495
 496         /* Calculate first mbuf skip */
 497         first_skip = (sizeof(struct rte_mbuf));
 498         first_skip += RTE_PKTMBUF_HEADROOM;
 499         first_skip += rte_pktmbuf_priv_size(mp);
 500         rq->first_skip = first_skip;
 501         rq->later_skip = sizeof(struct rte_mbuf);
 502         rq->lpb_size = mp->elt_size;
 503
 504         /* Enable Inline IPSec on RQ, will not be used for Poll mode */
 505         if (roc_nix_inl_inb_is_enabled(nix))
 506                 rq->ipsech_ena = true;
 507
 508         rc = roc_nix_rq_init(&dev->nix, rq, !!eth_dev->data->dev_started);
 509         if (rc) {
 510                 plt_err("Failed to init roc rq for rq=%d, rc=%d", qid, rc);
 511                 goto cq_fini;
 512         }
 513
 514         /* Allocate and setup fast path rx queue */
 515         rc = -ENOMEM;
 516         rxq_sz = sizeof(struct cnxk_eth_rxq_sp) + fp_rx_q_sz;
 517         rxq_sp = plt_zmalloc(rxq_sz, PLT_CACHE_LINE_SIZE);
 518         if (!rxq_sp) {
 519                 plt_err("Failed to alloc rx queue for rq=%d", qid);
 520                 goto rq_fini;
 521         }
 522
 523         /* Setup slow path fields */
 524         rxq_sp->dev = dev;
 525         rxq_sp->qid = qid;
 526         rxq_sp->qconf.conf.rx = *rx_conf;
 527         /* Queue config should reflect global offloads */
 528         rxq_sp->qconf.conf.rx.offloads = dev->rx_offloads;
 529         rxq_sp->qconf.nb_desc = nb_desc;
 530         rxq_sp->qconf.mp = mp;
 531
 532         if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
 533                 /* Setup rq reference for inline dev if present */
 534                 rc = roc_nix_inl_dev_rq_get(rq);
 535                 if (rc)
 536                         goto free_mem;
 537         }
 538
 539         plt_nix_dbg("rq=%d pool=%s nb_desc=%d->%d", qid, mp->name, nb_desc,
 540                     cq->nb_desc);
 541
 542         /* Store start of fast path area */
 543         eth_dev->data->rx_queues[qid] = rxq_sp + 1;
 544         eth_dev->data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
 545
 546         /* Calculating delta and freq mult between PTP HI clock and tsc.
 547          * These are needed in deriving raw clock value from tsc counter.
 548          * read_clock eth op returns raw clock value.
 549          */
 550         if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) || dev->ptp_en) {
 551                 rc = cnxk_nix_tsc_convert(dev);
 552                 if (rc) {
 553                         plt_err("Failed to calculate delta and freq mult");
 554                         goto rq_fini;
 555                 }
 556         }
 557
 558         return 0;
 559 free_mem:
 560         plt_free(rxq_sp);
 561 rq_fini:
 562         rc |= roc_nix_rq_fini(rq);
 563 cq_fini:
 564         rc |= roc_nix_cq_fini(cq);
 565 fail:
 566         return rc;
 567 }
 568
 569 static void
 570 cnxk_nix_rx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)
 571 {
 572         void *rxq = eth_dev->data->rx_queues[qid];
 573         struct cnxk_eth_rxq_sp *rxq_sp;
 574         struct cnxk_eth_dev *dev;
 575         struct roc_nix_rq *rq;
 576         struct roc_nix_cq *cq;
 577         int rc;
 578
 579         if (!rxq)
 580                 return;
 581
 582         rxq_sp = cnxk_eth_rxq_to_sp(rxq);
 583         dev = rxq_sp->dev;
 584         rq = &dev->rqs[qid];
 585
 586         plt_nix_dbg("Releasing rxq %u", qid);
 587
 588         /* Release rq reference for inline dev if present */
 589         if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY)
 590                 roc_nix_inl_dev_rq_put(rq);
 591
 592         /* Cleanup ROC RQ */
 593         rc = roc_nix_rq_fini(rq);
 594         if (rc)
 595                 plt_err("Failed to cleanup rq, rc=%d", rc);
 596
 597         /* Cleanup ROC CQ */
 598         cq = &dev->cqs[qid];
 599         rc = roc_nix_cq_fini(cq);
 600         if (rc)
 601                 plt_err("Failed to cleanup cq, rc=%d", rc);
 602
 603         /* Finally free fast path area */
 604         plt_free(rxq_sp);
 605 }
 606
 607 uint32_t
 608 cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
 609                        uint8_t rss_level)
 610 {
 611         uint32_t flow_key_type[RSS_MAX_LEVELS][6] = {
 612                 {FLOW_KEY_TYPE_IPV4, FLOW_KEY_TYPE_IPV6, FLOW_KEY_TYPE_TCP,
 613                  FLOW_KEY_TYPE_UDP, FLOW_KEY_TYPE_SCTP, FLOW_KEY_TYPE_ETH_DMAC},
 614                 {FLOW_KEY_TYPE_INNR_IPV4, FLOW_KEY_TYPE_INNR_IPV6,
 615                  FLOW_KEY_TYPE_INNR_TCP, FLOW_KEY_TYPE_INNR_UDP,
 616                  FLOW_KEY_TYPE_INNR_SCTP, FLOW_KEY_TYPE_INNR_ETH_DMAC},
 617                 {FLOW_KEY_TYPE_IPV4 | FLOW_KEY_TYPE_INNR_IPV4,
 618                  FLOW_KEY_TYPE_IPV6 | FLOW_KEY_TYPE_INNR_IPV6,
 619                  FLOW_KEY_TYPE_TCP | FLOW_KEY_TYPE_INNR_TCP,
 620                  FLOW_KEY_TYPE_UDP | FLOW_KEY_TYPE_INNR_UDP,
 621                  FLOW_KEY_TYPE_SCTP | FLOW_KEY_TYPE_INNR_SCTP,
 622                  FLOW_KEY_TYPE_ETH_DMAC | FLOW_KEY_TYPE_INNR_ETH_DMAC}
 623         };
 624         uint32_t flowkey_cfg = 0;
 625
 626         dev->ethdev_rss_hf = ethdev_rss;
 627
 628         if (ethdev_rss & ETH_RSS_L2_PAYLOAD &&
 629             dev->npc.switch_header_type == ROC_PRIV_FLAGS_LEN_90B) {
 630                 flowkey_cfg |= FLOW_KEY_TYPE_CH_LEN_90B;
 631         }
 632
 633         if (ethdev_rss & ETH_RSS_C_VLAN)
 634                 flowkey_cfg |= FLOW_KEY_TYPE_VLAN;
 635
 636         if (ethdev_rss & ETH_RSS_L3_SRC_ONLY)
 637                 flowkey_cfg |= FLOW_KEY_TYPE_L3_SRC;
 638
 639         if (ethdev_rss & ETH_RSS_L3_DST_ONLY)
 640                 flowkey_cfg |= FLOW_KEY_TYPE_L3_DST;
 641
 642         if (ethdev_rss & ETH_RSS_L4_SRC_ONLY)
 643                 flowkey_cfg |= FLOW_KEY_TYPE_L4_SRC;
 644
 645         if (ethdev_rss & ETH_RSS_L4_DST_ONLY)
 646                 flowkey_cfg |= FLOW_KEY_TYPE_L4_DST;
 647
 648         if (ethdev_rss & RSS_IPV4_ENABLE)
 649                 flowkey_cfg |= flow_key_type[rss_level][RSS_IPV4_INDEX];
 650
 651         if (ethdev_rss & RSS_IPV6_ENABLE)
 652                 flowkey_cfg |= flow_key_type[rss_level][RSS_IPV6_INDEX];
 653
 654         if (ethdev_rss & ETH_RSS_TCP)
 655                 flowkey_cfg |= flow_key_type[rss_level][RSS_TCP_INDEX];
 656
 657         if (ethdev_rss & ETH_RSS_UDP)
 658                 flowkey_cfg |= flow_key_type[rss_level][RSS_UDP_INDEX];
 659
 660         if (ethdev_rss & ETH_RSS_SCTP)
 661                 flowkey_cfg |= flow_key_type[rss_level][RSS_SCTP_INDEX];
 662
 663         if (ethdev_rss & ETH_RSS_L2_PAYLOAD)
 664                 flowkey_cfg |= flow_key_type[rss_level][RSS_DMAC_INDEX];
 665
 666         if (ethdev_rss & RSS_IPV6_EX_ENABLE)
 667                 flowkey_cfg |= FLOW_KEY_TYPE_IPV6_EXT;
 668
 669         if (ethdev_rss & ETH_RSS_PORT)
 670                 flowkey_cfg |= FLOW_KEY_TYPE_PORT;
 671
 672         if (ethdev_rss & ETH_RSS_NVGRE)
 673                 flowkey_cfg |= FLOW_KEY_TYPE_NVGRE;
 674
 675         if (ethdev_rss & ETH_RSS_VXLAN)
 676                 flowkey_cfg |= FLOW_KEY_TYPE_VXLAN;
 677
 678         if (ethdev_rss & ETH_RSS_GENEVE)
 679                 flowkey_cfg |= FLOW_KEY_TYPE_GENEVE;
 680
 681         if (ethdev_rss & ETH_RSS_GTPU)
 682                 flowkey_cfg |= FLOW_KEY_TYPE_GTPU;
 683
 684         return flowkey_cfg;
 685 }
 686
 687 static void
 688 nix_free_queue_mem(struct cnxk_eth_dev *dev)
 689 {
 690         plt_free(dev->rqs);
 691         plt_free(dev->cqs);
 692         plt_free(dev->sqs);
 693         dev->rqs = NULL;
 694         dev->cqs = NULL;
 695         dev->sqs = NULL;
 696 }
 697
 698 static int
 699 nix_ingress_policer_setup(struct cnxk_eth_dev *dev)
 700 {
 701         TAILQ_INIT(&dev->mtr_profiles);
 702
 703         return 0;
 704 }
 705
 706 static int
 707 nix_rss_default_setup(struct cnxk_eth_dev *dev)
 708 {
 709         struct rte_eth_dev *eth_dev = dev->eth_dev;
 710         uint8_t rss_hash_level;
 711         uint32_t flowkey_cfg;
 712         uint64_t rss_hf;
 713
 714         rss_hf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
 715         rss_hash_level = ETH_RSS_LEVEL(rss_hf);
 716         if (rss_hash_level)
 717                 rss_hash_level -= 1;
 718
 719         flowkey_cfg = cnxk_rss_ethdev_to_nix(dev, rss_hf, rss_hash_level);
 720         return roc_nix_rss_default_setup(&dev->nix, flowkey_cfg);
 721 }
 722
 723 static int
 724 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
 725 {
 726         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 727         const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
 728         struct cnxk_eth_qconf *tx_qconf = NULL;
 729         struct cnxk_eth_qconf *rx_qconf = NULL;
 730         struct cnxk_eth_rxq_sp *rxq_sp;
 731         struct cnxk_eth_txq_sp *txq_sp;
 732         int i, nb_rxq, nb_txq;
 733         void **txq, **rxq;
 734
 735         nb_rxq = RTE_MIN(dev->nb_rxq, eth_dev->data->nb_rx_queues);
 736         nb_txq = RTE_MIN(dev->nb_txq, eth_dev->data->nb_tx_queues);
 737
 738         tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
 739         if (tx_qconf == NULL) {
 740                 plt_err("Failed to allocate memory for tx_qconf");
 741                 goto fail;
 742         }
 743
 744         rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
 745         if (rx_qconf == NULL) {
 746                 plt_err("Failed to allocate memory for rx_qconf");
 747                 goto fail;
 748         }
 749
 750         txq = eth_dev->data->tx_queues;
 751         for (i = 0; i < nb_txq; i++) {
 752                 if (txq[i] == NULL) {
 753                         tx_qconf[i].valid = false;
 754                         plt_info("txq[%d] is already released", i);
 755                         continue;
 756                 }
 757                 txq_sp = cnxk_eth_txq_to_sp(txq[i]);
 758                 memcpy(&tx_qconf[i], &txq_sp->qconf, sizeof(*tx_qconf));
 759                 tx_qconf[i].valid = true;
 760                 dev_ops->tx_queue_release(eth_dev, i);
 761                 eth_dev->data->tx_queues[i] = NULL;
 762         }
 763
 764         rxq = eth_dev->data->rx_queues;
 765         for (i = 0; i < nb_rxq; i++) {
 766                 if (rxq[i] == NULL) {
 767                         rx_qconf[i].valid = false;
 768                         plt_info("rxq[%d] is already released", i);
 769                         continue;
 770                 }
 771                 rxq_sp = cnxk_eth_rxq_to_sp(rxq[i]);
 772                 memcpy(&rx_qconf[i], &rxq_sp->qconf, sizeof(*rx_qconf));
 773                 rx_qconf[i].valid = true;
 774                 dev_ops->rx_queue_release(eth_dev, i);
 775                 eth_dev->data->rx_queues[i] = NULL;
 776         }
 777
 778         dev->tx_qconf = tx_qconf;
 779         dev->rx_qconf = rx_qconf;
 780         return 0;
 781
 782 fail:
 783         free(tx_qconf);
 784         free(rx_qconf);
 785         return -ENOMEM;
 786 }
 787
 788 static int
 789 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
 790 {
 791         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 792         const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
 793         struct cnxk_eth_qconf *tx_qconf = dev->tx_qconf;
 794         struct cnxk_eth_qconf *rx_qconf = dev->rx_qconf;
 795         int rc, i, nb_rxq, nb_txq;
 796
 797         nb_rxq = RTE_MIN(dev->nb_rxq, eth_dev->data->nb_rx_queues);
 798         nb_txq = RTE_MIN(dev->nb_txq, eth_dev->data->nb_tx_queues);
 799
 800         rc = -ENOMEM;
 801         /* Setup tx & rx queues with previous configuration so
 802          * that the queues can be functional in cases like ports
 803          * are started without re configuring queues.
 804          *
 805          * Usual re config sequence is like below:
 806          * port_configure() {
 807          *      if(reconfigure) {
 808          *              queue_release()
 809          *              queue_setup()
 810          *      }
 811          *      queue_configure() {
 812          *              queue_release()
 813          *              queue_setup()
 814          *      }
 815          * }
 816          * port_start()
 817          *
 818          * In some application's control path, queue_configure() would
 819          * NOT be invoked for TXQs/RXQs in port_configure().
 820          * In such cases, queues can be functional after start as the
 821          * queues are already setup in port_configure().
 822          */
 823         for (i = 0; i < nb_txq; i++) {
 824                 if (!tx_qconf[i].valid)
 825                         continue;
 826                 rc = dev_ops->tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc, 0,
 827                                              &tx_qconf[i].conf.tx);
 828                 if (rc) {
 829                         plt_err("Failed to setup tx queue rc=%d", rc);
 830                         for (i -= 1; i >= 0; i--)
 831                                 dev_ops->tx_queue_release(eth_dev, i);
 832                         goto fail;
 833                 }
 834         }
 835
 836         free(tx_qconf);
 837         tx_qconf = NULL;
 838
 839         for (i = 0; i < nb_rxq; i++) {
 840                 if (!rx_qconf[i].valid)
 841                         continue;
 842                 rc = dev_ops->rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc, 0,
 843                                              &rx_qconf[i].conf.rx,
 844                                              rx_qconf[i].mp);
 845                 if (rc) {
 846                         plt_err("Failed to setup rx queue rc=%d", rc);
 847                         for (i -= 1; i >= 0; i--)
 848                                 dev_ops->rx_queue_release(eth_dev, i);
 849                         goto tx_queue_release;
 850                 }
 851         }
 852
 853         free(rx_qconf);
 854         rx_qconf = NULL;
 855
 856         return 0;
 857
 858 tx_queue_release:
 859         for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
 860                 dev_ops->tx_queue_release(eth_dev, i);
 861 fail:
 862         if (tx_qconf)
 863                 free(tx_qconf);
 864         if (rx_qconf)
 865                 free(rx_qconf);
 866
 867         return rc;
 868 }
 869
 870 static uint16_t
 871 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
 872 {
 873         RTE_SET_USED(queue);
 874         RTE_SET_USED(mbufs);
 875         RTE_SET_USED(pkts);
 876
 877         return 0;
 878 }
 879
 880 static void
 881 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
 882 {
 883         /* These dummy functions are required for supporting
 884          * some applications which reconfigure queues without
 885          * stopping tx burst and rx burst threads(eg kni app)
 886          * When the queues context is saved, txq/rxqs are released
 887          * which caused app crash since rx/tx burst is still
 888          * on different lcores
 889          */
 890         eth_dev->tx_pkt_burst = nix_eth_nop_burst;
 891         eth_dev->rx_pkt_burst = nix_eth_nop_burst;
 892         rte_mb();
 893 }
 894
 895 static int
 896 nix_lso_tun_fmt_update(struct cnxk_eth_dev *dev)
 897 {
 898         uint8_t udp_tun[ROC_NIX_LSO_TUN_MAX];
 899         uint8_t tun[ROC_NIX_LSO_TUN_MAX];
 900         struct roc_nix *nix = &dev->nix;
 901         int rc;
 902
 903         rc = roc_nix_lso_fmt_get(nix, udp_tun, tun);
 904         if (rc)
 905                 return rc;
 906
 907         dev->lso_tun_fmt = ((uint64_t)tun[ROC_NIX_LSO_TUN_V4V4] |
 908                             (uint64_t)tun[ROC_NIX_LSO_TUN_V4V6] << 8 |
 909                             (uint64_t)tun[ROC_NIX_LSO_TUN_V6V4] << 16 |
 910                             (uint64_t)tun[ROC_NIX_LSO_TUN_V6V6] << 24);
 911
 912         dev->lso_tun_fmt |= ((uint64_t)udp_tun[ROC_NIX_LSO_TUN_V4V4] << 32 |
 913                              (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V4V6] << 40 |
 914                              (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V6V4] << 48 |
 915                              (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V6V6] << 56);
 916         return 0;
 917 }
 918
 919 static int
 920 nix_lso_fmt_setup(struct cnxk_eth_dev *dev)
 921 {
 922         struct roc_nix *nix = &dev->nix;
 923         int rc;
 924
 925         /* Nothing much to do if offload is not enabled */
 926         if (!(dev->tx_offloads &
 927               (DEV_TX_OFFLOAD_TCP_TSO | DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 928                DEV_TX_OFFLOAD_GENEVE_TNL_TSO | DEV_TX_OFFLOAD_GRE_TNL_TSO)))
 929                 return 0;
 930
 931         /* Setup LSO formats in AF. Its a no-op if other ethdev has
 932          * already set it up
 933          */
 934         rc = roc_nix_lso_fmt_setup(nix);
 935         if (rc)
 936                 return rc;
 937
 938         return nix_lso_tun_fmt_update(dev);
 939 }
 940
 941 int
 942 cnxk_nix_configure(struct rte_eth_dev *eth_dev)
 943 {
 944         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 945         struct rte_eth_dev_data *data = eth_dev->data;
 946         struct rte_eth_conf *conf = &data->dev_conf;
 947         struct rte_eth_rxmode *rxmode = &conf->rxmode;
 948         struct rte_eth_txmode *txmode = &conf->txmode;
 949         char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
 950         struct roc_nix_fc_cfg fc_cfg = {0};
 951         struct roc_nix *nix = &dev->nix;
 952         struct rte_ether_addr *ea;
 953         uint8_t nb_rxq, nb_txq;
 954         uint64_t rx_cfg;
 955         void *qs;
 956         int rc;
 957
 958         rc = -EINVAL;
 959
 960         /* Sanity checks */
 961         if (rte_eal_has_hugepages() == 0) {
 962                 plt_err("Huge page is not configured");
 963                 goto fail_configure;
 964         }
 965
 966         if (conf->dcb_capability_en == 1) {
 967                 plt_err("dcb enable is not supported");
 968                 goto fail_configure;
 969         }
 970
 971         if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
 972                 plt_err("Flow director is not supported");
 973                 goto fail_configure;
 974         }
 975
 976         if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
 977             rxmode->mq_mode != ETH_MQ_RX_RSS) {
 978                 plt_err("Unsupported mq rx mode %d", rxmode->mq_mode);
 979                 goto fail_configure;
 980         }
 981
 982         if (txmode->mq_mode != ETH_MQ_TX_NONE) {
 983                 plt_err("Unsupported mq tx mode %d", txmode->mq_mode);
 984                 goto fail_configure;
 985         }
 986
 987         /* Free the resources allocated from the previous configure */
 988         if (dev->configured == 1) {
 989                 /* Unregister queue irq's */
 990                 roc_nix_unregister_queue_irqs(nix);
 991
 992                 /* Unregister CQ irqs if present */
 993                 if (eth_dev->data->dev_conf.intr_conf.rxq)
 994                         roc_nix_unregister_cq_irqs(nix);
 995
 996                 /* Set no-op functions */
 997                 nix_set_nop_rxtx_function(eth_dev);
 998                 /* Store queue config for later */
 999                 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1000                 if (rc)
1001                         goto fail_configure;
1002
1003                 /* Cleanup security support */
1004                 rc = nix_security_release(dev);
1005                 if (rc)
1006                         goto fail_configure;
1007
1008                 roc_nix_tm_fini(nix);
1009                 roc_nix_lf_free(nix);
1010         }
1011
1012         dev->rx_offloads = rxmode->offloads;
1013         dev->tx_offloads = txmode->offloads;
1014
1015         /* Prepare rx cfg */
1016         rx_cfg = ROC_NIX_LF_RX_CFG_DIS_APAD;
1017         if (dev->rx_offloads &
1018             (DEV_RX_OFFLOAD_TCP_CKSUM | DEV_RX_OFFLOAD_UDP_CKSUM)) {
1019                 rx_cfg |= ROC_NIX_LF_RX_CFG_CSUM_OL4;
1020                 rx_cfg |= ROC_NIX_LF_RX_CFG_CSUM_IL4;
1021         }
1022         rx_cfg |= (ROC_NIX_LF_RX_CFG_DROP_RE | ROC_NIX_LF_RX_CFG_L2_LEN_ERR |
1023                    ROC_NIX_LF_RX_CFG_LEN_IL4 | ROC_NIX_LF_RX_CFG_LEN_IL3 |
1024                    ROC_NIX_LF_RX_CFG_LEN_OL4 | ROC_NIX_LF_RX_CFG_LEN_OL3);
1025
1026         if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
1027                 rx_cfg |= ROC_NIX_LF_RX_CFG_IP6_UDP_OPT;
1028                 /* Disable drop re if rx offload security is enabled and
1029                  * platform does not support it.
1030                  */
1031                 if (dev->ipsecd_drop_re_dis)
1032                         rx_cfg &= ~(ROC_NIX_LF_RX_CFG_DROP_RE);
1033         }
1034
1035         nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1036         nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1037
1038         /* Alloc a nix lf */
1039         rc = roc_nix_lf_alloc(nix, nb_rxq, nb_txq, rx_cfg);
1040         if (rc) {
1041                 plt_err("Failed to init nix_lf rc=%d", rc);
1042                 goto fail_configure;
1043         }
1044
1045         dev->npc.channel = roc_nix_get_base_chan(nix);
1046
1047         nb_rxq = data->nb_rx_queues;
1048         nb_txq = data->nb_tx_queues;
1049         rc = -ENOMEM;
1050         if (nb_rxq) {
1051                 /* Allocate memory for roc rq's and cq's */
1052                 qs = plt_zmalloc(sizeof(struct roc_nix_rq) * nb_rxq, 0);
1053                 if (!qs) {
1054                         plt_err("Failed to alloc rqs");
1055                         goto free_nix_lf;
1056                 }
1057                 dev->rqs = qs;
1058
1059                 qs = plt_zmalloc(sizeof(struct roc_nix_cq) * nb_rxq, 0);
1060                 if (!qs) {
1061                         plt_err("Failed to alloc cqs");
1062                         goto free_nix_lf;
1063                 }
1064                 dev->cqs = qs;
1065         }
1066
1067         if (nb_txq) {
1068                 /* Allocate memory for roc sq's */
1069                 qs = plt_zmalloc(sizeof(struct roc_nix_sq) * nb_txq, 0);
1070                 if (!qs) {
1071                         plt_err("Failed to alloc sqs");
1072                         goto free_nix_lf;
1073                 }
1074                 dev->sqs = qs;
1075         }
1076
1077         /* Re-enable NIX LF error interrupts */
1078         roc_nix_err_intr_ena_dis(nix, true);
1079         roc_nix_ras_intr_ena_dis(nix, true);
1080
1081         if (nix->rx_ptp_ena &&
1082             dev->npc.switch_header_type == ROC_PRIV_FLAGS_HIGIG) {
1083                 plt_err("Both PTP and switch header enabled");
1084                 goto free_nix_lf;
1085         }
1086
1087         rc = roc_nix_switch_hdr_set(nix, dev->npc.switch_header_type);
1088         if (rc) {
1089                 plt_err("Failed to enable switch type nix_lf rc=%d", rc);
1090                 goto free_nix_lf;
1091         }
1092
1093         /* Setup LSO if needed */
1094         rc = nix_lso_fmt_setup(dev);
1095         if (rc) {
1096                 plt_err("Failed to setup nix lso format fields, rc=%d", rc);
1097                 goto free_nix_lf;
1098         }
1099
1100         /* Configure RSS */
1101         rc = nix_rss_default_setup(dev);
1102         if (rc) {
1103                 plt_err("Failed to configure rss rc=%d", rc);
1104                 goto free_nix_lf;
1105         }
1106
1107         /* Init the default TM scheduler hierarchy */
1108         rc = roc_nix_tm_init(nix);
1109         if (rc) {
1110                 plt_err("Failed to init traffic manager, rc=%d", rc);
1111                 goto free_nix_lf;
1112         }
1113
1114         rc = nix_ingress_policer_setup(dev);
1115         if (rc) {
1116                 plt_err("Failed to setup ingress policer rc=%d", rc);
1117                 goto free_nix_lf;
1118         }
1119
1120         rc = roc_nix_tm_hierarchy_enable(nix, ROC_NIX_TM_DEFAULT, false);
1121         if (rc) {
1122                 plt_err("Failed to enable default tm hierarchy, rc=%d", rc);
1123                 goto tm_fini;
1124         }
1125
1126         /* Register queue IRQs */
1127         rc = roc_nix_register_queue_irqs(nix);
1128         if (rc) {
1129                 plt_err("Failed to register queue interrupts rc=%d", rc);
1130                 goto tm_fini;
1131         }
1132
1133         /* Register cq IRQs */
1134         if (eth_dev->data->dev_conf.intr_conf.rxq) {
1135                 if (eth_dev->data->nb_rx_queues > dev->nix.cints) {
1136                         plt_err("Rx interrupt cannot be enabled, rxq > %d",
1137                                 dev->nix.cints);
1138                         goto q_irq_fini;
1139                 }
1140                 /* Rx interrupt feature cannot work with vector mode because,
1141                  * vector mode does not process packets unless min 4 pkts are
1142                  * received, while cq interrupts are generated even for 1 pkt
1143                  * in the CQ.
1144                  */
1145                 dev->scalar_ena = true;
1146
1147                 rc = roc_nix_register_cq_irqs(nix);
1148                 if (rc) {
1149                         plt_err("Failed to register CQ interrupts rc=%d", rc);
1150                         goto q_irq_fini;
1151                 }
1152         }
1153
1154         /* Configure loop back mode */
1155         rc = roc_nix_mac_loopback_enable(nix,
1156                                          eth_dev->data->dev_conf.lpbk_mode);
1157         if (rc) {
1158                 plt_err("Failed to configure cgx loop back mode rc=%d", rc);
1159                 goto cq_fini;
1160         }
1161
1162         /* Init flow control configuration */
1163         fc_cfg.cq_cfg_valid = false;
1164         fc_cfg.rxchan_cfg.enable = true;
1165         rc = roc_nix_fc_config_set(nix, &fc_cfg);
1166         if (rc) {
1167                 plt_err("Failed to initialize flow control rc=%d", rc);
1168                 goto cq_fini;
1169         }
1170
1171         /* Update flow control configuration to PMD */
1172         rc = nix_init_flow_ctrl_config(eth_dev);
1173         if (rc) {
1174                 plt_err("Failed to initialize flow control rc=%d", rc);
1175                 goto cq_fini;
1176         }
1177
1178         /* Setup Inline security support */
1179         rc = nix_security_setup(dev);
1180         if (rc)
1181                 goto cq_fini;
1182
1183         /*
1184          * Restore queue config when reconfigure followed by
1185          * reconfigure and no queue configure invoked from application case.
1186          */
1187         if (dev->configured == 1) {
1188                 rc = nix_restore_queue_cfg(eth_dev);
1189                 if (rc)
1190                         goto sec_release;
1191         }
1192
1193         /* Update the mac address */
1194         ea = eth_dev->data->mac_addrs;
1195         memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1196         if (rte_is_zero_ether_addr(ea))
1197                 rte_eth_random_addr((uint8_t *)ea);
1198
1199         rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
1200
1201         plt_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
1202                     " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 "",
1203                     eth_dev->data->port_id, ea_fmt, nb_rxq, nb_txq,
1204                     dev->rx_offloads, dev->tx_offloads);
1205
1206         /* All good */
1207         dev->configured = 1;
1208         dev->nb_rxq = data->nb_rx_queues;
1209         dev->nb_txq = data->nb_tx_queues;
1210         return 0;
1211
1212 sec_release:
1213         rc |= nix_security_release(dev);
1214 cq_fini:
1215         roc_nix_unregister_cq_irqs(nix);
1216 q_irq_fini:
1217         roc_nix_unregister_queue_irqs(nix);
1218 tm_fini:
1219         roc_nix_tm_fini(nix);
1220 free_nix_lf:
1221         nix_free_queue_mem(dev);
1222         rc |= roc_nix_lf_free(nix);
1223 fail_configure:
1224         dev->configured = 0;
1225         return rc;
1226 }
1227
1228 int
1229 cnxk_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid)
1230 {
1231         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1232         struct rte_eth_dev_data *data = eth_dev->data;
1233         struct roc_nix_sq *sq = &dev->sqs[qid];
1234         int rc = -EINVAL;
1235
1236         if (data->tx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STARTED)
1237                 return 0;
1238
1239         rc = roc_nix_tm_sq_aura_fc(sq, true);
1240         if (rc) {
1241                 plt_err("Failed to enable sq aura fc, txq=%u, rc=%d", qid, rc);
1242                 goto done;
1243         }
1244
1245         data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STARTED;
1246 done:
1247         return rc;
1248 }
1249
1250 int
1251 cnxk_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid)
1252 {
1253         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1254         struct rte_eth_dev_data *data = eth_dev->data;
1255         struct roc_nix_sq *sq = &dev->sqs[qid];
1256         int rc;
1257
1258         if (data->tx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STOPPED)
1259                 return 0;
1260
1261         rc = roc_nix_tm_sq_aura_fc(sq, false);
1262         if (rc) {
1263                 plt_err("Failed to disable sqb aura fc, txq=%u, rc=%d", qid,
1264                         rc);
1265                 goto done;
1266         }
1267
1268         data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
1269 done:
1270         return rc;
1271 }
1272
1273 static int
1274 cnxk_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid)
1275 {
1276         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1277         struct rte_eth_dev_data *data = eth_dev->data;
1278         struct roc_nix_rq *rq = &dev->rqs[qid];
1279         int rc;
1280
1281         if (data->rx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STARTED)
1282                 return 0;
1283
1284         rc = roc_nix_rq_ena_dis(rq, true);
1285         if (rc) {
1286                 plt_err("Failed to enable rxq=%u, rc=%d", qid, rc);
1287                 goto done;
1288         }
1289
1290         data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STARTED;
1291 done:
1292         return rc;
1293 }
1294
1295 static int
1296 cnxk_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid)
1297 {
1298         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1299         struct rte_eth_dev_data *data = eth_dev->data;
1300         struct roc_nix_rq *rq = &dev->rqs[qid];
1301         int rc;
1302
1303         if (data->rx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STOPPED)
1304                 return 0;
1305
1306         rc = roc_nix_rq_ena_dis(rq, false);
1307         if (rc) {
1308                 plt_err("Failed to disable rxq=%u, rc=%d", qid, rc);
1309                 goto done;
1310         }
1311
1312         data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
1313 done:
1314         return rc;
1315 }
1316
1317 static int
1318 cnxk_nix_dev_stop(struct rte_eth_dev *eth_dev)
1319 {
1320         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1321         const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
1322         struct rte_mbuf *rx_pkts[32];
1323         struct rte_eth_link link;
1324         int count, i, j, rc;
1325         void *rxq;
1326
1327         /* Disable switch hdr pkind */
1328         roc_nix_switch_hdr_set(&dev->nix, 0);
1329
1330         /* Stop link change events */
1331         if (!roc_nix_is_vf_or_sdp(&dev->nix))
1332                 roc_nix_mac_link_event_start_stop(&dev->nix, false);
1333
1334         /* Disable Rx via NPC */
1335         roc_nix_npc_rx_ena_dis(&dev->nix, false);
1336
1337         /* Stop rx queues and free up pkts pending */
1338         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1339                 rc = dev_ops->rx_queue_stop(eth_dev, i);
1340                 if (rc)
1341                         continue;
1342
1343                 rxq = eth_dev->data->rx_queues[i];
1344                 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1345                 while (count) {
1346                         for (j = 0; j < count; j++)
1347                                 rte_pktmbuf_free(rx_pkts[j]);
1348                         count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1349                 }
1350         }
1351
1352         /* Stop tx queues  */
1353         for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1354                 dev_ops->tx_queue_stop(eth_dev, i);
1355
1356         /* Bring down link status internally */
1357         memset(&link, 0, sizeof(link));
1358         rte_eth_linkstatus_set(eth_dev, &link);
1359
1360         return 0;
1361 }
1362
1363 int
1364 cnxk_nix_dev_start(struct rte_eth_dev *eth_dev)
1365 {
1366         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1367         int rc, i;
1368
1369         if (eth_dev->data->nb_rx_queues != 0 && !dev->ptp_en) {
1370                 rc = nix_recalc_mtu(eth_dev);
1371                 if (rc)
1372                         return rc;
1373         }
1374
1375         /* Start rx queues */
1376         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1377                 rc = cnxk_nix_rx_queue_start(eth_dev, i);
1378                 if (rc)
1379                         return rc;
1380         }
1381
1382         /* Start tx queues  */
1383         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1384                 rc = cnxk_nix_tx_queue_start(eth_dev, i);
1385                 if (rc)
1386                         return rc;
1387         }
1388
1389         /* Update Flow control configuration */
1390         rc = nix_update_flow_ctrl_config(eth_dev);
1391         if (rc) {
1392                 plt_err("Failed to enable flow control. error code(%d)", rc);
1393                 return rc;
1394         }
1395
1396         /* Enable Rx in NPC */
1397         rc = roc_nix_npc_rx_ena_dis(&dev->nix, true);
1398         if (rc) {
1399                 plt_err("Failed to enable NPC rx %d", rc);
1400                 return rc;
1401         }
1402
1403         cnxk_nix_toggle_flag_link_cfg(dev, true);
1404
1405         /* Start link change events */
1406         if (!roc_nix_is_vf_or_sdp(&dev->nix)) {
1407                 rc = roc_nix_mac_link_event_start_stop(&dev->nix, true);
1408                 if (rc) {
1409                         plt_err("Failed to start cgx link event %d", rc);
1410                         goto rx_disable;
1411                 }
1412         }
1413
1414         /* Enable PTP if it is requested by the user or already
1415          * enabled on PF owning this VF
1416          */
1417         memset(&dev->tstamp, 0, sizeof(struct cnxk_timesync_info));
1418         if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) || dev->ptp_en)
1419                 cnxk_eth_dev_ops.timesync_enable(eth_dev);
1420         else
1421                 cnxk_eth_dev_ops.timesync_disable(eth_dev);
1422
1423         if (dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) {
1424                 rc = rte_mbuf_dyn_rx_timestamp_register
1425                         (&dev->tstamp.tstamp_dynfield_offset,
1426                          &dev->tstamp.rx_tstamp_dynflag);
1427                 if (rc != 0) {
1428                         plt_err("Failed to register Rx timestamp field/flag");
1429                         goto rx_disable;
1430                 }
1431         }
1432
1433         cnxk_nix_toggle_flag_link_cfg(dev, false);
1434
1435         return 0;
1436
1437 rx_disable:
1438         roc_nix_npc_rx_ena_dis(&dev->nix, false);
1439         cnxk_nix_toggle_flag_link_cfg(dev, false);
1440         return rc;
1441 }
1442
1443 static int cnxk_nix_dev_reset(struct rte_eth_dev *eth_dev);
1444 static int cnxk_nix_dev_close(struct rte_eth_dev *eth_dev);
1445
1446 /* CNXK platform independent eth dev ops */
1447 struct eth_dev_ops cnxk_eth_dev_ops = {
1448         .mtu_set = cnxk_nix_mtu_set,
1449         .mac_addr_add = cnxk_nix_mac_addr_add,
1450         .mac_addr_remove = cnxk_nix_mac_addr_del,
1451         .mac_addr_set = cnxk_nix_mac_addr_set,
1452         .dev_infos_get = cnxk_nix_info_get,
1453         .link_update = cnxk_nix_link_update,
1454         .tx_queue_release = cnxk_nix_tx_queue_release,
1455         .rx_queue_release = cnxk_nix_rx_queue_release,
1456         .dev_stop = cnxk_nix_dev_stop,
1457         .dev_close = cnxk_nix_dev_close,
1458         .dev_reset = cnxk_nix_dev_reset,
1459         .tx_queue_start = cnxk_nix_tx_queue_start,
1460         .rx_queue_start = cnxk_nix_rx_queue_start,
1461         .rx_queue_stop = cnxk_nix_rx_queue_stop,
1462         .dev_supported_ptypes_get = cnxk_nix_supported_ptypes_get,
1463         .promiscuous_enable = cnxk_nix_promisc_enable,
1464         .promiscuous_disable = cnxk_nix_promisc_disable,
1465         .allmulticast_enable = cnxk_nix_allmulticast_enable,
1466         .allmulticast_disable = cnxk_nix_allmulticast_disable,
1467         .rx_burst_mode_get = cnxk_nix_rx_burst_mode_get,
1468         .tx_burst_mode_get = cnxk_nix_tx_burst_mode_get,
1469         .flow_ctrl_get = cnxk_nix_flow_ctrl_get,
1470         .flow_ctrl_set = cnxk_nix_flow_ctrl_set,
1471         .dev_set_link_up = cnxk_nix_set_link_up,
1472         .dev_set_link_down = cnxk_nix_set_link_down,
1473         .get_module_info = cnxk_nix_get_module_info,
1474         .get_module_eeprom = cnxk_nix_get_module_eeprom,
1475         .rx_queue_intr_enable = cnxk_nix_rx_queue_intr_enable,
1476         .rx_queue_intr_disable = cnxk_nix_rx_queue_intr_disable,
1477         .pool_ops_supported = cnxk_nix_pool_ops_supported,
1478         .queue_stats_mapping_set = cnxk_nix_queue_stats_mapping,
1479         .stats_get = cnxk_nix_stats_get,
1480         .stats_reset = cnxk_nix_stats_reset,
1481         .xstats_get = cnxk_nix_xstats_get,
1482         .xstats_get_names = cnxk_nix_xstats_get_names,
1483         .xstats_reset = cnxk_nix_xstats_reset,
1484         .xstats_get_by_id = cnxk_nix_xstats_get_by_id,
1485         .xstats_get_names_by_id = cnxk_nix_xstats_get_names_by_id,
1486         .fw_version_get = cnxk_nix_fw_version_get,
1487         .rxq_info_get = cnxk_nix_rxq_info_get,
1488         .txq_info_get = cnxk_nix_txq_info_get,
1489         .tx_done_cleanup = cnxk_nix_tx_done_cleanup,
1490         .flow_ops_get = cnxk_nix_flow_ops_get,
1491         .get_reg = cnxk_nix_dev_get_reg,
1492         .timesync_read_rx_timestamp = cnxk_nix_timesync_read_rx_timestamp,
1493         .timesync_read_tx_timestamp = cnxk_nix_timesync_read_tx_timestamp,
1494         .timesync_read_time = cnxk_nix_timesync_read_time,
1495         .timesync_write_time = cnxk_nix_timesync_write_time,
1496         .timesync_adjust_time = cnxk_nix_timesync_adjust_time,
1497         .read_clock = cnxk_nix_read_clock,
1498         .reta_update = cnxk_nix_reta_update,
1499         .reta_query = cnxk_nix_reta_query,
1500         .rss_hash_update = cnxk_nix_rss_hash_update,
1501         .rss_hash_conf_get = cnxk_nix_rss_hash_conf_get,
1502         .set_mc_addr_list = cnxk_nix_mc_addr_list_configure,
1503         .set_queue_rate_limit = cnxk_nix_tm_set_queue_rate_limit,
1504         .tm_ops_get = cnxk_nix_tm_ops_get,
1505         .mtr_ops_get = cnxk_nix_mtr_ops_get,
1506 };
1507
1508 static int
1509 cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)
1510 {
1511         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1512         struct rte_security_ctx *sec_ctx;
1513         struct roc_nix *nix = &dev->nix;
1514         struct rte_pci_device *pci_dev;
1515         int rc, max_entries;
1516
1517         eth_dev->dev_ops = &cnxk_eth_dev_ops;
1518
1519         /* Alloc security context */
1520         sec_ctx = plt_zmalloc(sizeof(struct rte_security_ctx), 0);
1521         if (!sec_ctx)
1522                 return -ENOMEM;
1523         sec_ctx->device = eth_dev;
1524         sec_ctx->ops = &cnxk_eth_sec_ops;
1525         sec_ctx->flags =
1526                 (RTE_SEC_CTX_F_FAST_SET_MDATA | RTE_SEC_CTX_F_FAST_GET_UDATA);
1527         eth_dev->security_ctx = sec_ctx;
1528         TAILQ_INIT(&dev->inb.list);
1529         TAILQ_INIT(&dev->outb.list);
1530
1531         /* For secondary processes, the primary has done all the work */
1532         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1533                 return 0;
1534
1535         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1536         rte_eth_copy_pci_info(eth_dev, pci_dev);
1537
1538         /* Parse devargs string */
1539         rc = cnxk_ethdev_parse_devargs(eth_dev->device->devargs, dev);
1540         if (rc) {
1541                 plt_err("Failed to parse devargs rc=%d", rc);
1542                 goto error;
1543         }
1544
1545         /* Initialize base roc nix */
1546         nix->pci_dev = pci_dev;
1547         nix->hw_vlan_ins = true;
1548         rc = roc_nix_dev_init(nix);
1549         if (rc) {
1550                 plt_err("Failed to initialize roc nix rc=%d", rc);
1551                 goto error;
1552         }
1553
1554         /* Register up msg callbacks */
1555         roc_nix_mac_link_cb_register(nix, cnxk_eth_dev_link_status_cb);
1556
1557         /* Register up msg callbacks */
1558         roc_nix_mac_link_info_get_cb_register(nix,
1559                                               cnxk_eth_dev_link_status_get_cb);
1560
1561         dev->eth_dev = eth_dev;
1562         dev->configured = 0;
1563         dev->ptype_disable = 0;
1564
1565         /* For vfs, returned max_entries will be 0. but to keep default mac
1566          * address, one entry must be allocated. so setting up to 1.
1567          */
1568         if (roc_nix_is_vf_or_sdp(nix))
1569                 max_entries = 1;
1570         else
1571                 max_entries = roc_nix_mac_max_entries_get(nix);
1572
1573         if (max_entries <= 0) {
1574                 plt_err("Failed to get max entries for mac addr");
1575                 rc = -ENOTSUP;
1576                 goto dev_fini;
1577         }
1578
1579         eth_dev->data->mac_addrs =
1580                 rte_zmalloc("mac_addr", max_entries * RTE_ETHER_ADDR_LEN, 0);
1581         if (eth_dev->data->mac_addrs == NULL) {
1582                 plt_err("Failed to allocate memory for mac addr");
1583                 rc = -ENOMEM;
1584                 goto dev_fini;
1585         }
1586
1587         dev->max_mac_entries = max_entries;
1588         dev->dmac_filter_count = 1;
1589
1590         /* Get mac address */
1591         rc = roc_nix_npc_mac_addr_get(nix, dev->mac_addr);
1592         if (rc) {
1593                 plt_err("Failed to get mac addr, rc=%d", rc);
1594                 goto free_mac_addrs;
1595         }
1596
1597         /* Update the mac address */
1598         memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1599
1600         if (!roc_nix_is_vf_or_sdp(nix)) {
1601                 /* Sync same MAC address to CGX/RPM table */
1602                 rc = roc_nix_mac_addr_set(nix, dev->mac_addr);
1603                 if (rc) {
1604                         plt_err("Failed to set mac addr, rc=%d", rc);
1605                         goto free_mac_addrs;
1606                 }
1607         }
1608
1609         /* Union of all capabilities supported by CNXK.
1610          * Platform specific capabilities will be
1611          * updated later.
1612          */
1613         dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
1614         dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
1615         dev->speed_capa = nix_get_speed_capa(dev);
1616
1617         /* Initialize roc npc */
1618         dev->npc.roc_nix = nix;
1619         rc = roc_npc_init(&dev->npc);
1620         if (rc)
1621                 goto free_mac_addrs;
1622
1623         plt_nix_dbg("Port=%d pf=%d vf=%d ver=%s hwcap=0x%" PRIx64
1624                     " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
1625                     eth_dev->data->port_id, roc_nix_get_pf(nix),
1626                     roc_nix_get_vf(nix), CNXK_ETH_DEV_PMD_VERSION, dev->hwcap,
1627                     dev->rx_offload_capa, dev->tx_offload_capa);
1628         return 0;
1629
1630 free_mac_addrs:
1631         rte_free(eth_dev->data->mac_addrs);
1632 dev_fini:
1633         roc_nix_dev_fini(nix);
1634 error:
1635         plt_err("Failed to init nix eth_dev rc=%d", rc);
1636         return rc;
1637 }
1638
1639 static int
1640 cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool reset)
1641 {
1642         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1643         const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
1644         struct roc_nix *nix = &dev->nix;
1645         int rc, i;
1646
1647         plt_free(eth_dev->security_ctx);
1648         eth_dev->security_ctx = NULL;
1649
1650         /* Nothing to be done for secondary processes */
1651         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1652                 return 0;
1653
1654         /* Clear the flag since we are closing down */
1655         dev->configured = 0;
1656
1657         roc_nix_npc_rx_ena_dis(nix, false);
1658
1659         /* Disable and free rte_flow entries */
1660         roc_npc_fini(&dev->npc);
1661
1662         /* Disable link status events */
1663         roc_nix_mac_link_event_start_stop(nix, false);
1664
1665         /* Unregister the link update op, this is required to stop VFs from
1666          * receiving link status updates on exit path.
1667          */
1668         roc_nix_mac_link_cb_unregister(nix);
1669
1670         /* Free up SQs */
1671         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1672                 dev_ops->tx_queue_release(eth_dev, i);
1673                 eth_dev->data->tx_queues[i] = NULL;
1674         }
1675         eth_dev->data->nb_tx_queues = 0;
1676
1677         /* Free up RQ's and CQ's */
1678         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1679                 dev_ops->rx_queue_release(eth_dev, i);
1680                 eth_dev->data->rx_queues[i] = NULL;
1681         }
1682         eth_dev->data->nb_rx_queues = 0;
1683
1684         /* Free security resources */
1685         nix_security_release(dev);
1686
1687         /* Free tm resources */
1688         roc_nix_tm_fini(nix);
1689
1690         /* Unregister queue irqs */
1691         roc_nix_unregister_queue_irqs(nix);
1692
1693         /* Unregister cq irqs */
1694         if (eth_dev->data->dev_conf.intr_conf.rxq)
1695                 roc_nix_unregister_cq_irqs(nix);
1696
1697         /* Free ROC RQ's, SQ's and CQ's memory */
1698         nix_free_queue_mem(dev);
1699
1700         /* Free nix lf resources */
1701         rc = roc_nix_lf_free(nix);
1702         if (rc)
1703                 plt_err("Failed to free nix lf, rc=%d", rc);
1704
1705         rte_free(eth_dev->data->mac_addrs);
1706         eth_dev->data->mac_addrs = NULL;
1707
1708         rc = roc_nix_dev_fini(nix);
1709         /* Can be freed later by PMD if NPA LF is in use */
1710         if (rc == -EAGAIN) {
1711                 if (!reset)
1712                         eth_dev->data->dev_private = NULL;
1713                 return 0;
1714         } else if (rc) {
1715                 plt_err("Failed in nix dev fini, rc=%d", rc);
1716         }
1717
1718         return rc;
1719 }
1720
1721 static int
1722 cnxk_nix_dev_close(struct rte_eth_dev *eth_dev)
1723 {
1724         cnxk_eth_dev_uninit(eth_dev, false);
1725         return 0;
1726 }
1727
1728 static int
1729 cnxk_nix_dev_reset(struct rte_eth_dev *eth_dev)
1730 {
1731         int rc;
1732
1733         rc = cnxk_eth_dev_uninit(eth_dev, true);
1734         if (rc)
1735                 return rc;
1736
1737         return cnxk_eth_dev_init(eth_dev);
1738 }
1739
1740 int
1741 cnxk_nix_remove(struct rte_pci_device *pci_dev)
1742 {
1743         struct rte_eth_dev *eth_dev;
1744         struct roc_nix *nix;
1745         int rc = -EINVAL;
1746
1747         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
1748         if (eth_dev) {
1749                 /* Cleanup eth dev */
1750                 rc = cnxk_eth_dev_uninit(eth_dev, false);
1751                 if (rc)
1752                         return rc;
1753
1754                 rte_eth_dev_release_port(eth_dev);
1755         }
1756
1757         /* Nothing to be done for secondary processes */
1758         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1759                 return 0;
1760
1761         /* Check if this device is hosting common resource */
1762         nix = roc_idev_npa_nix_get();
1763         if (nix->pci_dev != pci_dev)
1764                 return 0;
1765
1766         /* Try nix fini now */
1767         rc = roc_nix_dev_fini(nix);
1768         if (rc == -EAGAIN) {
1769                 plt_info("%s: common resource in use by other devices",
1770                          pci_dev->name);
1771                 goto exit;
1772         } else if (rc) {
1773                 plt_err("Failed in nix dev fini, rc=%d", rc);
1774                 goto exit;
1775         }
1776
1777         /* Free device pointer as rte_ethdev does not have it anymore */
1778         rte_free(nix);
1779 exit:
1780         return rc;
1781 }
1782
1783 int
1784 cnxk_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1785 {
1786         int rc;
1787
1788         RTE_SET_USED(pci_drv);
1789
1790         rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct cnxk_eth_dev),
1791                                            cnxk_eth_dev_init);
1792
1793         /* On error on secondary, recheck if port exists in primary or
1794          * in mid of detach state.
1795          */
1796         if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
1797                 if (!rte_eth_dev_allocated(pci_dev->device.name))
1798                         return 0;
1799         return rc;
1800 }