1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
4 #include <cnxk_ethdev.h>
6 #include <rte_eventdev.h>
9 nix_get_rx_offload_capa(struct cnxk_eth_dev *dev)
11 uint64_t capa = CNXK_NIX_RX_OFFLOAD_CAPA;
13 if (roc_nix_is_vf_or_sdp(&dev->nix) ||
14 dev->npc.switch_header_type == ROC_PRIV_FLAGS_HIGIG)
15 capa &= ~RTE_ETH_RX_OFFLOAD_TIMESTAMP;
20 static inline uint64_t
21 nix_get_tx_offload_capa(struct cnxk_eth_dev *dev)
24 return CNXK_NIX_TX_OFFLOAD_CAPA;
27 static inline uint32_t
28 nix_get_speed_capa(struct cnxk_eth_dev *dev)
32 /* Auto negotiation disabled */
33 speed_capa = RTE_ETH_LINK_SPEED_FIXED;
34 if (!roc_nix_is_vf_or_sdp(&dev->nix) && !roc_nix_is_lbk(&dev->nix)) {
35 speed_capa |= RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G |
36 RTE_ETH_LINK_SPEED_25G | RTE_ETH_LINK_SPEED_40G |
37 RTE_ETH_LINK_SPEED_50G | RTE_ETH_LINK_SPEED_100G;
44 cnxk_nix_inb_mode_set(struct cnxk_eth_dev *dev, bool use_inl_dev)
46 struct roc_nix *nix = &dev->nix;
48 if (dev->inb.inl_dev == use_inl_dev)
51 plt_nix_dbg("Security sessions(%u) still active, inl=%u!!!",
52 dev->inb.nb_sess, !!dev->inb.inl_dev);
55 dev->inb.inl_dev = use_inl_dev;
57 /* Update RoC for NPC rule insertion */
58 roc_nix_inb_mode_set(nix, use_inl_dev);
60 /* Setup lookup mem */
61 return cnxk_nix_lookup_mem_sa_base_set(dev);
65 nix_security_setup(struct cnxk_eth_dev *dev)
67 struct roc_nix *nix = &dev->nix;
70 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
71 /* Setup Inline Inbound */
72 rc = roc_nix_inl_inb_init(nix);
74 plt_err("Failed to initialize nix inline inb, rc=%d",
79 /* By default pick using inline device for poll mode.
80 * Will be overridden when event mode rq's are setup.
82 cnxk_nix_inb_mode_set(dev, true);
84 /* Allocate memory to be used as dptr for CPT ucode
88 plt_zmalloc(ROC_NIX_INL_OT_IPSEC_INB_HW_SZ, 0);
89 if (!dev->inb.sa_dptr) {
90 plt_err("Couldn't allocate memory for SA dptr");
96 if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY ||
97 dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
98 struct plt_bitmap *bmap;
102 /* Setup enough descriptors for all tx queues */
103 nix->outb_nb_desc = dev->outb.nb_desc;
104 nix->outb_nb_crypto_qs = dev->outb.nb_crypto_qs;
106 /* Setup Inline Outbound */
107 rc = roc_nix_inl_outb_init(nix);
109 plt_err("Failed to initialize nix inline outb, rc=%d",
114 dev->outb.lf_base = roc_nix_inl_outb_lf_base_get(nix);
116 /* Skip the rest if DEV_TX_OFFLOAD_SECURITY is not enabled */
117 if (!(dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY))
120 /* Allocate memory to be used as dptr for CPT ucode
124 plt_zmalloc(ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ, 0);
125 if (!dev->outb.sa_dptr) {
126 plt_err("Couldn't allocate memory for SA dptr");
132 /* Allocate a bitmap to alloc and free sa indexes */
133 bmap_sz = plt_bitmap_get_memory_footprint(dev->outb.max_sa);
134 mem = plt_zmalloc(bmap_sz, PLT_CACHE_LINE_SIZE);
136 plt_err("Outbound SA bmap alloc failed");
138 rc |= roc_nix_inl_outb_fini(nix);
143 bmap = plt_bitmap_init(dev->outb.max_sa, mem, bmap_sz);
145 plt_err("Outbound SA bmap init failed");
147 rc |= roc_nix_inl_outb_fini(nix);
152 for (i = 0; i < dev->outb.max_sa; i++)
153 plt_bitmap_set(bmap, i);
155 dev->outb.sa_base = roc_nix_inl_outb_sa_base_get(nix);
156 dev->outb.sa_bmap_mem = mem;
157 dev->outb.sa_bmap = bmap;
162 if (dev->inb.sa_dptr)
163 plt_free(dev->inb.sa_dptr);
164 if (dev->outb.sa_dptr)
165 plt_free(dev->outb.sa_dptr);
167 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)
168 rc |= roc_nix_inl_inb_fini(nix);
173 nix_meter_fini(struct cnxk_eth_dev *dev)
175 struct cnxk_meter_node *next_mtr = NULL;
176 struct roc_nix_bpf_objs profs = {0};
177 struct cnxk_meter_node *mtr = NULL;
178 struct cnxk_mtr *fms = &dev->mtr;
179 struct roc_nix *nix = &dev->nix;
180 struct roc_nix_rq *rq;
184 RTE_TAILQ_FOREACH_SAFE(mtr, fms, next, next_mtr) {
185 for (i = 0; i < mtr->rq_num; i++) {
186 rq = &dev->rqs[mtr->rq_id[i]];
187 rc |= roc_nix_bpf_ena_dis(nix, mtr->bpf_id, rq, false);
190 profs.level = mtr->level;
192 profs.ids[0] = mtr->bpf_id;
193 rc = roc_nix_bpf_free(nix, &profs, 1);
198 TAILQ_REMOVE(fms, mtr, next);
205 nix_security_release(struct cnxk_eth_dev *dev)
207 struct rte_eth_dev *eth_dev = dev->eth_dev;
208 struct cnxk_eth_sec_sess *eth_sec, *tvar;
209 struct roc_nix *nix = &dev->nix;
212 /* Cleanup Inline inbound */
213 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
214 /* Destroy inbound sessions */
216 RTE_TAILQ_FOREACH_SAFE(eth_sec, &dev->inb.list, entry, tvar)
217 cnxk_eth_sec_ops.session_destroy(eth_dev,
220 /* Clear lookup mem */
221 cnxk_nix_lookup_mem_sa_base_clear(dev);
223 rc = roc_nix_inl_inb_fini(nix);
225 plt_err("Failed to cleanup nix inline inb, rc=%d", rc);
228 if (dev->inb.sa_dptr) {
229 plt_free(dev->inb.sa_dptr);
230 dev->inb.sa_dptr = NULL;
234 /* Cleanup Inline outbound */
235 if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY ||
236 dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
237 /* Destroy outbound sessions */
239 RTE_TAILQ_FOREACH_SAFE(eth_sec, &dev->outb.list, entry, tvar)
240 cnxk_eth_sec_ops.session_destroy(eth_dev,
243 rc = roc_nix_inl_outb_fini(nix);
245 plt_err("Failed to cleanup nix inline outb, rc=%d", rc);
248 plt_bitmap_free(dev->outb.sa_bmap);
249 plt_free(dev->outb.sa_bmap_mem);
250 dev->outb.sa_bmap = NULL;
251 dev->outb.sa_bmap_mem = NULL;
252 if (dev->outb.sa_dptr) {
253 plt_free(dev->outb.sa_dptr);
254 dev->outb.sa_dptr = NULL;
258 dev->inb.inl_dev = false;
259 roc_nix_inb_mode_set(nix, false);
261 dev->inb.nb_sess = 0;
262 dev->outb.nb_sess = 0;
267 nix_enable_mseg_on_jumbo(struct cnxk_eth_rxq_sp *rxq)
269 struct rte_pktmbuf_pool_private *mbp_priv;
270 struct rte_eth_dev *eth_dev;
271 struct cnxk_eth_dev *dev;
275 eth_dev = dev->eth_dev;
277 /* Get rx buffer size */
278 mbp_priv = rte_mempool_get_priv(rxq->qconf.mp);
279 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
281 if (eth_dev->data->mtu + (uint32_t)CNXK_NIX_L2_OVERHEAD > buffsz) {
282 dev->rx_offloads |= RTE_ETH_RX_OFFLOAD_SCATTER;
283 dev->tx_offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
288 nix_recalc_mtu(struct rte_eth_dev *eth_dev)
290 struct rte_eth_dev_data *data = eth_dev->data;
291 struct cnxk_eth_rxq_sp *rxq;
294 rxq = ((struct cnxk_eth_rxq_sp *)data->rx_queues[0]) - 1;
295 /* Setup scatter mode if needed by jumbo */
296 nix_enable_mseg_on_jumbo(rxq);
298 rc = cnxk_nix_mtu_set(eth_dev, data->mtu);
300 plt_err("Failed to set default MTU size, rc=%d", rc);
306 nix_init_flow_ctrl_config(struct rte_eth_dev *eth_dev)
308 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
309 struct cnxk_fc_cfg *fc = &dev->fc_cfg;
310 struct rte_eth_fc_conf fc_conf = {0};
313 /* Both Rx & Tx flow ctrl get enabled(RTE_ETH_FC_FULL) in HW
314 * by AF driver, update those info in PMD structure.
316 rc = cnxk_nix_flow_ctrl_get(eth_dev, &fc_conf);
320 fc->mode = fc_conf.mode;
321 fc->rx_pause = (fc_conf.mode == RTE_ETH_FC_FULL) ||
322 (fc_conf.mode == RTE_ETH_FC_RX_PAUSE);
323 fc->tx_pause = (fc_conf.mode == RTE_ETH_FC_FULL) ||
324 (fc_conf.mode == RTE_ETH_FC_TX_PAUSE);
331 nix_update_flow_ctrl_config(struct rte_eth_dev *eth_dev)
333 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
334 struct cnxk_fc_cfg *fc = &dev->fc_cfg;
335 struct rte_eth_fc_conf fc_cfg = {0};
337 if (roc_nix_is_vf_or_sdp(&dev->nix) && !roc_nix_is_lbk(&dev->nix))
340 fc_cfg.mode = fc->mode;
342 /* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */
343 if (roc_model_is_cn96_ax() &&
344 dev->npc.switch_header_type != ROC_PRIV_FLAGS_HIGIG &&
345 (fc_cfg.mode == RTE_ETH_FC_FULL || fc_cfg.mode == RTE_ETH_FC_RX_PAUSE)) {
347 (fc_cfg.mode == RTE_ETH_FC_FULL ||
348 fc_cfg.mode == RTE_ETH_FC_TX_PAUSE) ?
349 RTE_ETH_FC_TX_PAUSE : RTE_ETH_FC_NONE;
352 return cnxk_nix_flow_ctrl_set(eth_dev, &fc_cfg);
356 cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev)
358 uint16_t port_id = dev->eth_dev->data->port_id;
359 struct rte_mbuf mb_def;
362 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
363 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
364 offsetof(struct rte_mbuf, data_off) !=
366 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
367 offsetof(struct rte_mbuf, data_off) !=
369 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
370 offsetof(struct rte_mbuf, data_off) !=
373 mb_def.data_off = RTE_PKTMBUF_HEADROOM +
374 (dev->ptp_en * CNXK_NIX_TIMESYNC_RX_OFFSET);
375 mb_def.port = port_id;
376 rte_mbuf_refcnt_set(&mb_def, 1);
378 /* Prevent compiler reordering: rearm_data covers previous fields */
379 rte_compiler_barrier();
380 tmp = (uint64_t *)&mb_def.rearm_data;
385 static inline uint8_t
386 nix_sq_max_sqe_sz(struct cnxk_eth_dev *dev)
389 * Maximum three segments can be supported with W8, Choose
390 * NIX_MAXSQESZ_W16 for multi segment offload.
392 if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_MULTI_SEGS)
393 return NIX_MAXSQESZ_W16;
395 return NIX_MAXSQESZ_W8;
399 cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
400 uint16_t nb_desc, uint16_t fp_tx_q_sz,
401 const struct rte_eth_txconf *tx_conf)
403 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
404 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
405 struct cnxk_eth_txq_sp *txq_sp;
406 struct roc_nix_sq *sq;
410 /* Free memory prior to re-allocation if needed. */
411 if (eth_dev->data->tx_queues[qid] != NULL) {
412 plt_nix_dbg("Freeing memory prior to re-allocation %d", qid);
413 dev_ops->tx_queue_release(eth_dev, qid);
414 eth_dev->data->tx_queues[qid] = NULL;
417 /* When Tx Security offload is enabled, increase tx desc count by
418 * max possible outbound desc count.
420 if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY)
421 nb_desc += dev->outb.nb_desc;
426 sq->nb_desc = nb_desc;
427 sq->max_sqe_sz = nix_sq_max_sqe_sz(dev);
429 rc = roc_nix_sq_init(&dev->nix, sq);
431 plt_err("Failed to init sq=%d, rc=%d", qid, rc);
436 txq_sz = sizeof(struct cnxk_eth_txq_sp) + fp_tx_q_sz;
437 txq_sp = plt_zmalloc(txq_sz, PLT_CACHE_LINE_SIZE);
439 plt_err("Failed to alloc tx queue mem");
440 rc |= roc_nix_sq_fini(sq);
446 txq_sp->qconf.conf.tx = *tx_conf;
447 /* Queue config should reflect global offloads */
448 txq_sp->qconf.conf.tx.offloads = dev->tx_offloads;
449 txq_sp->qconf.nb_desc = nb_desc;
451 plt_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " lmt_addr=%p"
452 " nb_sqb_bufs=%d sqes_per_sqb_log2=%d",
453 qid, sq->fc, dev->tx_offloads, sq->lmt_addr,
454 sq->nb_sqb_bufs, sq->sqes_per_sqb_log2);
456 /* Store start of fast path area */
457 eth_dev->data->tx_queues[qid] = txq_sp + 1;
458 eth_dev->data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
463 cnxk_nix_tx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)
465 void *txq = eth_dev->data->tx_queues[qid];
466 struct cnxk_eth_txq_sp *txq_sp;
467 struct cnxk_eth_dev *dev;
468 struct roc_nix_sq *sq;
474 txq_sp = cnxk_eth_txq_to_sp(txq);
478 plt_nix_dbg("Releasing txq %u", qid);
482 rc = roc_nix_sq_fini(sq);
484 plt_err("Failed to cleanup sq, rc=%d", rc);
491 cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
492 uint16_t nb_desc, uint16_t fp_rx_q_sz,
493 const struct rte_eth_rxconf *rx_conf,
494 struct rte_mempool *mp)
496 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
497 struct roc_nix *nix = &dev->nix;
498 struct cnxk_eth_rxq_sp *rxq_sp;
499 struct rte_mempool_ops *ops;
500 const char *platform_ops;
501 struct roc_nix_rq *rq;
502 struct roc_nix_cq *cq;
508 if (rx_conf->rx_deferred_start == 1) {
509 plt_err("Deferred Rx start is not supported");
513 platform_ops = rte_mbuf_platform_mempool_ops();
514 /* This driver needs cnxk_npa mempool ops to work */
515 ops = rte_mempool_get_ops(mp->ops_index);
516 if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
517 plt_err("mempool ops should be of cnxk_npa type");
521 if (mp->pool_id == 0) {
522 plt_err("Invalid pool_id");
526 /* Free memory prior to re-allocation if needed */
527 if (eth_dev->data->rx_queues[qid] != NULL) {
528 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
530 plt_nix_dbg("Freeing memory prior to re-allocation %d", qid);
531 dev_ops->rx_queue_release(eth_dev, qid);
532 eth_dev->data->rx_queues[qid] = NULL;
535 /* Clam up cq limit to size of packet pool aura for LBK
536 * to avoid meta packet drop as LBK does not currently support
539 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY && roc_nix_is_lbk(nix)) {
540 uint64_t pkt_pool_limit = roc_nix_inl_dev_rq_limit_get();
542 /* Use current RQ's aura limit if inl rq is not available */
544 pkt_pool_limit = roc_npa_aura_op_limit_get(mp->pool_id);
545 nb_desc = RTE_MAX(nb_desc, pkt_pool_limit);
548 /* Its a no-op when inline device is not used */
549 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY ||
550 dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY)
551 roc_nix_inl_dev_xaq_realloc(mp->pool_id);
556 cq->nb_desc = nb_desc;
557 rc = roc_nix_cq_init(&dev->nix, cq);
559 plt_err("Failed to init roc cq for rq=%d, rc=%d", qid, rc);
566 rq->aura_handle = mp->pool_id;
567 rq->flow_tag_width = 32;
570 /* Calculate first mbuf skip */
571 first_skip = (sizeof(struct rte_mbuf));
572 first_skip += RTE_PKTMBUF_HEADROOM;
573 first_skip += rte_pktmbuf_priv_size(mp);
574 rq->first_skip = first_skip;
575 rq->later_skip = sizeof(struct rte_mbuf);
576 rq->lpb_size = mp->elt_size;
577 rq->lpb_drop_ena = !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY);
579 /* Enable Inline IPSec on RQ, will not be used for Poll mode */
580 if (roc_nix_inl_inb_is_enabled(nix))
581 rq->ipsech_ena = true;
583 rc = roc_nix_rq_init(&dev->nix, rq, !!eth_dev->data->dev_started);
585 plt_err("Failed to init roc rq for rq=%d, rc=%d", qid, rc);
589 /* Allocate and setup fast path rx queue */
591 rxq_sz = sizeof(struct cnxk_eth_rxq_sp) + fp_rx_q_sz;
592 rxq_sp = plt_zmalloc(rxq_sz, PLT_CACHE_LINE_SIZE);
594 plt_err("Failed to alloc rx queue for rq=%d", qid);
598 /* Setup slow path fields */
601 rxq_sp->qconf.conf.rx = *rx_conf;
602 /* Queue config should reflect global offloads */
603 rxq_sp->qconf.conf.rx.offloads = dev->rx_offloads;
604 rxq_sp->qconf.nb_desc = nb_desc;
605 rxq_sp->qconf.mp = mp;
607 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
608 /* Pass a tagmask used to handle error packets in inline device.
609 * Ethdev rq's tag_mask field will be overwritten later
613 0x0FF00000 | ((uint32_t)RTE_EVENT_TYPE_ETHDEV << 28);
615 /* Setup rq reference for inline dev if present */
616 rc = roc_nix_inl_dev_rq_get(rq);
621 plt_nix_dbg("rq=%d pool=%s nb_desc=%d->%d", qid, mp->name, nb_desc,
624 /* Store start of fast path area */
625 eth_dev->data->rx_queues[qid] = rxq_sp + 1;
626 eth_dev->data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
628 /* Calculating delta and freq mult between PTP HI clock and tsc.
629 * These are needed in deriving raw clock value from tsc counter.
630 * read_clock eth op returns raw clock value.
632 if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) || dev->ptp_en) {
633 rc = cnxk_nix_tsc_convert(dev);
635 plt_err("Failed to calculate delta and freq mult");
644 rc |= roc_nix_rq_fini(rq);
646 rc |= roc_nix_cq_fini(cq);
652 cnxk_nix_rx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)
654 void *rxq = eth_dev->data->rx_queues[qid];
655 struct cnxk_eth_rxq_sp *rxq_sp;
656 struct cnxk_eth_dev *dev;
657 struct roc_nix_rq *rq;
658 struct roc_nix_cq *cq;
664 rxq_sp = cnxk_eth_rxq_to_sp(rxq);
668 plt_nix_dbg("Releasing rxq %u", qid);
670 /* Release rq reference for inline dev if present */
671 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)
672 roc_nix_inl_dev_rq_put(rq);
675 rc = roc_nix_rq_fini(rq);
677 plt_err("Failed to cleanup rq, rc=%d", rc);
681 rc = roc_nix_cq_fini(cq);
683 plt_err("Failed to cleanup cq, rc=%d", rc);
685 /* Finally free fast path area */
690 cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
693 uint32_t flow_key_type[RSS_MAX_LEVELS][6] = {
694 {FLOW_KEY_TYPE_IPV4, FLOW_KEY_TYPE_IPV6, FLOW_KEY_TYPE_TCP,
695 FLOW_KEY_TYPE_UDP, FLOW_KEY_TYPE_SCTP, FLOW_KEY_TYPE_ETH_DMAC},
696 {FLOW_KEY_TYPE_INNR_IPV4, FLOW_KEY_TYPE_INNR_IPV6,
697 FLOW_KEY_TYPE_INNR_TCP, FLOW_KEY_TYPE_INNR_UDP,
698 FLOW_KEY_TYPE_INNR_SCTP, FLOW_KEY_TYPE_INNR_ETH_DMAC},
699 {FLOW_KEY_TYPE_IPV4 | FLOW_KEY_TYPE_INNR_IPV4,
700 FLOW_KEY_TYPE_IPV6 | FLOW_KEY_TYPE_INNR_IPV6,
701 FLOW_KEY_TYPE_TCP | FLOW_KEY_TYPE_INNR_TCP,
702 FLOW_KEY_TYPE_UDP | FLOW_KEY_TYPE_INNR_UDP,
703 FLOW_KEY_TYPE_SCTP | FLOW_KEY_TYPE_INNR_SCTP,
704 FLOW_KEY_TYPE_ETH_DMAC | FLOW_KEY_TYPE_INNR_ETH_DMAC}
706 uint32_t flowkey_cfg = 0;
708 dev->ethdev_rss_hf = ethdev_rss;
710 if (ethdev_rss & RTE_ETH_RSS_L2_PAYLOAD &&
711 dev->npc.switch_header_type == ROC_PRIV_FLAGS_LEN_90B) {
712 flowkey_cfg |= FLOW_KEY_TYPE_CH_LEN_90B;
715 if (ethdev_rss & RTE_ETH_RSS_C_VLAN)
716 flowkey_cfg |= FLOW_KEY_TYPE_VLAN;
718 if (ethdev_rss & RTE_ETH_RSS_L3_SRC_ONLY)
719 flowkey_cfg |= FLOW_KEY_TYPE_L3_SRC;
721 if (ethdev_rss & RTE_ETH_RSS_L3_DST_ONLY)
722 flowkey_cfg |= FLOW_KEY_TYPE_L3_DST;
724 if (ethdev_rss & RTE_ETH_RSS_L4_SRC_ONLY)
725 flowkey_cfg |= FLOW_KEY_TYPE_L4_SRC;
727 if (ethdev_rss & RTE_ETH_RSS_L4_DST_ONLY)
728 flowkey_cfg |= FLOW_KEY_TYPE_L4_DST;
730 if (ethdev_rss & RSS_IPV4_ENABLE)
731 flowkey_cfg |= flow_key_type[rss_level][RSS_IPV4_INDEX];
733 if (ethdev_rss & RSS_IPV6_ENABLE)
734 flowkey_cfg |= flow_key_type[rss_level][RSS_IPV6_INDEX];
736 if (ethdev_rss & RTE_ETH_RSS_TCP)
737 flowkey_cfg |= flow_key_type[rss_level][RSS_TCP_INDEX];
739 if (ethdev_rss & RTE_ETH_RSS_UDP)
740 flowkey_cfg |= flow_key_type[rss_level][RSS_UDP_INDEX];
742 if (ethdev_rss & RTE_ETH_RSS_SCTP)
743 flowkey_cfg |= flow_key_type[rss_level][RSS_SCTP_INDEX];
745 if (ethdev_rss & RTE_ETH_RSS_L2_PAYLOAD)
746 flowkey_cfg |= flow_key_type[rss_level][RSS_DMAC_INDEX];
748 if (ethdev_rss & RSS_IPV6_EX_ENABLE)
749 flowkey_cfg |= FLOW_KEY_TYPE_IPV6_EXT;
751 if (ethdev_rss & RTE_ETH_RSS_PORT)
752 flowkey_cfg |= FLOW_KEY_TYPE_PORT;
754 if (ethdev_rss & RTE_ETH_RSS_NVGRE)
755 flowkey_cfg |= FLOW_KEY_TYPE_NVGRE;
757 if (ethdev_rss & RTE_ETH_RSS_VXLAN)
758 flowkey_cfg |= FLOW_KEY_TYPE_VXLAN;
760 if (ethdev_rss & RTE_ETH_RSS_GENEVE)
761 flowkey_cfg |= FLOW_KEY_TYPE_GENEVE;
763 if (ethdev_rss & RTE_ETH_RSS_GTPU)
764 flowkey_cfg |= FLOW_KEY_TYPE_GTPU;
770 nix_free_queue_mem(struct cnxk_eth_dev *dev)
781 nix_ingress_policer_setup(struct cnxk_eth_dev *dev)
783 struct rte_eth_dev *eth_dev = dev->eth_dev;
786 TAILQ_INIT(&dev->mtr_profiles);
787 TAILQ_INIT(&dev->mtr_policy);
788 TAILQ_INIT(&dev->mtr);
790 if (eth_dev->dev_ops->mtr_ops_get == NULL)
793 return nix_mtr_capabilities_init(eth_dev);
797 nix_rss_default_setup(struct cnxk_eth_dev *dev)
799 struct rte_eth_dev *eth_dev = dev->eth_dev;
800 uint8_t rss_hash_level;
801 uint32_t flowkey_cfg;
804 rss_hf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
805 rss_hash_level = RTE_ETH_RSS_LEVEL(rss_hf);
809 flowkey_cfg = cnxk_rss_ethdev_to_nix(dev, rss_hf, rss_hash_level);
810 return roc_nix_rss_default_setup(&dev->nix, flowkey_cfg);
814 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
816 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
817 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
818 struct cnxk_eth_qconf *tx_qconf = NULL;
819 struct cnxk_eth_qconf *rx_qconf = NULL;
820 struct cnxk_eth_rxq_sp *rxq_sp;
821 struct cnxk_eth_txq_sp *txq_sp;
822 int i, nb_rxq, nb_txq;
825 nb_rxq = RTE_MIN(dev->nb_rxq, eth_dev->data->nb_rx_queues);
826 nb_txq = RTE_MIN(dev->nb_txq, eth_dev->data->nb_tx_queues);
828 tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
829 if (tx_qconf == NULL) {
830 plt_err("Failed to allocate memory for tx_qconf");
834 rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
835 if (rx_qconf == NULL) {
836 plt_err("Failed to allocate memory for rx_qconf");
840 txq = eth_dev->data->tx_queues;
841 for (i = 0; i < nb_txq; i++) {
842 if (txq[i] == NULL) {
843 tx_qconf[i].valid = false;
844 plt_info("txq[%d] is already released", i);
847 txq_sp = cnxk_eth_txq_to_sp(txq[i]);
848 memcpy(&tx_qconf[i], &txq_sp->qconf, sizeof(*tx_qconf));
849 tx_qconf[i].valid = true;
850 dev_ops->tx_queue_release(eth_dev, i);
851 eth_dev->data->tx_queues[i] = NULL;
854 rxq = eth_dev->data->rx_queues;
855 for (i = 0; i < nb_rxq; i++) {
856 if (rxq[i] == NULL) {
857 rx_qconf[i].valid = false;
858 plt_info("rxq[%d] is already released", i);
861 rxq_sp = cnxk_eth_rxq_to_sp(rxq[i]);
862 memcpy(&rx_qconf[i], &rxq_sp->qconf, sizeof(*rx_qconf));
863 rx_qconf[i].valid = true;
864 dev_ops->rx_queue_release(eth_dev, i);
865 eth_dev->data->rx_queues[i] = NULL;
868 dev->tx_qconf = tx_qconf;
869 dev->rx_qconf = rx_qconf;
879 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
881 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
882 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
883 struct cnxk_eth_qconf *tx_qconf = dev->tx_qconf;
884 struct cnxk_eth_qconf *rx_qconf = dev->rx_qconf;
885 int rc, i, nb_rxq, nb_txq;
887 nb_rxq = RTE_MIN(dev->nb_rxq, eth_dev->data->nb_rx_queues);
888 nb_txq = RTE_MIN(dev->nb_txq, eth_dev->data->nb_tx_queues);
891 /* Setup tx & rx queues with previous configuration so
892 * that the queues can be functional in cases like ports
893 * are started without re configuring queues.
895 * Usual re config sequence is like below:
901 * queue_configure() {
908 * In some application's control path, queue_configure() would
909 * NOT be invoked for TXQs/RXQs in port_configure().
910 * In such cases, queues can be functional after start as the
911 * queues are already setup in port_configure().
913 for (i = 0; i < nb_txq; i++) {
914 if (!tx_qconf[i].valid)
916 rc = dev_ops->tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc, 0,
917 &tx_qconf[i].conf.tx);
919 plt_err("Failed to setup tx queue rc=%d", rc);
920 for (i -= 1; i >= 0; i--)
921 dev_ops->tx_queue_release(eth_dev, i);
929 for (i = 0; i < nb_rxq; i++) {
930 if (!rx_qconf[i].valid)
932 rc = dev_ops->rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc, 0,
933 &rx_qconf[i].conf.rx,
936 plt_err("Failed to setup rx queue rc=%d", rc);
937 for (i -= 1; i >= 0; i--)
938 dev_ops->rx_queue_release(eth_dev, i);
939 goto tx_queue_release;
949 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
950 dev_ops->tx_queue_release(eth_dev, i);
959 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
961 /* These dummy functions are required for supporting
962 * some applications which reconfigure queues without
963 * stopping tx burst and rx burst threads(eg kni app)
964 * When the queues context is saved, txq/rxqs are released
965 * which caused app crash since rx/tx burst is still
966 * on different lcores
968 eth_dev->tx_pkt_burst = rte_eth_pkt_burst_dummy;
969 eth_dev->rx_pkt_burst = rte_eth_pkt_burst_dummy;
974 nix_lso_tun_fmt_update(struct cnxk_eth_dev *dev)
976 uint8_t udp_tun[ROC_NIX_LSO_TUN_MAX];
977 uint8_t tun[ROC_NIX_LSO_TUN_MAX];
978 struct roc_nix *nix = &dev->nix;
981 rc = roc_nix_lso_fmt_get(nix, udp_tun, tun);
985 dev->lso_tun_fmt = ((uint64_t)tun[ROC_NIX_LSO_TUN_V4V4] |
986 (uint64_t)tun[ROC_NIX_LSO_TUN_V4V6] << 8 |
987 (uint64_t)tun[ROC_NIX_LSO_TUN_V6V4] << 16 |
988 (uint64_t)tun[ROC_NIX_LSO_TUN_V6V6] << 24);
990 dev->lso_tun_fmt |= ((uint64_t)udp_tun[ROC_NIX_LSO_TUN_V4V4] << 32 |
991 (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V4V6] << 40 |
992 (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V6V4] << 48 |
993 (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V6V6] << 56);
998 nix_lso_fmt_setup(struct cnxk_eth_dev *dev)
1000 struct roc_nix *nix = &dev->nix;
1003 /* Nothing much to do if offload is not enabled */
1004 if (!(dev->tx_offloads &
1005 (RTE_ETH_TX_OFFLOAD_TCP_TSO | RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
1006 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO | RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO)))
1009 /* Setup LSO formats in AF. Its a no-op if other ethdev has
1012 rc = roc_nix_lso_fmt_setup(nix);
1016 return nix_lso_tun_fmt_update(dev);
1020 cnxk_nix_configure(struct rte_eth_dev *eth_dev)
1022 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1023 struct rte_eth_dev_data *data = eth_dev->data;
1024 struct rte_eth_conf *conf = &data->dev_conf;
1025 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1026 struct rte_eth_txmode *txmode = &conf->txmode;
1027 char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
1028 struct roc_nix_fc_cfg fc_cfg = {0};
1029 struct roc_nix *nix = &dev->nix;
1030 struct rte_ether_addr *ea;
1031 uint8_t nb_rxq, nb_txq;
1039 if (rte_eal_has_hugepages() == 0) {
1040 plt_err("Huge page is not configured");
1041 goto fail_configure;
1044 if (conf->dcb_capability_en == 1) {
1045 plt_err("dcb enable is not supported");
1046 goto fail_configure;
1049 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1050 plt_err("Flow director is not supported");
1051 goto fail_configure;
1054 if (rxmode->mq_mode != RTE_ETH_MQ_RX_NONE &&
1055 rxmode->mq_mode != RTE_ETH_MQ_RX_RSS) {
1056 plt_err("Unsupported mq rx mode %d", rxmode->mq_mode);
1057 goto fail_configure;
1060 if (txmode->mq_mode != RTE_ETH_MQ_TX_NONE) {
1061 plt_err("Unsupported mq tx mode %d", txmode->mq_mode);
1062 goto fail_configure;
1065 /* Free the resources allocated from the previous configure */
1066 if (dev->configured == 1) {
1067 /* Unregister queue irq's */
1068 roc_nix_unregister_queue_irqs(nix);
1070 /* Unregister CQ irqs if present */
1071 if (eth_dev->data->dev_conf.intr_conf.rxq)
1072 roc_nix_unregister_cq_irqs(nix);
1074 /* Set no-op functions */
1075 nix_set_nop_rxtx_function(eth_dev);
1076 /* Store queue config for later */
1077 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1079 goto fail_configure;
1081 /* Disable and free rte_meter entries */
1082 rc = nix_meter_fini(dev);
1084 goto fail_configure;
1086 /* Cleanup security support */
1087 rc = nix_security_release(dev);
1089 goto fail_configure;
1091 roc_nix_tm_fini(nix);
1092 roc_nix_lf_free(nix);
1095 dev->rx_offloads = rxmode->offloads;
1096 dev->tx_offloads = txmode->offloads;
1098 /* Prepare rx cfg */
1099 rx_cfg = ROC_NIX_LF_RX_CFG_DIS_APAD;
1100 if (dev->rx_offloads &
1101 (RTE_ETH_RX_OFFLOAD_TCP_CKSUM | RTE_ETH_RX_OFFLOAD_UDP_CKSUM)) {
1102 rx_cfg |= ROC_NIX_LF_RX_CFG_CSUM_OL4;
1103 rx_cfg |= ROC_NIX_LF_RX_CFG_CSUM_IL4;
1105 rx_cfg |= (ROC_NIX_LF_RX_CFG_DROP_RE | ROC_NIX_LF_RX_CFG_L2_LEN_ERR |
1106 ROC_NIX_LF_RX_CFG_LEN_IL4 | ROC_NIX_LF_RX_CFG_LEN_IL3 |
1107 ROC_NIX_LF_RX_CFG_LEN_OL4 | ROC_NIX_LF_RX_CFG_LEN_OL3);
1109 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
1110 rx_cfg |= ROC_NIX_LF_RX_CFG_IP6_UDP_OPT;
1111 /* Disable drop re if rx offload security is enabled and
1112 * platform does not support it.
1114 if (dev->ipsecd_drop_re_dis)
1115 rx_cfg &= ~(ROC_NIX_LF_RX_CFG_DROP_RE);
1118 nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1119 nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1121 /* Alloc a nix lf */
1122 rc = roc_nix_lf_alloc(nix, nb_rxq, nb_txq, rx_cfg);
1124 plt_err("Failed to init nix_lf rc=%d", rc);
1125 goto fail_configure;
1128 dev->npc.channel = roc_nix_get_base_chan(nix);
1130 nb_rxq = data->nb_rx_queues;
1131 nb_txq = data->nb_tx_queues;
1134 /* Allocate memory for roc rq's and cq's */
1135 qs = plt_zmalloc(sizeof(struct roc_nix_rq) * nb_rxq, 0);
1137 plt_err("Failed to alloc rqs");
1142 qs = plt_zmalloc(sizeof(struct roc_nix_cq) * nb_rxq, 0);
1144 plt_err("Failed to alloc cqs");
1151 /* Allocate memory for roc sq's */
1152 qs = plt_zmalloc(sizeof(struct roc_nix_sq) * nb_txq, 0);
1154 plt_err("Failed to alloc sqs");
1160 /* Re-enable NIX LF error interrupts */
1161 roc_nix_err_intr_ena_dis(nix, true);
1162 roc_nix_ras_intr_ena_dis(nix, true);
1164 if (nix->rx_ptp_ena &&
1165 dev->npc.switch_header_type == ROC_PRIV_FLAGS_HIGIG) {
1166 plt_err("Both PTP and switch header enabled");
1170 rc = roc_nix_switch_hdr_set(nix, dev->npc.switch_header_type,
1171 dev->npc.pre_l2_size_offset,
1172 dev->npc.pre_l2_size_offset_mask,
1173 dev->npc.pre_l2_size_shift_dir);
1175 plt_err("Failed to enable switch type nix_lf rc=%d", rc);
1179 /* Setup LSO if needed */
1180 rc = nix_lso_fmt_setup(dev);
1182 plt_err("Failed to setup nix lso format fields, rc=%d", rc);
1187 rc = nix_rss_default_setup(dev);
1189 plt_err("Failed to configure rss rc=%d", rc);
1193 /* Init the default TM scheduler hierarchy */
1194 rc = roc_nix_tm_init(nix);
1196 plt_err("Failed to init traffic manager, rc=%d", rc);
1200 rc = nix_ingress_policer_setup(dev);
1202 plt_err("Failed to setup ingress policer rc=%d", rc);
1206 rc = roc_nix_tm_hierarchy_enable(nix, ROC_NIX_TM_DEFAULT, false);
1208 plt_err("Failed to enable default tm hierarchy, rc=%d", rc);
1212 /* Register queue IRQs */
1213 rc = roc_nix_register_queue_irqs(nix);
1215 plt_err("Failed to register queue interrupts rc=%d", rc);
1219 /* Register cq IRQs */
1220 if (eth_dev->data->dev_conf.intr_conf.rxq) {
1221 if (eth_dev->data->nb_rx_queues > dev->nix.cints) {
1222 plt_err("Rx interrupt cannot be enabled, rxq > %d",
1226 /* Rx interrupt feature cannot work with vector mode because,
1227 * vector mode does not process packets unless min 4 pkts are
1228 * received, while cq interrupts are generated even for 1 pkt
1231 dev->scalar_ena = true;
1233 rc = roc_nix_register_cq_irqs(nix);
1235 plt_err("Failed to register CQ interrupts rc=%d", rc);
1240 /* Configure loop back mode */
1241 rc = roc_nix_mac_loopback_enable(nix,
1242 eth_dev->data->dev_conf.lpbk_mode);
1244 plt_err("Failed to configure cgx loop back mode rc=%d", rc);
1248 /* Setup Inline security support */
1249 rc = nix_security_setup(dev);
1253 /* Init flow control configuration */
1254 fc_cfg.type = ROC_NIX_FC_RXCHAN_CFG;
1255 fc_cfg.rxchan_cfg.enable = true;
1256 rc = roc_nix_fc_config_set(nix, &fc_cfg);
1258 plt_err("Failed to initialize flow control rc=%d", rc);
1262 /* Update flow control configuration to PMD */
1263 rc = nix_init_flow_ctrl_config(eth_dev);
1265 plt_err("Failed to initialize flow control rc=%d", rc);
1269 /* Initialize TC to SQ mapping as invalid */
1270 memset(dev->pfc_tc_sq_map, 0xFF, sizeof(dev->pfc_tc_sq_map));
1272 * Restore queue config when reconfigure followed by
1273 * reconfigure and no queue configure invoked from application case.
1275 if (dev->configured == 1) {
1276 rc = nix_restore_queue_cfg(eth_dev);
1281 /* Update the mac address */
1282 ea = eth_dev->data->mac_addrs;
1283 memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1284 if (rte_is_zero_ether_addr(ea))
1285 rte_eth_random_addr((uint8_t *)ea);
1287 rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
1289 plt_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
1290 " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 "",
1291 eth_dev->data->port_id, ea_fmt, nb_rxq, nb_txq,
1292 dev->rx_offloads, dev->tx_offloads);
1295 dev->configured = 1;
1296 dev->nb_rxq = data->nb_rx_queues;
1297 dev->nb_txq = data->nb_tx_queues;
1301 rc |= nix_security_release(dev);
1303 roc_nix_unregister_cq_irqs(nix);
1305 roc_nix_unregister_queue_irqs(nix);
1307 roc_nix_tm_fini(nix);
1309 nix_free_queue_mem(dev);
1310 rc |= roc_nix_lf_free(nix);
1312 dev->configured = 0;
1317 cnxk_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid)
1319 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1320 struct rte_eth_dev_data *data = eth_dev->data;
1321 struct roc_nix_sq *sq = &dev->sqs[qid];
1324 if (data->tx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STARTED)
1327 rc = roc_nix_tm_sq_aura_fc(sq, true);
1329 plt_err("Failed to enable sq aura fc, txq=%u, rc=%d", qid, rc);
1333 data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STARTED;
1339 cnxk_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid)
1341 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1342 struct rte_eth_dev_data *data = eth_dev->data;
1343 struct roc_nix_sq *sq = &dev->sqs[qid];
1346 if (data->tx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STOPPED)
1349 rc = roc_nix_tm_sq_aura_fc(sq, false);
1351 plt_err("Failed to disable sqb aura fc, txq=%u, rc=%d", qid,
1356 data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
1362 cnxk_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid)
1364 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1365 struct rte_eth_dev_data *data = eth_dev->data;
1366 struct roc_nix_rq *rq = &dev->rqs[qid];
1369 if (data->rx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STARTED)
1372 rc = roc_nix_rq_ena_dis(rq, true);
1374 plt_err("Failed to enable rxq=%u, rc=%d", qid, rc);
1378 data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STARTED;
1384 cnxk_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid)
1386 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1387 struct rte_eth_dev_data *data = eth_dev->data;
1388 struct roc_nix_rq *rq = &dev->rqs[qid];
1391 if (data->rx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STOPPED)
1394 rc = roc_nix_rq_ena_dis(rq, false);
1396 plt_err("Failed to disable rxq=%u, rc=%d", qid, rc);
1400 data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
1406 cnxk_nix_dev_stop(struct rte_eth_dev *eth_dev)
1408 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1409 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
1410 struct rte_mbuf *rx_pkts[32];
1411 struct rte_eth_link link;
1412 int count, i, j, rc;
1415 /* Disable all the NPC entries */
1416 rc = roc_npc_mcam_enable_all_entries(&dev->npc, 0);
1420 /* Stop link change events */
1421 if (!roc_nix_is_vf_or_sdp(&dev->nix))
1422 roc_nix_mac_link_event_start_stop(&dev->nix, false);
1424 /* Disable Rx via NPC */
1425 roc_nix_npc_rx_ena_dis(&dev->nix, false);
1427 /* Stop rx queues and free up pkts pending */
1428 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1429 rc = dev_ops->rx_queue_stop(eth_dev, i);
1433 rxq = eth_dev->data->rx_queues[i];
1434 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1436 for (j = 0; j < count; j++)
1437 rte_pktmbuf_free(rx_pkts[j]);
1438 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1442 /* Stop tx queues */
1443 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1444 dev_ops->tx_queue_stop(eth_dev, i);
1446 /* Bring down link status internally */
1447 memset(&link, 0, sizeof(link));
1448 rte_eth_linkstatus_set(eth_dev, &link);
1454 cnxk_nix_dev_start(struct rte_eth_dev *eth_dev)
1456 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1459 if (eth_dev->data->nb_rx_queues != 0 && !dev->ptp_en) {
1460 rc = nix_recalc_mtu(eth_dev);
1465 /* Start rx queues */
1466 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1467 rc = cnxk_nix_rx_queue_start(eth_dev, i);
1472 /* Start tx queues */
1473 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1474 rc = cnxk_nix_tx_queue_start(eth_dev, i);
1479 /* Update Flow control configuration */
1480 rc = nix_update_flow_ctrl_config(eth_dev);
1482 plt_err("Failed to enable flow control. error code(%d)", rc);
1486 /* Enable Rx in NPC */
1487 rc = roc_nix_npc_rx_ena_dis(&dev->nix, true);
1489 plt_err("Failed to enable NPC rx %d", rc);
1493 rc = roc_npc_mcam_enable_all_entries(&dev->npc, 1);
1495 plt_err("Failed to enable NPC entries %d", rc);
1499 cnxk_nix_toggle_flag_link_cfg(dev, true);
1501 /* Start link change events */
1502 if (!roc_nix_is_vf_or_sdp(&dev->nix)) {
1503 rc = roc_nix_mac_link_event_start_stop(&dev->nix, true);
1505 plt_err("Failed to start cgx link event %d", rc);
1510 /* Enable PTP if it is requested by the user or already
1511 * enabled on PF owning this VF
1513 memset(&dev->tstamp, 0, sizeof(struct cnxk_timesync_info));
1514 if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) || dev->ptp_en)
1515 cnxk_eth_dev_ops.timesync_enable(eth_dev);
1517 cnxk_eth_dev_ops.timesync_disable(eth_dev);
1519 if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
1520 rc = rte_mbuf_dyn_rx_timestamp_register
1521 (&dev->tstamp.tstamp_dynfield_offset,
1522 &dev->tstamp.rx_tstamp_dynflag);
1524 plt_err("Failed to register Rx timestamp field/flag");
1529 cnxk_nix_toggle_flag_link_cfg(dev, false);
1534 roc_nix_npc_rx_ena_dis(&dev->nix, false);
1535 cnxk_nix_toggle_flag_link_cfg(dev, false);
1539 static int cnxk_nix_dev_reset(struct rte_eth_dev *eth_dev);
1540 static int cnxk_nix_dev_close(struct rte_eth_dev *eth_dev);
1542 /* CNXK platform independent eth dev ops */
1543 struct eth_dev_ops cnxk_eth_dev_ops = {
1544 .mtu_set = cnxk_nix_mtu_set,
1545 .mac_addr_add = cnxk_nix_mac_addr_add,
1546 .mac_addr_remove = cnxk_nix_mac_addr_del,
1547 .mac_addr_set = cnxk_nix_mac_addr_set,
1548 .dev_infos_get = cnxk_nix_info_get,
1549 .link_update = cnxk_nix_link_update,
1550 .tx_queue_release = cnxk_nix_tx_queue_release,
1551 .rx_queue_release = cnxk_nix_rx_queue_release,
1552 .dev_stop = cnxk_nix_dev_stop,
1553 .dev_close = cnxk_nix_dev_close,
1554 .dev_reset = cnxk_nix_dev_reset,
1555 .tx_queue_start = cnxk_nix_tx_queue_start,
1556 .rx_queue_start = cnxk_nix_rx_queue_start,
1557 .rx_queue_stop = cnxk_nix_rx_queue_stop,
1558 .dev_supported_ptypes_get = cnxk_nix_supported_ptypes_get,
1559 .promiscuous_enable = cnxk_nix_promisc_enable,
1560 .promiscuous_disable = cnxk_nix_promisc_disable,
1561 .allmulticast_enable = cnxk_nix_allmulticast_enable,
1562 .allmulticast_disable = cnxk_nix_allmulticast_disable,
1563 .rx_burst_mode_get = cnxk_nix_rx_burst_mode_get,
1564 .tx_burst_mode_get = cnxk_nix_tx_burst_mode_get,
1565 .flow_ctrl_get = cnxk_nix_flow_ctrl_get,
1566 .flow_ctrl_set = cnxk_nix_flow_ctrl_set,
1567 .priority_flow_ctrl_queue_config =
1568 cnxk_nix_priority_flow_ctrl_queue_config,
1569 .priority_flow_ctrl_queue_info_get =
1570 cnxk_nix_priority_flow_ctrl_queue_info_get,
1571 .dev_set_link_up = cnxk_nix_set_link_up,
1572 .dev_set_link_down = cnxk_nix_set_link_down,
1573 .get_module_info = cnxk_nix_get_module_info,
1574 .get_module_eeprom = cnxk_nix_get_module_eeprom,
1575 .rx_queue_intr_enable = cnxk_nix_rx_queue_intr_enable,
1576 .rx_queue_intr_disable = cnxk_nix_rx_queue_intr_disable,
1577 .pool_ops_supported = cnxk_nix_pool_ops_supported,
1578 .queue_stats_mapping_set = cnxk_nix_queue_stats_mapping,
1579 .stats_get = cnxk_nix_stats_get,
1580 .stats_reset = cnxk_nix_stats_reset,
1581 .xstats_get = cnxk_nix_xstats_get,
1582 .xstats_get_names = cnxk_nix_xstats_get_names,
1583 .xstats_reset = cnxk_nix_xstats_reset,
1584 .xstats_get_by_id = cnxk_nix_xstats_get_by_id,
1585 .xstats_get_names_by_id = cnxk_nix_xstats_get_names_by_id,
1586 .fw_version_get = cnxk_nix_fw_version_get,
1587 .rxq_info_get = cnxk_nix_rxq_info_get,
1588 .txq_info_get = cnxk_nix_txq_info_get,
1589 .tx_done_cleanup = cnxk_nix_tx_done_cleanup,
1590 .flow_ops_get = cnxk_nix_flow_ops_get,
1591 .get_reg = cnxk_nix_dev_get_reg,
1592 .timesync_read_rx_timestamp = cnxk_nix_timesync_read_rx_timestamp,
1593 .timesync_read_tx_timestamp = cnxk_nix_timesync_read_tx_timestamp,
1594 .timesync_read_time = cnxk_nix_timesync_read_time,
1595 .timesync_write_time = cnxk_nix_timesync_write_time,
1596 .timesync_adjust_time = cnxk_nix_timesync_adjust_time,
1597 .read_clock = cnxk_nix_read_clock,
1598 .reta_update = cnxk_nix_reta_update,
1599 .reta_query = cnxk_nix_reta_query,
1600 .rss_hash_update = cnxk_nix_rss_hash_update,
1601 .rss_hash_conf_get = cnxk_nix_rss_hash_conf_get,
1602 .set_mc_addr_list = cnxk_nix_mc_addr_list_configure,
1603 .set_queue_rate_limit = cnxk_nix_tm_set_queue_rate_limit,
1604 .tm_ops_get = cnxk_nix_tm_ops_get,
1605 .mtr_ops_get = cnxk_nix_mtr_ops_get,
1609 cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)
1611 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1612 struct rte_security_ctx *sec_ctx;
1613 struct roc_nix *nix = &dev->nix;
1614 struct rte_pci_device *pci_dev;
1615 int rc, max_entries;
1617 eth_dev->dev_ops = &cnxk_eth_dev_ops;
1618 eth_dev->rx_queue_count = cnxk_nix_rx_queue_count;
1619 eth_dev->rx_descriptor_status = cnxk_nix_rx_descriptor_status;
1620 eth_dev->tx_descriptor_status = cnxk_nix_tx_descriptor_status;
1622 /* Alloc security context */
1623 sec_ctx = plt_zmalloc(sizeof(struct rte_security_ctx), 0);
1626 sec_ctx->device = eth_dev;
1627 sec_ctx->ops = &cnxk_eth_sec_ops;
1629 (RTE_SEC_CTX_F_FAST_SET_MDATA | RTE_SEC_CTX_F_FAST_GET_UDATA);
1630 eth_dev->security_ctx = sec_ctx;
1632 /* For secondary processes, the primary has done all the work */
1633 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1636 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1637 rte_eth_copy_pci_info(eth_dev, pci_dev);
1639 /* Parse devargs string */
1640 rc = cnxk_ethdev_parse_devargs(eth_dev->device->devargs, dev);
1642 plt_err("Failed to parse devargs rc=%d", rc);
1646 /* Initialize base roc nix */
1647 nix->pci_dev = pci_dev;
1648 nix->hw_vlan_ins = true;
1649 rc = roc_nix_dev_init(nix);
1651 plt_err("Failed to initialize roc nix rc=%d", rc);
1655 /* Register up msg callbacks */
1656 roc_nix_mac_link_cb_register(nix, cnxk_eth_dev_link_status_cb);
1658 /* Register up msg callbacks */
1659 roc_nix_mac_link_info_get_cb_register(nix,
1660 cnxk_eth_dev_link_status_get_cb);
1662 dev->eth_dev = eth_dev;
1663 dev->configured = 0;
1664 dev->ptype_disable = 0;
1666 TAILQ_INIT(&dev->inb.list);
1667 TAILQ_INIT(&dev->outb.list);
1668 rte_spinlock_init(&dev->inb.lock);
1669 rte_spinlock_init(&dev->outb.lock);
1671 /* For vfs, returned max_entries will be 0. but to keep default mac
1672 * address, one entry must be allocated. so setting up to 1.
1674 if (roc_nix_is_vf_or_sdp(nix))
1677 max_entries = roc_nix_mac_max_entries_get(nix);
1679 if (max_entries <= 0) {
1680 plt_err("Failed to get max entries for mac addr");
1685 eth_dev->data->mac_addrs =
1686 rte_zmalloc("mac_addr", max_entries * RTE_ETHER_ADDR_LEN, 0);
1687 if (eth_dev->data->mac_addrs == NULL) {
1688 plt_err("Failed to allocate memory for mac addr");
1693 dev->max_mac_entries = max_entries;
1694 dev->dmac_filter_count = 1;
1696 /* Get mac address */
1697 rc = roc_nix_npc_mac_addr_get(nix, dev->mac_addr);
1699 plt_err("Failed to get mac addr, rc=%d", rc);
1700 goto free_mac_addrs;
1703 /* Update the mac address */
1704 memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1706 if (!roc_nix_is_vf_or_sdp(nix)) {
1707 /* Sync same MAC address to CGX/RPM table */
1708 rc = roc_nix_mac_addr_set(nix, dev->mac_addr);
1710 plt_err("Failed to set mac addr, rc=%d", rc);
1711 goto free_mac_addrs;
1715 /* Union of all capabilities supported by CNXK.
1716 * Platform specific capabilities will be
1719 dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
1720 dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
1721 dev->speed_capa = nix_get_speed_capa(dev);
1723 /* Initialize roc npc */
1724 dev->npc.roc_nix = nix;
1725 rc = roc_npc_init(&dev->npc);
1727 goto free_mac_addrs;
1729 plt_nix_dbg("Port=%d pf=%d vf=%d ver=%s hwcap=0x%" PRIx64
1730 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
1731 eth_dev->data->port_id, roc_nix_get_pf(nix),
1732 roc_nix_get_vf(nix), CNXK_ETH_DEV_PMD_VERSION, dev->hwcap,
1733 dev->rx_offload_capa, dev->tx_offload_capa);
1737 rte_free(eth_dev->data->mac_addrs);
1739 roc_nix_dev_fini(nix);
1741 plt_err("Failed to init nix eth_dev rc=%d", rc);
1746 cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool reset)
1748 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1749 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
1750 struct rte_eth_pfc_queue_conf pfc_conf;
1751 struct roc_nix *nix = &dev->nix;
1752 struct rte_eth_fc_conf fc_conf;
1755 /* Disable switch hdr pkind */
1756 roc_nix_switch_hdr_set(&dev->nix, 0, 0, 0, 0);
1758 plt_free(eth_dev->security_ctx);
1759 eth_dev->security_ctx = NULL;
1761 /* Nothing to be done for secondary processes */
1762 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1765 /* Clear the flag since we are closing down */
1766 dev->configured = 0;
1768 roc_nix_npc_rx_ena_dis(nix, false);
1770 /* Restore 802.3 Flow control configuration */
1771 memset(&pfc_conf, 0, sizeof(struct rte_eth_pfc_queue_conf));
1772 memset(&fc_conf, 0, sizeof(struct rte_eth_fc_conf));
1773 fc_conf.mode = RTE_ETH_FC_NONE;
1774 rc = cnxk_nix_flow_ctrl_set(eth_dev, &fc_conf);
1776 pfc_conf.mode = RTE_ETH_FC_NONE;
1777 for (i = 0; i < CNXK_NIX_PFC_CHAN_COUNT; i++) {
1778 if (dev->pfc_tc_sq_map[i] != 0xFFFF) {
1779 pfc_conf.rx_pause.tx_qid = dev->pfc_tc_sq_map[i];
1780 pfc_conf.rx_pause.tc = i;
1781 pfc_conf.tx_pause.rx_qid = i;
1782 pfc_conf.tx_pause.tc = i;
1783 rc = cnxk_nix_priority_flow_ctrl_queue_config(eth_dev,
1786 plt_err("Failed to reset PFC. error code(%d)",
1791 fc_conf.mode = RTE_ETH_FC_FULL;
1792 rc = cnxk_nix_flow_ctrl_set(eth_dev, &fc_conf);
1794 /* Disable and free rte_meter entries */
1795 nix_meter_fini(dev);
1797 /* Disable and free rte_flow entries */
1798 roc_npc_fini(&dev->npc);
1800 /* Disable link status events */
1801 roc_nix_mac_link_event_start_stop(nix, false);
1803 /* Unregister the link update op, this is required to stop VFs from
1804 * receiving link status updates on exit path.
1806 roc_nix_mac_link_cb_unregister(nix);
1809 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1810 dev_ops->tx_queue_release(eth_dev, i);
1811 eth_dev->data->tx_queues[i] = NULL;
1813 eth_dev->data->nb_tx_queues = 0;
1815 /* Free up RQ's and CQ's */
1816 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1817 dev_ops->rx_queue_release(eth_dev, i);
1818 eth_dev->data->rx_queues[i] = NULL;
1820 eth_dev->data->nb_rx_queues = 0;
1822 /* Free security resources */
1823 nix_security_release(dev);
1825 /* Free tm resources */
1826 roc_nix_tm_fini(nix);
1828 /* Unregister queue irqs */
1829 roc_nix_unregister_queue_irqs(nix);
1831 /* Unregister cq irqs */
1832 if (eth_dev->data->dev_conf.intr_conf.rxq)
1833 roc_nix_unregister_cq_irqs(nix);
1835 /* Free ROC RQ's, SQ's and CQ's memory */
1836 nix_free_queue_mem(dev);
1838 /* Free nix lf resources */
1839 rc = roc_nix_lf_free(nix);
1841 plt_err("Failed to free nix lf, rc=%d", rc);
1843 rte_free(eth_dev->data->mac_addrs);
1844 eth_dev->data->mac_addrs = NULL;
1846 rc = roc_nix_dev_fini(nix);
1847 /* Can be freed later by PMD if NPA LF is in use */
1848 if (rc == -EAGAIN) {
1850 eth_dev->data->dev_private = NULL;
1853 plt_err("Failed in nix dev fini, rc=%d", rc);
1860 cnxk_nix_dev_close(struct rte_eth_dev *eth_dev)
1862 cnxk_eth_dev_uninit(eth_dev, false);
1867 cnxk_nix_dev_reset(struct rte_eth_dev *eth_dev)
1871 rc = cnxk_eth_dev_uninit(eth_dev, true);
1875 return cnxk_eth_dev_init(eth_dev);
1879 cnxk_nix_remove(struct rte_pci_device *pci_dev)
1881 struct rte_eth_dev *eth_dev;
1882 struct roc_nix *nix;
1885 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
1887 /* Cleanup eth dev */
1888 rc = cnxk_eth_dev_uninit(eth_dev, false);
1892 rte_eth_dev_release_port(eth_dev);
1895 /* Nothing to be done for secondary processes */
1896 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1899 /* Check if this device is hosting common resource */
1900 nix = roc_idev_npa_nix_get();
1901 if (nix->pci_dev != pci_dev)
1904 /* Try nix fini now */
1905 rc = roc_nix_dev_fini(nix);
1906 if (rc == -EAGAIN) {
1907 plt_info("%s: common resource in use by other devices",
1911 plt_err("Failed in nix dev fini, rc=%d", rc);
1915 /* Free device pointer as rte_ethdev does not have it anymore */
1922 cnxk_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1926 RTE_SET_USED(pci_drv);
1928 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct cnxk_eth_dev),
1931 /* On error on secondary, recheck if port exists in primary or
1932 * in mid of detach state.
1934 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
1935 if (!rte_eth_dev_allocated(pci_dev->device.name))