1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
4 #include <cnxk_ethdev.h>
7 nix_get_rx_offload_capa(struct cnxk_eth_dev *dev)
9 uint64_t capa = CNXK_NIX_RX_OFFLOAD_CAPA;
11 if (roc_nix_is_vf_or_sdp(&dev->nix) ||
12 dev->npc.switch_header_type == ROC_PRIV_FLAGS_HIGIG)
13 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
18 static inline uint64_t
19 nix_get_tx_offload_capa(struct cnxk_eth_dev *dev)
22 return CNXK_NIX_TX_OFFLOAD_CAPA;
25 static inline uint32_t
26 nix_get_speed_capa(struct cnxk_eth_dev *dev)
30 /* Auto negotiation disabled */
31 speed_capa = ETH_LINK_SPEED_FIXED;
32 if (!roc_nix_is_vf_or_sdp(&dev->nix) && !roc_nix_is_lbk(&dev->nix)) {
33 speed_capa |= ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
34 ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
35 ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
42 cnxk_nix_inb_mode_set(struct cnxk_eth_dev *dev, bool use_inl_dev)
44 struct roc_nix *nix = &dev->nix;
46 if (dev->inb.inl_dev == use_inl_dev)
49 plt_nix_dbg("Security sessions(%u) still active, inl=%u!!!",
50 dev->inb.nb_sess, !!dev->inb.inl_dev);
53 dev->inb.inl_dev = use_inl_dev;
55 /* Update RoC for NPC rule insertion */
56 roc_nix_inb_mode_set(nix, use_inl_dev);
58 /* Setup lookup mem */
59 return cnxk_nix_lookup_mem_sa_base_set(dev);
63 nix_security_setup(struct cnxk_eth_dev *dev)
65 struct roc_nix *nix = &dev->nix;
68 if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
69 /* Setup Inline Inbound */
70 rc = roc_nix_inl_inb_init(nix);
72 plt_err("Failed to initialize nix inline inb, rc=%d",
77 /* By default pick using inline device for poll mode.
78 * Will be overridden when event mode rq's are setup.
80 cnxk_nix_inb_mode_set(dev, true);
83 if (dev->tx_offloads & DEV_TX_OFFLOAD_SECURITY ||
84 dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
85 struct plt_bitmap *bmap;
89 /* Setup enough descriptors for all tx queues */
90 nix->outb_nb_desc = dev->outb.nb_desc;
91 nix->outb_nb_crypto_qs = dev->outb.nb_crypto_qs;
93 /* Setup Inline Outbound */
94 rc = roc_nix_inl_outb_init(nix);
96 plt_err("Failed to initialize nix inline outb, rc=%d",
101 dev->outb.lf_base = roc_nix_inl_outb_lf_base_get(nix);
103 /* Skip the rest if DEV_TX_OFFLOAD_SECURITY is not enabled */
104 if (!(dev->tx_offloads & DEV_TX_OFFLOAD_SECURITY))
108 /* Allocate a bitmap to alloc and free sa indexes */
109 bmap_sz = plt_bitmap_get_memory_footprint(dev->outb.max_sa);
110 mem = plt_zmalloc(bmap_sz, PLT_CACHE_LINE_SIZE);
112 plt_err("Outbound SA bmap alloc failed");
114 rc |= roc_nix_inl_outb_fini(nix);
119 bmap = plt_bitmap_init(dev->outb.max_sa, mem, bmap_sz);
121 plt_err("Outbound SA bmap init failed");
123 rc |= roc_nix_inl_outb_fini(nix);
128 for (i = 0; i < dev->outb.max_sa; i++)
129 plt_bitmap_set(bmap, i);
131 dev->outb.sa_base = roc_nix_inl_outb_sa_base_get(nix);
132 dev->outb.sa_bmap_mem = mem;
133 dev->outb.sa_bmap = bmap;
139 if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY)
140 rc |= roc_nix_inl_inb_fini(nix);
145 nix_security_release(struct cnxk_eth_dev *dev)
147 struct rte_eth_dev *eth_dev = dev->eth_dev;
148 struct cnxk_eth_sec_sess *eth_sec, *tvar;
149 struct roc_nix *nix = &dev->nix;
152 /* Cleanup Inline inbound */
153 if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
154 /* Destroy inbound sessions */
156 RTE_TAILQ_FOREACH_SAFE(eth_sec, &dev->inb.list, entry, tvar)
157 cnxk_eth_sec_ops.session_destroy(eth_dev,
160 /* Clear lookup mem */
161 cnxk_nix_lookup_mem_sa_base_clear(dev);
163 rc = roc_nix_inl_inb_fini(nix);
165 plt_err("Failed to cleanup nix inline inb, rc=%d", rc);
169 /* Cleanup Inline outbound */
170 if (dev->tx_offloads & DEV_TX_OFFLOAD_SECURITY ||
171 dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
172 /* Destroy outbound sessions */
174 RTE_TAILQ_FOREACH_SAFE(eth_sec, &dev->outb.list, entry, tvar)
175 cnxk_eth_sec_ops.session_destroy(eth_dev,
178 rc = roc_nix_inl_outb_fini(nix);
180 plt_err("Failed to cleanup nix inline outb, rc=%d", rc);
183 plt_bitmap_free(dev->outb.sa_bmap);
184 plt_free(dev->outb.sa_bmap_mem);
185 dev->outb.sa_bmap = NULL;
186 dev->outb.sa_bmap_mem = NULL;
189 dev->inb.inl_dev = false;
190 roc_nix_inb_mode_set(nix, false);
192 dev->inb.nb_sess = 0;
193 dev->outb.nb_sess = 0;
198 nix_enable_mseg_on_jumbo(struct cnxk_eth_rxq_sp *rxq)
200 struct rte_pktmbuf_pool_private *mbp_priv;
201 struct rte_eth_dev *eth_dev;
202 struct cnxk_eth_dev *dev;
206 eth_dev = dev->eth_dev;
208 /* Get rx buffer size */
209 mbp_priv = rte_mempool_get_priv(rxq->qconf.mp);
210 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
212 if (eth_dev->data->mtu + (uint32_t)CNXK_NIX_L2_OVERHEAD > buffsz) {
213 dev->rx_offloads |= DEV_RX_OFFLOAD_SCATTER;
214 dev->tx_offloads |= DEV_TX_OFFLOAD_MULTI_SEGS;
219 nix_recalc_mtu(struct rte_eth_dev *eth_dev)
221 struct rte_eth_dev_data *data = eth_dev->data;
222 struct cnxk_eth_rxq_sp *rxq;
225 rxq = ((struct cnxk_eth_rxq_sp *)data->rx_queues[0]) - 1;
226 /* Setup scatter mode if needed by jumbo */
227 nix_enable_mseg_on_jumbo(rxq);
229 rc = cnxk_nix_mtu_set(eth_dev, data->mtu);
231 plt_err("Failed to set default MTU size, rc=%d", rc);
237 nix_init_flow_ctrl_config(struct rte_eth_dev *eth_dev)
239 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
240 struct cnxk_fc_cfg *fc = &dev->fc_cfg;
241 struct rte_eth_fc_conf fc_conf = {0};
244 /* Both Rx & Tx flow ctrl get enabled(RTE_FC_FULL) in HW
245 * by AF driver, update those info in PMD structure.
247 rc = cnxk_nix_flow_ctrl_get(eth_dev, &fc_conf);
251 fc->mode = fc_conf.mode;
252 fc->rx_pause = (fc_conf.mode == RTE_FC_FULL) ||
253 (fc_conf.mode == RTE_FC_RX_PAUSE);
254 fc->tx_pause = (fc_conf.mode == RTE_FC_FULL) ||
255 (fc_conf.mode == RTE_FC_TX_PAUSE);
262 nix_update_flow_ctrl_config(struct rte_eth_dev *eth_dev)
264 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
265 struct cnxk_fc_cfg *fc = &dev->fc_cfg;
266 struct rte_eth_fc_conf fc_cfg = {0};
268 if (roc_nix_is_vf_or_sdp(&dev->nix))
271 fc_cfg.mode = fc->mode;
273 /* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */
274 if (roc_model_is_cn96_ax() &&
275 dev->npc.switch_header_type != ROC_PRIV_FLAGS_HIGIG &&
276 (fc_cfg.mode == RTE_FC_FULL || fc_cfg.mode == RTE_FC_RX_PAUSE)) {
278 (fc_cfg.mode == RTE_FC_FULL ||
279 fc_cfg.mode == RTE_FC_TX_PAUSE) ?
280 RTE_FC_TX_PAUSE : RTE_FC_NONE;
283 return cnxk_nix_flow_ctrl_set(eth_dev, &fc_cfg);
287 cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev)
289 uint16_t port_id = dev->eth_dev->data->port_id;
290 struct rte_mbuf mb_def;
293 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
294 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
295 offsetof(struct rte_mbuf, data_off) !=
297 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
298 offsetof(struct rte_mbuf, data_off) !=
300 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
301 offsetof(struct rte_mbuf, data_off) !=
304 mb_def.data_off = RTE_PKTMBUF_HEADROOM +
305 (dev->ptp_en * CNXK_NIX_TIMESYNC_RX_OFFSET);
306 mb_def.port = port_id;
307 rte_mbuf_refcnt_set(&mb_def, 1);
309 /* Prevent compiler reordering: rearm_data covers previous fields */
310 rte_compiler_barrier();
311 tmp = (uint64_t *)&mb_def.rearm_data;
316 static inline uint8_t
317 nix_sq_max_sqe_sz(struct cnxk_eth_dev *dev)
320 * Maximum three segments can be supported with W8, Choose
321 * NIX_MAXSQESZ_W16 for multi segment offload.
323 if (dev->tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
324 return NIX_MAXSQESZ_W16;
326 return NIX_MAXSQESZ_W8;
330 cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
331 uint16_t nb_desc, uint16_t fp_tx_q_sz,
332 const struct rte_eth_txconf *tx_conf)
334 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
335 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
336 struct cnxk_eth_txq_sp *txq_sp;
337 struct roc_nix_sq *sq;
341 /* Free memory prior to re-allocation if needed. */
342 if (eth_dev->data->tx_queues[qid] != NULL) {
343 plt_nix_dbg("Freeing memory prior to re-allocation %d", qid);
344 dev_ops->tx_queue_release(eth_dev, qid);
345 eth_dev->data->tx_queues[qid] = NULL;
348 /* When Tx Security offload is enabled, increase tx desc count by
349 * max possible outbound desc count.
351 if (dev->tx_offloads & DEV_TX_OFFLOAD_SECURITY)
352 nb_desc += dev->outb.nb_desc;
357 sq->nb_desc = nb_desc;
358 sq->max_sqe_sz = nix_sq_max_sqe_sz(dev);
360 rc = roc_nix_sq_init(&dev->nix, sq);
362 plt_err("Failed to init sq=%d, rc=%d", qid, rc);
367 txq_sz = sizeof(struct cnxk_eth_txq_sp) + fp_tx_q_sz;
368 txq_sp = plt_zmalloc(txq_sz, PLT_CACHE_LINE_SIZE);
370 plt_err("Failed to alloc tx queue mem");
371 rc |= roc_nix_sq_fini(sq);
377 txq_sp->qconf.conf.tx = *tx_conf;
378 /* Queue config should reflect global offloads */
379 txq_sp->qconf.conf.tx.offloads = dev->tx_offloads;
380 txq_sp->qconf.nb_desc = nb_desc;
382 plt_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " lmt_addr=%p"
383 " nb_sqb_bufs=%d sqes_per_sqb_log2=%d",
384 qid, sq->fc, dev->tx_offloads, sq->lmt_addr,
385 sq->nb_sqb_bufs, sq->sqes_per_sqb_log2);
387 /* Store start of fast path area */
388 eth_dev->data->tx_queues[qid] = txq_sp + 1;
389 eth_dev->data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
394 cnxk_nix_tx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)
396 void *txq = eth_dev->data->tx_queues[qid];
397 struct cnxk_eth_txq_sp *txq_sp;
398 struct cnxk_eth_dev *dev;
399 struct roc_nix_sq *sq;
405 txq_sp = cnxk_eth_txq_to_sp(txq);
409 plt_nix_dbg("Releasing txq %u", qid);
413 rc = roc_nix_sq_fini(sq);
415 plt_err("Failed to cleanup sq, rc=%d", rc);
422 cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
423 uint16_t nb_desc, uint16_t fp_rx_q_sz,
424 const struct rte_eth_rxconf *rx_conf,
425 struct rte_mempool *mp)
427 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
428 struct roc_nix *nix = &dev->nix;
429 struct cnxk_eth_rxq_sp *rxq_sp;
430 struct rte_mempool_ops *ops;
431 const char *platform_ops;
432 struct roc_nix_rq *rq;
433 struct roc_nix_cq *cq;
439 if (rx_conf->rx_deferred_start == 1) {
440 plt_err("Deferred Rx start is not supported");
444 platform_ops = rte_mbuf_platform_mempool_ops();
445 /* This driver needs cnxk_npa mempool ops to work */
446 ops = rte_mempool_get_ops(mp->ops_index);
447 if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
448 plt_err("mempool ops should be of cnxk_npa type");
452 if (mp->pool_id == 0) {
453 plt_err("Invalid pool_id");
457 /* Free memory prior to re-allocation if needed */
458 if (eth_dev->data->rx_queues[qid] != NULL) {
459 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
461 plt_nix_dbg("Freeing memory prior to re-allocation %d", qid);
462 dev_ops->rx_queue_release(eth_dev, qid);
463 eth_dev->data->rx_queues[qid] = NULL;
466 /* Clam up cq limit to size of packet pool aura for LBK
467 * to avoid meta packet drop as LBK does not currently support
470 if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY && roc_nix_is_lbk(nix)) {
471 uint64_t pkt_pool_limit = roc_nix_inl_dev_rq_limit_get();
473 /* Use current RQ's aura limit if inl rq is not available */
475 pkt_pool_limit = roc_npa_aura_op_limit_get(mp->pool_id);
476 nb_desc = RTE_MAX(nb_desc, pkt_pool_limit);
482 cq->nb_desc = nb_desc;
483 rc = roc_nix_cq_init(&dev->nix, cq);
485 plt_err("Failed to init roc cq for rq=%d, rc=%d", qid, rc);
492 rq->aura_handle = mp->pool_id;
493 rq->flow_tag_width = 32;
496 /* Calculate first mbuf skip */
497 first_skip = (sizeof(struct rte_mbuf));
498 first_skip += RTE_PKTMBUF_HEADROOM;
499 first_skip += rte_pktmbuf_priv_size(mp);
500 rq->first_skip = first_skip;
501 rq->later_skip = sizeof(struct rte_mbuf);
502 rq->lpb_size = mp->elt_size;
504 /* Enable Inline IPSec on RQ, will not be used for Poll mode */
505 if (roc_nix_inl_inb_is_enabled(nix))
506 rq->ipsech_ena = true;
508 rc = roc_nix_rq_init(&dev->nix, rq, !!eth_dev->data->dev_started);
510 plt_err("Failed to init roc rq for rq=%d, rc=%d", qid, rc);
514 /* Allocate and setup fast path rx queue */
516 rxq_sz = sizeof(struct cnxk_eth_rxq_sp) + fp_rx_q_sz;
517 rxq_sp = plt_zmalloc(rxq_sz, PLT_CACHE_LINE_SIZE);
519 plt_err("Failed to alloc rx queue for rq=%d", qid);
523 /* Setup slow path fields */
526 rxq_sp->qconf.conf.rx = *rx_conf;
527 /* Queue config should reflect global offloads */
528 rxq_sp->qconf.conf.rx.offloads = dev->rx_offloads;
529 rxq_sp->qconf.nb_desc = nb_desc;
530 rxq_sp->qconf.mp = mp;
532 if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
533 /* Setup rq reference for inline dev if present */
534 rc = roc_nix_inl_dev_rq_get(rq);
539 plt_nix_dbg("rq=%d pool=%s nb_desc=%d->%d", qid, mp->name, nb_desc,
542 /* Store start of fast path area */
543 eth_dev->data->rx_queues[qid] = rxq_sp + 1;
544 eth_dev->data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
546 /* Calculating delta and freq mult between PTP HI clock and tsc.
547 * These are needed in deriving raw clock value from tsc counter.
548 * read_clock eth op returns raw clock value.
550 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) || dev->ptp_en) {
551 rc = cnxk_nix_tsc_convert(dev);
553 plt_err("Failed to calculate delta and freq mult");
562 rc |= roc_nix_rq_fini(rq);
564 rc |= roc_nix_cq_fini(cq);
570 cnxk_nix_rx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)
572 void *rxq = eth_dev->data->rx_queues[qid];
573 struct cnxk_eth_rxq_sp *rxq_sp;
574 struct cnxk_eth_dev *dev;
575 struct roc_nix_rq *rq;
576 struct roc_nix_cq *cq;
582 rxq_sp = cnxk_eth_rxq_to_sp(rxq);
586 plt_nix_dbg("Releasing rxq %u", qid);
588 /* Release rq reference for inline dev if present */
589 if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY)
590 roc_nix_inl_dev_rq_put(rq);
593 rc = roc_nix_rq_fini(rq);
595 plt_err("Failed to cleanup rq, rc=%d", rc);
599 rc = roc_nix_cq_fini(cq);
601 plt_err("Failed to cleanup cq, rc=%d", rc);
603 /* Finally free fast path area */
608 cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
611 uint32_t flow_key_type[RSS_MAX_LEVELS][6] = {
612 {FLOW_KEY_TYPE_IPV4, FLOW_KEY_TYPE_IPV6, FLOW_KEY_TYPE_TCP,
613 FLOW_KEY_TYPE_UDP, FLOW_KEY_TYPE_SCTP, FLOW_KEY_TYPE_ETH_DMAC},
614 {FLOW_KEY_TYPE_INNR_IPV4, FLOW_KEY_TYPE_INNR_IPV6,
615 FLOW_KEY_TYPE_INNR_TCP, FLOW_KEY_TYPE_INNR_UDP,
616 FLOW_KEY_TYPE_INNR_SCTP, FLOW_KEY_TYPE_INNR_ETH_DMAC},
617 {FLOW_KEY_TYPE_IPV4 | FLOW_KEY_TYPE_INNR_IPV4,
618 FLOW_KEY_TYPE_IPV6 | FLOW_KEY_TYPE_INNR_IPV6,
619 FLOW_KEY_TYPE_TCP | FLOW_KEY_TYPE_INNR_TCP,
620 FLOW_KEY_TYPE_UDP | FLOW_KEY_TYPE_INNR_UDP,
621 FLOW_KEY_TYPE_SCTP | FLOW_KEY_TYPE_INNR_SCTP,
622 FLOW_KEY_TYPE_ETH_DMAC | FLOW_KEY_TYPE_INNR_ETH_DMAC}
624 uint32_t flowkey_cfg = 0;
626 dev->ethdev_rss_hf = ethdev_rss;
628 if (ethdev_rss & ETH_RSS_L2_PAYLOAD &&
629 dev->npc.switch_header_type == ROC_PRIV_FLAGS_LEN_90B) {
630 flowkey_cfg |= FLOW_KEY_TYPE_CH_LEN_90B;
633 if (ethdev_rss & ETH_RSS_C_VLAN)
634 flowkey_cfg |= FLOW_KEY_TYPE_VLAN;
636 if (ethdev_rss & ETH_RSS_L3_SRC_ONLY)
637 flowkey_cfg |= FLOW_KEY_TYPE_L3_SRC;
639 if (ethdev_rss & ETH_RSS_L3_DST_ONLY)
640 flowkey_cfg |= FLOW_KEY_TYPE_L3_DST;
642 if (ethdev_rss & ETH_RSS_L4_SRC_ONLY)
643 flowkey_cfg |= FLOW_KEY_TYPE_L4_SRC;
645 if (ethdev_rss & ETH_RSS_L4_DST_ONLY)
646 flowkey_cfg |= FLOW_KEY_TYPE_L4_DST;
648 if (ethdev_rss & RSS_IPV4_ENABLE)
649 flowkey_cfg |= flow_key_type[rss_level][RSS_IPV4_INDEX];
651 if (ethdev_rss & RSS_IPV6_ENABLE)
652 flowkey_cfg |= flow_key_type[rss_level][RSS_IPV6_INDEX];
654 if (ethdev_rss & ETH_RSS_TCP)
655 flowkey_cfg |= flow_key_type[rss_level][RSS_TCP_INDEX];
657 if (ethdev_rss & ETH_RSS_UDP)
658 flowkey_cfg |= flow_key_type[rss_level][RSS_UDP_INDEX];
660 if (ethdev_rss & ETH_RSS_SCTP)
661 flowkey_cfg |= flow_key_type[rss_level][RSS_SCTP_INDEX];
663 if (ethdev_rss & ETH_RSS_L2_PAYLOAD)
664 flowkey_cfg |= flow_key_type[rss_level][RSS_DMAC_INDEX];
666 if (ethdev_rss & RSS_IPV6_EX_ENABLE)
667 flowkey_cfg |= FLOW_KEY_TYPE_IPV6_EXT;
669 if (ethdev_rss & ETH_RSS_PORT)
670 flowkey_cfg |= FLOW_KEY_TYPE_PORT;
672 if (ethdev_rss & ETH_RSS_NVGRE)
673 flowkey_cfg |= FLOW_KEY_TYPE_NVGRE;
675 if (ethdev_rss & ETH_RSS_VXLAN)
676 flowkey_cfg |= FLOW_KEY_TYPE_VXLAN;
678 if (ethdev_rss & ETH_RSS_GENEVE)
679 flowkey_cfg |= FLOW_KEY_TYPE_GENEVE;
681 if (ethdev_rss & ETH_RSS_GTPU)
682 flowkey_cfg |= FLOW_KEY_TYPE_GTPU;
688 nix_free_queue_mem(struct cnxk_eth_dev *dev)
699 nix_ingress_policer_setup(struct cnxk_eth_dev *dev)
701 TAILQ_INIT(&dev->mtr_profiles);
702 TAILQ_INIT(&dev->mtr_policy);
703 TAILQ_INIT(&dev->mtr);
709 nix_rss_default_setup(struct cnxk_eth_dev *dev)
711 struct rte_eth_dev *eth_dev = dev->eth_dev;
712 uint8_t rss_hash_level;
713 uint32_t flowkey_cfg;
716 rss_hf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
717 rss_hash_level = ETH_RSS_LEVEL(rss_hf);
721 flowkey_cfg = cnxk_rss_ethdev_to_nix(dev, rss_hf, rss_hash_level);
722 return roc_nix_rss_default_setup(&dev->nix, flowkey_cfg);
726 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
728 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
729 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
730 struct cnxk_eth_qconf *tx_qconf = NULL;
731 struct cnxk_eth_qconf *rx_qconf = NULL;
732 struct cnxk_eth_rxq_sp *rxq_sp;
733 struct cnxk_eth_txq_sp *txq_sp;
734 int i, nb_rxq, nb_txq;
737 nb_rxq = RTE_MIN(dev->nb_rxq, eth_dev->data->nb_rx_queues);
738 nb_txq = RTE_MIN(dev->nb_txq, eth_dev->data->nb_tx_queues);
740 tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
741 if (tx_qconf == NULL) {
742 plt_err("Failed to allocate memory for tx_qconf");
746 rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
747 if (rx_qconf == NULL) {
748 plt_err("Failed to allocate memory for rx_qconf");
752 txq = eth_dev->data->tx_queues;
753 for (i = 0; i < nb_txq; i++) {
754 if (txq[i] == NULL) {
755 tx_qconf[i].valid = false;
756 plt_info("txq[%d] is already released", i);
759 txq_sp = cnxk_eth_txq_to_sp(txq[i]);
760 memcpy(&tx_qconf[i], &txq_sp->qconf, sizeof(*tx_qconf));
761 tx_qconf[i].valid = true;
762 dev_ops->tx_queue_release(eth_dev, i);
763 eth_dev->data->tx_queues[i] = NULL;
766 rxq = eth_dev->data->rx_queues;
767 for (i = 0; i < nb_rxq; i++) {
768 if (rxq[i] == NULL) {
769 rx_qconf[i].valid = false;
770 plt_info("rxq[%d] is already released", i);
773 rxq_sp = cnxk_eth_rxq_to_sp(rxq[i]);
774 memcpy(&rx_qconf[i], &rxq_sp->qconf, sizeof(*rx_qconf));
775 rx_qconf[i].valid = true;
776 dev_ops->rx_queue_release(eth_dev, i);
777 eth_dev->data->rx_queues[i] = NULL;
780 dev->tx_qconf = tx_qconf;
781 dev->rx_qconf = rx_qconf;
791 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
793 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
794 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
795 struct cnxk_eth_qconf *tx_qconf = dev->tx_qconf;
796 struct cnxk_eth_qconf *rx_qconf = dev->rx_qconf;
797 int rc, i, nb_rxq, nb_txq;
799 nb_rxq = RTE_MIN(dev->nb_rxq, eth_dev->data->nb_rx_queues);
800 nb_txq = RTE_MIN(dev->nb_txq, eth_dev->data->nb_tx_queues);
803 /* Setup tx & rx queues with previous configuration so
804 * that the queues can be functional in cases like ports
805 * are started without re configuring queues.
807 * Usual re config sequence is like below:
813 * queue_configure() {
820 * In some application's control path, queue_configure() would
821 * NOT be invoked for TXQs/RXQs in port_configure().
822 * In such cases, queues can be functional after start as the
823 * queues are already setup in port_configure().
825 for (i = 0; i < nb_txq; i++) {
826 if (!tx_qconf[i].valid)
828 rc = dev_ops->tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc, 0,
829 &tx_qconf[i].conf.tx);
831 plt_err("Failed to setup tx queue rc=%d", rc);
832 for (i -= 1; i >= 0; i--)
833 dev_ops->tx_queue_release(eth_dev, i);
841 for (i = 0; i < nb_rxq; i++) {
842 if (!rx_qconf[i].valid)
844 rc = dev_ops->rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc, 0,
845 &rx_qconf[i].conf.rx,
848 plt_err("Failed to setup rx queue rc=%d", rc);
849 for (i -= 1; i >= 0; i--)
850 dev_ops->rx_queue_release(eth_dev, i);
851 goto tx_queue_release;
861 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
862 dev_ops->tx_queue_release(eth_dev, i);
873 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
883 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
885 /* These dummy functions are required for supporting
886 * some applications which reconfigure queues without
887 * stopping tx burst and rx burst threads(eg kni app)
888 * When the queues context is saved, txq/rxqs are released
889 * which caused app crash since rx/tx burst is still
890 * on different lcores
892 eth_dev->tx_pkt_burst = nix_eth_nop_burst;
893 eth_dev->rx_pkt_burst = nix_eth_nop_burst;
898 nix_lso_tun_fmt_update(struct cnxk_eth_dev *dev)
900 uint8_t udp_tun[ROC_NIX_LSO_TUN_MAX];
901 uint8_t tun[ROC_NIX_LSO_TUN_MAX];
902 struct roc_nix *nix = &dev->nix;
905 rc = roc_nix_lso_fmt_get(nix, udp_tun, tun);
909 dev->lso_tun_fmt = ((uint64_t)tun[ROC_NIX_LSO_TUN_V4V4] |
910 (uint64_t)tun[ROC_NIX_LSO_TUN_V4V6] << 8 |
911 (uint64_t)tun[ROC_NIX_LSO_TUN_V6V4] << 16 |
912 (uint64_t)tun[ROC_NIX_LSO_TUN_V6V6] << 24);
914 dev->lso_tun_fmt |= ((uint64_t)udp_tun[ROC_NIX_LSO_TUN_V4V4] << 32 |
915 (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V4V6] << 40 |
916 (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V6V4] << 48 |
917 (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V6V6] << 56);
922 nix_lso_fmt_setup(struct cnxk_eth_dev *dev)
924 struct roc_nix *nix = &dev->nix;
927 /* Nothing much to do if offload is not enabled */
928 if (!(dev->tx_offloads &
929 (DEV_TX_OFFLOAD_TCP_TSO | DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
930 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | DEV_TX_OFFLOAD_GRE_TNL_TSO)))
933 /* Setup LSO formats in AF. Its a no-op if other ethdev has
936 rc = roc_nix_lso_fmt_setup(nix);
940 return nix_lso_tun_fmt_update(dev);
944 cnxk_nix_configure(struct rte_eth_dev *eth_dev)
946 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
947 struct rte_eth_dev_data *data = eth_dev->data;
948 struct rte_eth_conf *conf = &data->dev_conf;
949 struct rte_eth_rxmode *rxmode = &conf->rxmode;
950 struct rte_eth_txmode *txmode = &conf->txmode;
951 char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
952 struct roc_nix_fc_cfg fc_cfg = {0};
953 struct roc_nix *nix = &dev->nix;
954 struct rte_ether_addr *ea;
955 uint8_t nb_rxq, nb_txq;
963 if (rte_eal_has_hugepages() == 0) {
964 plt_err("Huge page is not configured");
968 if (conf->dcb_capability_en == 1) {
969 plt_err("dcb enable is not supported");
973 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
974 plt_err("Flow director is not supported");
978 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
979 rxmode->mq_mode != ETH_MQ_RX_RSS) {
980 plt_err("Unsupported mq rx mode %d", rxmode->mq_mode);
984 if (txmode->mq_mode != ETH_MQ_TX_NONE) {
985 plt_err("Unsupported mq tx mode %d", txmode->mq_mode);
989 /* Free the resources allocated from the previous configure */
990 if (dev->configured == 1) {
991 /* Unregister queue irq's */
992 roc_nix_unregister_queue_irqs(nix);
994 /* Unregister CQ irqs if present */
995 if (eth_dev->data->dev_conf.intr_conf.rxq)
996 roc_nix_unregister_cq_irqs(nix);
998 /* Set no-op functions */
999 nix_set_nop_rxtx_function(eth_dev);
1000 /* Store queue config for later */
1001 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1003 goto fail_configure;
1005 /* Cleanup security support */
1006 rc = nix_security_release(dev);
1008 goto fail_configure;
1010 roc_nix_tm_fini(nix);
1011 roc_nix_lf_free(nix);
1014 dev->rx_offloads = rxmode->offloads;
1015 dev->tx_offloads = txmode->offloads;
1017 /* Prepare rx cfg */
1018 rx_cfg = ROC_NIX_LF_RX_CFG_DIS_APAD;
1019 if (dev->rx_offloads &
1020 (DEV_RX_OFFLOAD_TCP_CKSUM | DEV_RX_OFFLOAD_UDP_CKSUM)) {
1021 rx_cfg |= ROC_NIX_LF_RX_CFG_CSUM_OL4;
1022 rx_cfg |= ROC_NIX_LF_RX_CFG_CSUM_IL4;
1024 rx_cfg |= (ROC_NIX_LF_RX_CFG_DROP_RE | ROC_NIX_LF_RX_CFG_L2_LEN_ERR |
1025 ROC_NIX_LF_RX_CFG_LEN_IL4 | ROC_NIX_LF_RX_CFG_LEN_IL3 |
1026 ROC_NIX_LF_RX_CFG_LEN_OL4 | ROC_NIX_LF_RX_CFG_LEN_OL3);
1028 if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
1029 rx_cfg |= ROC_NIX_LF_RX_CFG_IP6_UDP_OPT;
1030 /* Disable drop re if rx offload security is enabled and
1031 * platform does not support it.
1033 if (dev->ipsecd_drop_re_dis)
1034 rx_cfg &= ~(ROC_NIX_LF_RX_CFG_DROP_RE);
1037 nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1038 nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1040 /* Alloc a nix lf */
1041 rc = roc_nix_lf_alloc(nix, nb_rxq, nb_txq, rx_cfg);
1043 plt_err("Failed to init nix_lf rc=%d", rc);
1044 goto fail_configure;
1047 dev->npc.channel = roc_nix_get_base_chan(nix);
1049 nb_rxq = data->nb_rx_queues;
1050 nb_txq = data->nb_tx_queues;
1053 /* Allocate memory for roc rq's and cq's */
1054 qs = plt_zmalloc(sizeof(struct roc_nix_rq) * nb_rxq, 0);
1056 plt_err("Failed to alloc rqs");
1061 qs = plt_zmalloc(sizeof(struct roc_nix_cq) * nb_rxq, 0);
1063 plt_err("Failed to alloc cqs");
1070 /* Allocate memory for roc sq's */
1071 qs = plt_zmalloc(sizeof(struct roc_nix_sq) * nb_txq, 0);
1073 plt_err("Failed to alloc sqs");
1079 /* Re-enable NIX LF error interrupts */
1080 roc_nix_err_intr_ena_dis(nix, true);
1081 roc_nix_ras_intr_ena_dis(nix, true);
1083 if (nix->rx_ptp_ena &&
1084 dev->npc.switch_header_type == ROC_PRIV_FLAGS_HIGIG) {
1085 plt_err("Both PTP and switch header enabled");
1089 rc = roc_nix_switch_hdr_set(nix, dev->npc.switch_header_type);
1091 plt_err("Failed to enable switch type nix_lf rc=%d", rc);
1095 /* Setup LSO if needed */
1096 rc = nix_lso_fmt_setup(dev);
1098 plt_err("Failed to setup nix lso format fields, rc=%d", rc);
1103 rc = nix_rss_default_setup(dev);
1105 plt_err("Failed to configure rss rc=%d", rc);
1109 /* Init the default TM scheduler hierarchy */
1110 rc = roc_nix_tm_init(nix);
1112 plt_err("Failed to init traffic manager, rc=%d", rc);
1116 rc = nix_ingress_policer_setup(dev);
1118 plt_err("Failed to setup ingress policer rc=%d", rc);
1122 rc = roc_nix_tm_hierarchy_enable(nix, ROC_NIX_TM_DEFAULT, false);
1124 plt_err("Failed to enable default tm hierarchy, rc=%d", rc);
1128 /* Register queue IRQs */
1129 rc = roc_nix_register_queue_irqs(nix);
1131 plt_err("Failed to register queue interrupts rc=%d", rc);
1135 /* Register cq IRQs */
1136 if (eth_dev->data->dev_conf.intr_conf.rxq) {
1137 if (eth_dev->data->nb_rx_queues > dev->nix.cints) {
1138 plt_err("Rx interrupt cannot be enabled, rxq > %d",
1142 /* Rx interrupt feature cannot work with vector mode because,
1143 * vector mode does not process packets unless min 4 pkts are
1144 * received, while cq interrupts are generated even for 1 pkt
1147 dev->scalar_ena = true;
1149 rc = roc_nix_register_cq_irqs(nix);
1151 plt_err("Failed to register CQ interrupts rc=%d", rc);
1156 /* Configure loop back mode */
1157 rc = roc_nix_mac_loopback_enable(nix,
1158 eth_dev->data->dev_conf.lpbk_mode);
1160 plt_err("Failed to configure cgx loop back mode rc=%d", rc);
1164 /* Init flow control configuration */
1165 fc_cfg.cq_cfg_valid = false;
1166 fc_cfg.rxchan_cfg.enable = true;
1167 rc = roc_nix_fc_config_set(nix, &fc_cfg);
1169 plt_err("Failed to initialize flow control rc=%d", rc);
1173 /* Update flow control configuration to PMD */
1174 rc = nix_init_flow_ctrl_config(eth_dev);
1176 plt_err("Failed to initialize flow control rc=%d", rc);
1180 /* Setup Inline security support */
1181 rc = nix_security_setup(dev);
1186 * Restore queue config when reconfigure followed by
1187 * reconfigure and no queue configure invoked from application case.
1189 if (dev->configured == 1) {
1190 rc = nix_restore_queue_cfg(eth_dev);
1195 /* Update the mac address */
1196 ea = eth_dev->data->mac_addrs;
1197 memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1198 if (rte_is_zero_ether_addr(ea))
1199 rte_eth_random_addr((uint8_t *)ea);
1201 rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
1203 plt_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
1204 " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 "",
1205 eth_dev->data->port_id, ea_fmt, nb_rxq, nb_txq,
1206 dev->rx_offloads, dev->tx_offloads);
1209 dev->configured = 1;
1210 dev->nb_rxq = data->nb_rx_queues;
1211 dev->nb_txq = data->nb_tx_queues;
1215 rc |= nix_security_release(dev);
1217 roc_nix_unregister_cq_irqs(nix);
1219 roc_nix_unregister_queue_irqs(nix);
1221 roc_nix_tm_fini(nix);
1223 nix_free_queue_mem(dev);
1224 rc |= roc_nix_lf_free(nix);
1226 dev->configured = 0;
1231 cnxk_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid)
1233 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1234 struct rte_eth_dev_data *data = eth_dev->data;
1235 struct roc_nix_sq *sq = &dev->sqs[qid];
1238 if (data->tx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STARTED)
1241 rc = roc_nix_tm_sq_aura_fc(sq, true);
1243 plt_err("Failed to enable sq aura fc, txq=%u, rc=%d", qid, rc);
1247 data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STARTED;
1253 cnxk_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid)
1255 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1256 struct rte_eth_dev_data *data = eth_dev->data;
1257 struct roc_nix_sq *sq = &dev->sqs[qid];
1260 if (data->tx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STOPPED)
1263 rc = roc_nix_tm_sq_aura_fc(sq, false);
1265 plt_err("Failed to disable sqb aura fc, txq=%u, rc=%d", qid,
1270 data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
1276 cnxk_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid)
1278 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1279 struct rte_eth_dev_data *data = eth_dev->data;
1280 struct roc_nix_rq *rq = &dev->rqs[qid];
1283 if (data->rx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STARTED)
1286 rc = roc_nix_rq_ena_dis(rq, true);
1288 plt_err("Failed to enable rxq=%u, rc=%d", qid, rc);
1292 data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STARTED;
1298 cnxk_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid)
1300 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1301 struct rte_eth_dev_data *data = eth_dev->data;
1302 struct roc_nix_rq *rq = &dev->rqs[qid];
1305 if (data->rx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STOPPED)
1308 rc = roc_nix_rq_ena_dis(rq, false);
1310 plt_err("Failed to disable rxq=%u, rc=%d", qid, rc);
1314 data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
1320 cnxk_nix_dev_stop(struct rte_eth_dev *eth_dev)
1322 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1323 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
1324 struct rte_mbuf *rx_pkts[32];
1325 struct rte_eth_link link;
1326 int count, i, j, rc;
1329 /* Disable switch hdr pkind */
1330 roc_nix_switch_hdr_set(&dev->nix, 0);
1332 /* Stop link change events */
1333 if (!roc_nix_is_vf_or_sdp(&dev->nix))
1334 roc_nix_mac_link_event_start_stop(&dev->nix, false);
1336 /* Disable Rx via NPC */
1337 roc_nix_npc_rx_ena_dis(&dev->nix, false);
1339 /* Stop rx queues and free up pkts pending */
1340 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1341 rc = dev_ops->rx_queue_stop(eth_dev, i);
1345 rxq = eth_dev->data->rx_queues[i];
1346 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1348 for (j = 0; j < count; j++)
1349 rte_pktmbuf_free(rx_pkts[j]);
1350 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1354 /* Stop tx queues */
1355 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1356 dev_ops->tx_queue_stop(eth_dev, i);
1358 /* Bring down link status internally */
1359 memset(&link, 0, sizeof(link));
1360 rte_eth_linkstatus_set(eth_dev, &link);
1366 cnxk_nix_dev_start(struct rte_eth_dev *eth_dev)
1368 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1371 if (eth_dev->data->nb_rx_queues != 0 && !dev->ptp_en) {
1372 rc = nix_recalc_mtu(eth_dev);
1377 /* Start rx queues */
1378 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1379 rc = cnxk_nix_rx_queue_start(eth_dev, i);
1384 /* Start tx queues */
1385 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1386 rc = cnxk_nix_tx_queue_start(eth_dev, i);
1391 /* Update Flow control configuration */
1392 rc = nix_update_flow_ctrl_config(eth_dev);
1394 plt_err("Failed to enable flow control. error code(%d)", rc);
1398 /* Enable Rx in NPC */
1399 rc = roc_nix_npc_rx_ena_dis(&dev->nix, true);
1401 plt_err("Failed to enable NPC rx %d", rc);
1405 cnxk_nix_toggle_flag_link_cfg(dev, true);
1407 /* Start link change events */
1408 if (!roc_nix_is_vf_or_sdp(&dev->nix)) {
1409 rc = roc_nix_mac_link_event_start_stop(&dev->nix, true);
1411 plt_err("Failed to start cgx link event %d", rc);
1416 /* Enable PTP if it is requested by the user or already
1417 * enabled on PF owning this VF
1419 memset(&dev->tstamp, 0, sizeof(struct cnxk_timesync_info));
1420 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) || dev->ptp_en)
1421 cnxk_eth_dev_ops.timesync_enable(eth_dev);
1423 cnxk_eth_dev_ops.timesync_disable(eth_dev);
1425 if (dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) {
1426 rc = rte_mbuf_dyn_rx_timestamp_register
1427 (&dev->tstamp.tstamp_dynfield_offset,
1428 &dev->tstamp.rx_tstamp_dynflag);
1430 plt_err("Failed to register Rx timestamp field/flag");
1435 cnxk_nix_toggle_flag_link_cfg(dev, false);
1440 roc_nix_npc_rx_ena_dis(&dev->nix, false);
1441 cnxk_nix_toggle_flag_link_cfg(dev, false);
1445 static int cnxk_nix_dev_reset(struct rte_eth_dev *eth_dev);
1446 static int cnxk_nix_dev_close(struct rte_eth_dev *eth_dev);
1448 /* CNXK platform independent eth dev ops */
1449 struct eth_dev_ops cnxk_eth_dev_ops = {
1450 .mtu_set = cnxk_nix_mtu_set,
1451 .mac_addr_add = cnxk_nix_mac_addr_add,
1452 .mac_addr_remove = cnxk_nix_mac_addr_del,
1453 .mac_addr_set = cnxk_nix_mac_addr_set,
1454 .dev_infos_get = cnxk_nix_info_get,
1455 .link_update = cnxk_nix_link_update,
1456 .tx_queue_release = cnxk_nix_tx_queue_release,
1457 .rx_queue_release = cnxk_nix_rx_queue_release,
1458 .dev_stop = cnxk_nix_dev_stop,
1459 .dev_close = cnxk_nix_dev_close,
1460 .dev_reset = cnxk_nix_dev_reset,
1461 .tx_queue_start = cnxk_nix_tx_queue_start,
1462 .rx_queue_start = cnxk_nix_rx_queue_start,
1463 .rx_queue_stop = cnxk_nix_rx_queue_stop,
1464 .dev_supported_ptypes_get = cnxk_nix_supported_ptypes_get,
1465 .promiscuous_enable = cnxk_nix_promisc_enable,
1466 .promiscuous_disable = cnxk_nix_promisc_disable,
1467 .allmulticast_enable = cnxk_nix_allmulticast_enable,
1468 .allmulticast_disable = cnxk_nix_allmulticast_disable,
1469 .rx_burst_mode_get = cnxk_nix_rx_burst_mode_get,
1470 .tx_burst_mode_get = cnxk_nix_tx_burst_mode_get,
1471 .flow_ctrl_get = cnxk_nix_flow_ctrl_get,
1472 .flow_ctrl_set = cnxk_nix_flow_ctrl_set,
1473 .dev_set_link_up = cnxk_nix_set_link_up,
1474 .dev_set_link_down = cnxk_nix_set_link_down,
1475 .get_module_info = cnxk_nix_get_module_info,
1476 .get_module_eeprom = cnxk_nix_get_module_eeprom,
1477 .rx_queue_intr_enable = cnxk_nix_rx_queue_intr_enable,
1478 .rx_queue_intr_disable = cnxk_nix_rx_queue_intr_disable,
1479 .pool_ops_supported = cnxk_nix_pool_ops_supported,
1480 .queue_stats_mapping_set = cnxk_nix_queue_stats_mapping,
1481 .stats_get = cnxk_nix_stats_get,
1482 .stats_reset = cnxk_nix_stats_reset,
1483 .xstats_get = cnxk_nix_xstats_get,
1484 .xstats_get_names = cnxk_nix_xstats_get_names,
1485 .xstats_reset = cnxk_nix_xstats_reset,
1486 .xstats_get_by_id = cnxk_nix_xstats_get_by_id,
1487 .xstats_get_names_by_id = cnxk_nix_xstats_get_names_by_id,
1488 .fw_version_get = cnxk_nix_fw_version_get,
1489 .rxq_info_get = cnxk_nix_rxq_info_get,
1490 .txq_info_get = cnxk_nix_txq_info_get,
1491 .tx_done_cleanup = cnxk_nix_tx_done_cleanup,
1492 .flow_ops_get = cnxk_nix_flow_ops_get,
1493 .get_reg = cnxk_nix_dev_get_reg,
1494 .timesync_read_rx_timestamp = cnxk_nix_timesync_read_rx_timestamp,
1495 .timesync_read_tx_timestamp = cnxk_nix_timesync_read_tx_timestamp,
1496 .timesync_read_time = cnxk_nix_timesync_read_time,
1497 .timesync_write_time = cnxk_nix_timesync_write_time,
1498 .timesync_adjust_time = cnxk_nix_timesync_adjust_time,
1499 .read_clock = cnxk_nix_read_clock,
1500 .reta_update = cnxk_nix_reta_update,
1501 .reta_query = cnxk_nix_reta_query,
1502 .rss_hash_update = cnxk_nix_rss_hash_update,
1503 .rss_hash_conf_get = cnxk_nix_rss_hash_conf_get,
1504 .set_mc_addr_list = cnxk_nix_mc_addr_list_configure,
1505 .set_queue_rate_limit = cnxk_nix_tm_set_queue_rate_limit,
1506 .tm_ops_get = cnxk_nix_tm_ops_get,
1507 .mtr_ops_get = cnxk_nix_mtr_ops_get,
1511 cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)
1513 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1514 struct rte_security_ctx *sec_ctx;
1515 struct roc_nix *nix = &dev->nix;
1516 struct rte_pci_device *pci_dev;
1517 int rc, max_entries;
1519 eth_dev->dev_ops = &cnxk_eth_dev_ops;
1521 /* Alloc security context */
1522 sec_ctx = plt_zmalloc(sizeof(struct rte_security_ctx), 0);
1525 sec_ctx->device = eth_dev;
1526 sec_ctx->ops = &cnxk_eth_sec_ops;
1528 (RTE_SEC_CTX_F_FAST_SET_MDATA | RTE_SEC_CTX_F_FAST_GET_UDATA);
1529 eth_dev->security_ctx = sec_ctx;
1530 TAILQ_INIT(&dev->inb.list);
1531 TAILQ_INIT(&dev->outb.list);
1533 /* For secondary processes, the primary has done all the work */
1534 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1537 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1538 rte_eth_copy_pci_info(eth_dev, pci_dev);
1540 /* Parse devargs string */
1541 rc = cnxk_ethdev_parse_devargs(eth_dev->device->devargs, dev);
1543 plt_err("Failed to parse devargs rc=%d", rc);
1547 /* Initialize base roc nix */
1548 nix->pci_dev = pci_dev;
1549 nix->hw_vlan_ins = true;
1550 rc = roc_nix_dev_init(nix);
1552 plt_err("Failed to initialize roc nix rc=%d", rc);
1556 /* Register up msg callbacks */
1557 roc_nix_mac_link_cb_register(nix, cnxk_eth_dev_link_status_cb);
1559 /* Register up msg callbacks */
1560 roc_nix_mac_link_info_get_cb_register(nix,
1561 cnxk_eth_dev_link_status_get_cb);
1563 dev->eth_dev = eth_dev;
1564 dev->configured = 0;
1565 dev->ptype_disable = 0;
1567 /* For vfs, returned max_entries will be 0. but to keep default mac
1568 * address, one entry must be allocated. so setting up to 1.
1570 if (roc_nix_is_vf_or_sdp(nix))
1573 max_entries = roc_nix_mac_max_entries_get(nix);
1575 if (max_entries <= 0) {
1576 plt_err("Failed to get max entries for mac addr");
1581 eth_dev->data->mac_addrs =
1582 rte_zmalloc("mac_addr", max_entries * RTE_ETHER_ADDR_LEN, 0);
1583 if (eth_dev->data->mac_addrs == NULL) {
1584 plt_err("Failed to allocate memory for mac addr");
1589 dev->max_mac_entries = max_entries;
1590 dev->dmac_filter_count = 1;
1592 /* Get mac address */
1593 rc = roc_nix_npc_mac_addr_get(nix, dev->mac_addr);
1595 plt_err("Failed to get mac addr, rc=%d", rc);
1596 goto free_mac_addrs;
1599 /* Update the mac address */
1600 memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1602 if (!roc_nix_is_vf_or_sdp(nix)) {
1603 /* Sync same MAC address to CGX/RPM table */
1604 rc = roc_nix_mac_addr_set(nix, dev->mac_addr);
1606 plt_err("Failed to set mac addr, rc=%d", rc);
1607 goto free_mac_addrs;
1611 /* Union of all capabilities supported by CNXK.
1612 * Platform specific capabilities will be
1615 dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
1616 dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
1617 dev->speed_capa = nix_get_speed_capa(dev);
1619 /* Initialize roc npc */
1620 dev->npc.roc_nix = nix;
1621 rc = roc_npc_init(&dev->npc);
1623 goto free_mac_addrs;
1625 plt_nix_dbg("Port=%d pf=%d vf=%d ver=%s hwcap=0x%" PRIx64
1626 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
1627 eth_dev->data->port_id, roc_nix_get_pf(nix),
1628 roc_nix_get_vf(nix), CNXK_ETH_DEV_PMD_VERSION, dev->hwcap,
1629 dev->rx_offload_capa, dev->tx_offload_capa);
1633 rte_free(eth_dev->data->mac_addrs);
1635 roc_nix_dev_fini(nix);
1637 plt_err("Failed to init nix eth_dev rc=%d", rc);
1642 cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool reset)
1644 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1645 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
1646 struct roc_nix *nix = &dev->nix;
1649 plt_free(eth_dev->security_ctx);
1650 eth_dev->security_ctx = NULL;
1652 /* Nothing to be done for secondary processes */
1653 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1656 /* Clear the flag since we are closing down */
1657 dev->configured = 0;
1659 roc_nix_npc_rx_ena_dis(nix, false);
1661 /* Disable and free rte_flow entries */
1662 roc_npc_fini(&dev->npc);
1664 /* Disable link status events */
1665 roc_nix_mac_link_event_start_stop(nix, false);
1667 /* Unregister the link update op, this is required to stop VFs from
1668 * receiving link status updates on exit path.
1670 roc_nix_mac_link_cb_unregister(nix);
1673 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1674 dev_ops->tx_queue_release(eth_dev, i);
1675 eth_dev->data->tx_queues[i] = NULL;
1677 eth_dev->data->nb_tx_queues = 0;
1679 /* Free up RQ's and CQ's */
1680 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1681 dev_ops->rx_queue_release(eth_dev, i);
1682 eth_dev->data->rx_queues[i] = NULL;
1684 eth_dev->data->nb_rx_queues = 0;
1686 /* Free security resources */
1687 nix_security_release(dev);
1689 /* Free tm resources */
1690 roc_nix_tm_fini(nix);
1692 /* Unregister queue irqs */
1693 roc_nix_unregister_queue_irqs(nix);
1695 /* Unregister cq irqs */
1696 if (eth_dev->data->dev_conf.intr_conf.rxq)
1697 roc_nix_unregister_cq_irqs(nix);
1699 /* Free ROC RQ's, SQ's and CQ's memory */
1700 nix_free_queue_mem(dev);
1702 /* Free nix lf resources */
1703 rc = roc_nix_lf_free(nix);
1705 plt_err("Failed to free nix lf, rc=%d", rc);
1707 rte_free(eth_dev->data->mac_addrs);
1708 eth_dev->data->mac_addrs = NULL;
1710 rc = roc_nix_dev_fini(nix);
1711 /* Can be freed later by PMD if NPA LF is in use */
1712 if (rc == -EAGAIN) {
1714 eth_dev->data->dev_private = NULL;
1717 plt_err("Failed in nix dev fini, rc=%d", rc);
1724 cnxk_nix_dev_close(struct rte_eth_dev *eth_dev)
1726 cnxk_eth_dev_uninit(eth_dev, false);
1731 cnxk_nix_dev_reset(struct rte_eth_dev *eth_dev)
1735 rc = cnxk_eth_dev_uninit(eth_dev, true);
1739 return cnxk_eth_dev_init(eth_dev);
1743 cnxk_nix_remove(struct rte_pci_device *pci_dev)
1745 struct rte_eth_dev *eth_dev;
1746 struct roc_nix *nix;
1749 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
1751 /* Cleanup eth dev */
1752 rc = cnxk_eth_dev_uninit(eth_dev, false);
1756 rte_eth_dev_release_port(eth_dev);
1759 /* Nothing to be done for secondary processes */
1760 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1763 /* Check if this device is hosting common resource */
1764 nix = roc_idev_npa_nix_get();
1765 if (nix->pci_dev != pci_dev)
1768 /* Try nix fini now */
1769 rc = roc_nix_dev_fini(nix);
1770 if (rc == -EAGAIN) {
1771 plt_info("%s: common resource in use by other devices",
1775 plt_err("Failed in nix dev fini, rc=%d", rc);
1779 /* Free device pointer as rte_ethdev does not have it anymore */
1786 cnxk_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1790 RTE_SET_USED(pci_drv);
1792 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct cnxk_eth_dev),
1795 /* On error on secondary, recheck if port exists in primary or
1796 * in mid of detach state.
1798 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
1799 if (!rte_eth_dev_allocated(pci_dev->device.name))