drivers/net/cnxk/cnxk_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4 #include <cnxk_ethdev.h>
   5
   6 static inline uint64_t
   7 nix_get_rx_offload_capa(struct cnxk_eth_dev *dev)
   8 {
   9         uint64_t capa = CNXK_NIX_RX_OFFLOAD_CAPA;
  10
  11         if (roc_nix_is_vf_or_sdp(&dev->nix) ||
  12             dev->npc.switch_header_type == ROC_PRIV_FLAGS_HIGIG)
  13                 capa &= ~RTE_ETH_RX_OFFLOAD_TIMESTAMP;
  14
  15         return capa;
  16 }
  17
  18 static inline uint64_t
  19 nix_get_tx_offload_capa(struct cnxk_eth_dev *dev)
  20 {
  21         RTE_SET_USED(dev);
  22         return CNXK_NIX_TX_OFFLOAD_CAPA;
  23 }
  24
  25 static inline uint32_t
  26 nix_get_speed_capa(struct cnxk_eth_dev *dev)
  27 {
  28         uint32_t speed_capa;
  29
  30         /* Auto negotiation disabled */
  31         speed_capa = RTE_ETH_LINK_SPEED_FIXED;
  32         if (!roc_nix_is_vf_or_sdp(&dev->nix) && !roc_nix_is_lbk(&dev->nix)) {
  33                 speed_capa |= RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G |
  34                               RTE_ETH_LINK_SPEED_25G | RTE_ETH_LINK_SPEED_40G |
  35                               RTE_ETH_LINK_SPEED_50G | RTE_ETH_LINK_SPEED_100G;
  36         }
  37
  38         return speed_capa;
  39 }
  40
  41 int
  42 cnxk_nix_inb_mode_set(struct cnxk_eth_dev *dev, bool use_inl_dev)
  43 {
  44         struct roc_nix *nix = &dev->nix;
  45
  46         if (dev->inb.inl_dev == use_inl_dev)
  47                 return 0;
  48
  49         plt_nix_dbg("Security sessions(%u) still active, inl=%u!!!",
  50                     dev->inb.nb_sess, !!dev->inb.inl_dev);
  51
  52         /* Change the mode */
  53         dev->inb.inl_dev = use_inl_dev;
  54
  55         /* Update RoC for NPC rule insertion */
  56         roc_nix_inb_mode_set(nix, use_inl_dev);
  57
  58         /* Setup lookup mem */
  59         return cnxk_nix_lookup_mem_sa_base_set(dev);
  60 }
  61
  62 static int
  63 nix_security_setup(struct cnxk_eth_dev *dev)
  64 {
  65         struct roc_nix *nix = &dev->nix;
  66         int i, rc = 0;
  67
  68         if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
  69                 /* Setup Inline Inbound */
  70                 rc = roc_nix_inl_inb_init(nix);
  71                 if (rc) {
  72                         plt_err("Failed to initialize nix inline inb, rc=%d",
  73                                 rc);
  74                         return rc;
  75                 }
  76
  77                 /* By default pick using inline device for poll mode.
  78                  * Will be overridden when event mode rq's are setup.
  79                  */
  80                 cnxk_nix_inb_mode_set(dev, true);
  81
  82                 /* Allocate memory to be used as dptr for CPT ucode
  83                  * WRITE_SA op.
  84                  */
  85                 dev->inb.sa_dptr =
  86                         plt_zmalloc(ROC_NIX_INL_OT_IPSEC_INB_HW_SZ, 0);
  87                 if (!dev->inb.sa_dptr) {
  88                         plt_err("Couldn't allocate memory for SA dptr");
  89                         rc = -ENOMEM;
  90                         goto cleanup;
  91                 }
  92         }
  93
  94         if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY ||
  95             dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
  96                 struct plt_bitmap *bmap;
  97                 size_t bmap_sz;
  98                 void *mem;
  99
 100                 /* Setup enough descriptors for all tx queues */
 101                 nix->outb_nb_desc = dev->outb.nb_desc;
 102                 nix->outb_nb_crypto_qs = dev->outb.nb_crypto_qs;
 103
 104                 /* Setup Inline Outbound */
 105                 rc = roc_nix_inl_outb_init(nix);
 106                 if (rc) {
 107                         plt_err("Failed to initialize nix inline outb, rc=%d",
 108                                 rc);
 109                         goto sa_dptr_free;
 110                 }
 111
 112                 dev->outb.lf_base = roc_nix_inl_outb_lf_base_get(nix);
 113
 114                 /* Skip the rest if DEV_TX_OFFLOAD_SECURITY is not enabled */
 115                 if (!(dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY))
 116                         return 0;
 117
 118                 /* Allocate memory to be used as dptr for CPT ucode
 119                  * WRITE_SA op.
 120                  */
 121                 dev->outb.sa_dptr =
 122                         plt_zmalloc(ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ, 0);
 123                 if (!dev->outb.sa_dptr) {
 124                         plt_err("Couldn't allocate memory for SA dptr");
 125                         rc = -ENOMEM;
 126                         goto sa_dptr_free;
 127                 }
 128
 129                 rc = -ENOMEM;
 130                 /* Allocate a bitmap to alloc and free sa indexes */
 131                 bmap_sz = plt_bitmap_get_memory_footprint(dev->outb.max_sa);
 132                 mem = plt_zmalloc(bmap_sz, PLT_CACHE_LINE_SIZE);
 133                 if (mem == NULL) {
 134                         plt_err("Outbound SA bmap alloc failed");
 135
 136                         rc |= roc_nix_inl_outb_fini(nix);
 137                         goto sa_dptr_free;
 138                 }
 139
 140                 rc = -EIO;
 141                 bmap = plt_bitmap_init(dev->outb.max_sa, mem, bmap_sz);
 142                 if (!bmap) {
 143                         plt_err("Outbound SA bmap init failed");
 144
 145                         rc |= roc_nix_inl_outb_fini(nix);
 146                         plt_free(mem);
 147                         goto sa_dptr_free;
 148                 }
 149
 150                 for (i = 0; i < dev->outb.max_sa; i++)
 151                         plt_bitmap_set(bmap, i);
 152
 153                 dev->outb.sa_base = roc_nix_inl_outb_sa_base_get(nix);
 154                 dev->outb.sa_bmap_mem = mem;
 155                 dev->outb.sa_bmap = bmap;
 156         }
 157         return 0;
 158
 159 sa_dptr_free:
 160         if (dev->inb.sa_dptr)
 161                 plt_free(dev->inb.sa_dptr);
 162         if (dev->outb.sa_dptr)
 163                 plt_free(dev->outb.sa_dptr);
 164 cleanup:
 165         if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)
 166                 rc |= roc_nix_inl_inb_fini(nix);
 167         return rc;
 168 }
 169
 170 static int
 171 nix_meter_fini(struct cnxk_eth_dev *dev)
 172 {
 173         struct cnxk_meter_node *next_mtr = NULL;
 174         struct roc_nix_bpf_objs profs = {0};
 175         struct cnxk_meter_node *mtr = NULL;
 176         struct cnxk_mtr *fms = &dev->mtr;
 177         struct roc_nix *nix = &dev->nix;
 178         struct roc_nix_rq *rq;
 179         uint32_t i;
 180         int rc;
 181
 182         RTE_TAILQ_FOREACH_SAFE(mtr, fms, next, next_mtr) {
 183                 for (i = 0; i < mtr->rq_num; i++) {
 184                         rq = &dev->rqs[mtr->rq_id[i]];
 185                         rc |= roc_nix_bpf_ena_dis(nix, mtr->bpf_id, rq, false);
 186                 }
 187
 188                 profs.level = mtr->level;
 189                 profs.count = 1;
 190                 profs.ids[0] = mtr->bpf_id;
 191                 rc = roc_nix_bpf_free(nix, &profs, 1);
 192
 193                 if (rc)
 194                         return rc;
 195
 196                 TAILQ_REMOVE(fms, mtr, next);
 197                 plt_free(mtr);
 198         }
 199         return 0;
 200 }
 201
 202 static int
 203 nix_security_release(struct cnxk_eth_dev *dev)
 204 {
 205         struct rte_eth_dev *eth_dev = dev->eth_dev;
 206         struct cnxk_eth_sec_sess *eth_sec, *tvar;
 207         struct roc_nix *nix = &dev->nix;
 208         int rc, ret = 0;
 209
 210         /* Cleanup Inline inbound */
 211         if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
 212                 /* Destroy inbound sessions */
 213                 tvar = NULL;
 214                 RTE_TAILQ_FOREACH_SAFE(eth_sec, &dev->inb.list, entry, tvar)
 215                         cnxk_eth_sec_ops.session_destroy(eth_dev,
 216                                                          eth_sec->sess);
 217
 218                 /* Clear lookup mem */
 219                 cnxk_nix_lookup_mem_sa_base_clear(dev);
 220
 221                 rc = roc_nix_inl_inb_fini(nix);
 222                 if (rc)
 223                         plt_err("Failed to cleanup nix inline inb, rc=%d", rc);
 224                 ret |= rc;
 225
 226                 if (dev->inb.sa_dptr) {
 227                         plt_free(dev->inb.sa_dptr);
 228                         dev->inb.sa_dptr = NULL;
 229                 }
 230         }
 231
 232         /* Cleanup Inline outbound */
 233         if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY ||
 234             dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
 235                 /* Destroy outbound sessions */
 236                 tvar = NULL;
 237                 RTE_TAILQ_FOREACH_SAFE(eth_sec, &dev->outb.list, entry, tvar)
 238                         cnxk_eth_sec_ops.session_destroy(eth_dev,
 239                                                          eth_sec->sess);
 240
 241                 rc = roc_nix_inl_outb_fini(nix);
 242                 if (rc)
 243                         plt_err("Failed to cleanup nix inline outb, rc=%d", rc);
 244                 ret |= rc;
 245
 246                 plt_bitmap_free(dev->outb.sa_bmap);
 247                 plt_free(dev->outb.sa_bmap_mem);
 248                 dev->outb.sa_bmap = NULL;
 249                 dev->outb.sa_bmap_mem = NULL;
 250                 if (dev->outb.sa_dptr) {
 251                         plt_free(dev->outb.sa_dptr);
 252                         dev->outb.sa_dptr = NULL;
 253                 }
 254         }
 255
 256         dev->inb.inl_dev = false;
 257         roc_nix_inb_mode_set(nix, false);
 258         dev->nb_rxq_sso = 0;
 259         dev->inb.nb_sess = 0;
 260         dev->outb.nb_sess = 0;
 261         return ret;
 262 }
 263
 264 static void
 265 nix_enable_mseg_on_jumbo(struct cnxk_eth_rxq_sp *rxq)
 266 {
 267         struct rte_pktmbuf_pool_private *mbp_priv;
 268         struct rte_eth_dev *eth_dev;
 269         struct cnxk_eth_dev *dev;
 270         uint32_t buffsz;
 271
 272         dev = rxq->dev;
 273         eth_dev = dev->eth_dev;
 274
 275         /* Get rx buffer size */
 276         mbp_priv = rte_mempool_get_priv(rxq->qconf.mp);
 277         buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
 278
 279         if (eth_dev->data->mtu + (uint32_t)CNXK_NIX_L2_OVERHEAD > buffsz) {
 280                 dev->rx_offloads |= RTE_ETH_RX_OFFLOAD_SCATTER;
 281                 dev->tx_offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
 282         }
 283 }
 284
 285 int
 286 nix_recalc_mtu(struct rte_eth_dev *eth_dev)
 287 {
 288         struct rte_eth_dev_data *data = eth_dev->data;
 289         struct cnxk_eth_rxq_sp *rxq;
 290         int rc;
 291
 292         rxq = ((struct cnxk_eth_rxq_sp *)data->rx_queues[0]) - 1;
 293         /* Setup scatter mode if needed by jumbo */
 294         nix_enable_mseg_on_jumbo(rxq);
 295
 296         rc = cnxk_nix_mtu_set(eth_dev, data->mtu);
 297         if (rc)
 298                 plt_err("Failed to set default MTU size, rc=%d", rc);
 299
 300         return rc;
 301 }
 302
 303 static int
 304 nix_init_flow_ctrl_config(struct rte_eth_dev *eth_dev)
 305 {
 306         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 307         struct cnxk_fc_cfg *fc = &dev->fc_cfg;
 308         struct rte_eth_fc_conf fc_conf = {0};
 309         int rc;
 310
 311         /* Both Rx & Tx flow ctrl get enabled(RTE_ETH_FC_FULL) in HW
 312          * by AF driver, update those info in PMD structure.
 313          */
 314         rc = cnxk_nix_flow_ctrl_get(eth_dev, &fc_conf);
 315         if (rc)
 316                 goto exit;
 317
 318         fc->mode = fc_conf.mode;
 319         fc->rx_pause = (fc_conf.mode == RTE_ETH_FC_FULL) ||
 320                         (fc_conf.mode == RTE_ETH_FC_RX_PAUSE);
 321         fc->tx_pause = (fc_conf.mode == RTE_ETH_FC_FULL) ||
 322                         (fc_conf.mode == RTE_ETH_FC_TX_PAUSE);
 323
 324 exit:
 325         return rc;
 326 }
 327
 328 static int
 329 nix_update_flow_ctrl_config(struct rte_eth_dev *eth_dev)
 330 {
 331         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 332         struct cnxk_fc_cfg *fc = &dev->fc_cfg;
 333         struct rte_eth_fc_conf fc_cfg = {0};
 334
 335         if (roc_nix_is_vf_or_sdp(&dev->nix) && !roc_nix_is_lbk(&dev->nix))
 336                 return 0;
 337
 338         fc_cfg.mode = fc->mode;
 339
 340         /* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */
 341         if (roc_model_is_cn96_ax() &&
 342             dev->npc.switch_header_type != ROC_PRIV_FLAGS_HIGIG &&
 343             (fc_cfg.mode == RTE_ETH_FC_FULL || fc_cfg.mode == RTE_ETH_FC_RX_PAUSE)) {
 344                 fc_cfg.mode =
 345                                 (fc_cfg.mode == RTE_ETH_FC_FULL ||
 346                                 fc_cfg.mode == RTE_ETH_FC_TX_PAUSE) ?
 347                                 RTE_ETH_FC_TX_PAUSE : RTE_ETH_FC_NONE;
 348         }
 349
 350         return cnxk_nix_flow_ctrl_set(eth_dev, &fc_cfg);
 351 }
 352
 353 uint64_t
 354 cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev)
 355 {
 356         uint16_t port_id = dev->eth_dev->data->port_id;
 357         struct rte_mbuf mb_def;
 358         uint64_t *tmp;
 359
 360         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
 361         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
 362                                  offsetof(struct rte_mbuf, data_off) !=
 363                          2);
 364         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
 365                                  offsetof(struct rte_mbuf, data_off) !=
 366                          4);
 367         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
 368                                  offsetof(struct rte_mbuf, data_off) !=
 369                          6);
 370         mb_def.nb_segs = 1;
 371         mb_def.data_off = RTE_PKTMBUF_HEADROOM +
 372                           (dev->ptp_en * CNXK_NIX_TIMESYNC_RX_OFFSET);
 373         mb_def.port = port_id;
 374         rte_mbuf_refcnt_set(&mb_def, 1);
 375
 376         /* Prevent compiler reordering: rearm_data covers previous fields */
 377         rte_compiler_barrier();
 378         tmp = (uint64_t *)&mb_def.rearm_data;
 379
 380         return *tmp;
 381 }
 382
 383 static inline uint8_t
 384 nix_sq_max_sqe_sz(struct cnxk_eth_dev *dev)
 385 {
 386         /*
 387          * Maximum three segments can be supported with W8, Choose
 388          * NIX_MAXSQESZ_W16 for multi segment offload.
 389          */
 390         if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_MULTI_SEGS)
 391                 return NIX_MAXSQESZ_W16;
 392         else
 393                 return NIX_MAXSQESZ_W8;
 394 }
 395
 396 int
 397 cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 398                         uint16_t nb_desc, uint16_t fp_tx_q_sz,
 399                         const struct rte_eth_txconf *tx_conf)
 400 {
 401         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 402         const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
 403         struct cnxk_eth_txq_sp *txq_sp;
 404         struct roc_nix_sq *sq;
 405         size_t txq_sz;
 406         int rc;
 407
 408         /* Free memory prior to re-allocation if needed. */
 409         if (eth_dev->data->tx_queues[qid] != NULL) {
 410                 plt_nix_dbg("Freeing memory prior to re-allocation %d", qid);
 411                 dev_ops->tx_queue_release(eth_dev, qid);
 412                 eth_dev->data->tx_queues[qid] = NULL;
 413         }
 414
 415         /* When Tx Security offload is enabled, increase tx desc count by
 416          * max possible outbound desc count.
 417          */
 418         if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY)
 419                 nb_desc += dev->outb.nb_desc;
 420
 421         /* Setup ROC SQ */
 422         sq = &dev->sqs[qid];
 423         sq->qid = qid;
 424         sq->nb_desc = nb_desc;
 425         sq->max_sqe_sz = nix_sq_max_sqe_sz(dev);
 426
 427         rc = roc_nix_sq_init(&dev->nix, sq);
 428         if (rc) {
 429                 plt_err("Failed to init sq=%d, rc=%d", qid, rc);
 430                 return rc;
 431         }
 432
 433         rc = -ENOMEM;
 434         txq_sz = sizeof(struct cnxk_eth_txq_sp) + fp_tx_q_sz;
 435         txq_sp = plt_zmalloc(txq_sz, PLT_CACHE_LINE_SIZE);
 436         if (!txq_sp) {
 437                 plt_err("Failed to alloc tx queue mem");
 438                 rc |= roc_nix_sq_fini(sq);
 439                 return rc;
 440         }
 441
 442         txq_sp->dev = dev;
 443         txq_sp->qid = qid;
 444         txq_sp->qconf.conf.tx = *tx_conf;
 445         /* Queue config should reflect global offloads */
 446         txq_sp->qconf.conf.tx.offloads = dev->tx_offloads;
 447         txq_sp->qconf.nb_desc = nb_desc;
 448
 449         plt_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " lmt_addr=%p"
 450                     " nb_sqb_bufs=%d sqes_per_sqb_log2=%d",
 451                     qid, sq->fc, dev->tx_offloads, sq->lmt_addr,
 452                     sq->nb_sqb_bufs, sq->sqes_per_sqb_log2);
 453
 454         /* Store start of fast path area */
 455         eth_dev->data->tx_queues[qid] = txq_sp + 1;
 456         eth_dev->data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
 457         return 0;
 458 }
 459
 460 static void
 461 cnxk_nix_tx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)
 462 {
 463         void *txq = eth_dev->data->tx_queues[qid];
 464         struct cnxk_eth_txq_sp *txq_sp;
 465         struct cnxk_eth_dev *dev;
 466         struct roc_nix_sq *sq;
 467         int rc;
 468
 469         if (!txq)
 470                 return;
 471
 472         txq_sp = cnxk_eth_txq_to_sp(txq);
 473
 474         dev = txq_sp->dev;
 475
 476         plt_nix_dbg("Releasing txq %u", qid);
 477
 478         /* Cleanup ROC SQ */
 479         sq = &dev->sqs[qid];
 480         rc = roc_nix_sq_fini(sq);
 481         if (rc)
 482                 plt_err("Failed to cleanup sq, rc=%d", rc);
 483
 484         /* Finally free */
 485         plt_free(txq_sp);
 486 }
 487
 488 int
 489 cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 490                         uint16_t nb_desc, uint16_t fp_rx_q_sz,
 491                         const struct rte_eth_rxconf *rx_conf,
 492                         struct rte_mempool *mp)
 493 {
 494         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 495         struct roc_nix *nix = &dev->nix;
 496         struct cnxk_eth_rxq_sp *rxq_sp;
 497         struct rte_mempool_ops *ops;
 498         const char *platform_ops;
 499         struct roc_nix_rq *rq;
 500         struct roc_nix_cq *cq;
 501         uint16_t first_skip;
 502         int rc = -EINVAL;
 503         size_t rxq_sz;
 504
 505         /* Sanity checks */
 506         if (rx_conf->rx_deferred_start == 1) {
 507                 plt_err("Deferred Rx start is not supported");
 508                 goto fail;
 509         }
 510
 511         platform_ops = rte_mbuf_platform_mempool_ops();
 512         /* This driver needs cnxk_npa mempool ops to work */
 513         ops = rte_mempool_get_ops(mp->ops_index);
 514         if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
 515                 plt_err("mempool ops should be of cnxk_npa type");
 516                 goto fail;
 517         }
 518
 519         if (mp->pool_id == 0) {
 520                 plt_err("Invalid pool_id");
 521                 goto fail;
 522         }
 523
 524         /* Free memory prior to re-allocation if needed */
 525         if (eth_dev->data->rx_queues[qid] != NULL) {
 526                 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
 527
 528                 plt_nix_dbg("Freeing memory prior to re-allocation %d", qid);
 529                 dev_ops->rx_queue_release(eth_dev, qid);
 530                 eth_dev->data->rx_queues[qid] = NULL;
 531         }
 532
 533         /* Clam up cq limit to size of packet pool aura for LBK
 534          * to avoid meta packet drop as LBK does not currently support
 535          * backpressure.
 536          */
 537         if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY && roc_nix_is_lbk(nix)) {
 538                 uint64_t pkt_pool_limit = roc_nix_inl_dev_rq_limit_get();
 539
 540                 /* Use current RQ's aura limit if inl rq is not available */
 541                 if (!pkt_pool_limit)
 542                         pkt_pool_limit = roc_npa_aura_op_limit_get(mp->pool_id);
 543                 nb_desc = RTE_MAX(nb_desc, pkt_pool_limit);
 544         }
 545
 546         /* Setup ROC CQ */
 547         cq = &dev->cqs[qid];
 548         cq->qid = qid;
 549         cq->nb_desc = nb_desc;
 550         rc = roc_nix_cq_init(&dev->nix, cq);
 551         if (rc) {
 552                 plt_err("Failed to init roc cq for rq=%d, rc=%d", qid, rc);
 553                 goto fail;
 554         }
 555
 556         /* Setup ROC RQ */
 557         rq = &dev->rqs[qid];
 558         rq->qid = qid;
 559         rq->aura_handle = mp->pool_id;
 560         rq->flow_tag_width = 32;
 561         rq->sso_ena = false;
 562
 563         /* Calculate first mbuf skip */
 564         first_skip = (sizeof(struct rte_mbuf));
 565         first_skip += RTE_PKTMBUF_HEADROOM;
 566         first_skip += rte_pktmbuf_priv_size(mp);
 567         rq->first_skip = first_skip;
 568         rq->later_skip = sizeof(struct rte_mbuf);
 569         rq->lpb_size = mp->elt_size;
 570
 571         /* Enable Inline IPSec on RQ, will not be used for Poll mode */
 572         if (roc_nix_inl_inb_is_enabled(nix))
 573                 rq->ipsech_ena = true;
 574
 575         rc = roc_nix_rq_init(&dev->nix, rq, !!eth_dev->data->dev_started);
 576         if (rc) {
 577                 plt_err("Failed to init roc rq for rq=%d, rc=%d", qid, rc);
 578                 goto cq_fini;
 579         }
 580
 581         /* Allocate and setup fast path rx queue */
 582         rc = -ENOMEM;
 583         rxq_sz = sizeof(struct cnxk_eth_rxq_sp) + fp_rx_q_sz;
 584         rxq_sp = plt_zmalloc(rxq_sz, PLT_CACHE_LINE_SIZE);
 585         if (!rxq_sp) {
 586                 plt_err("Failed to alloc rx queue for rq=%d", qid);
 587                 goto rq_fini;
 588         }
 589
 590         /* Setup slow path fields */
 591         rxq_sp->dev = dev;
 592         rxq_sp->qid = qid;
 593         rxq_sp->qconf.conf.rx = *rx_conf;
 594         /* Queue config should reflect global offloads */
 595         rxq_sp->qconf.conf.rx.offloads = dev->rx_offloads;
 596         rxq_sp->qconf.nb_desc = nb_desc;
 597         rxq_sp->qconf.mp = mp;
 598
 599         if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
 600                 /* Setup rq reference for inline dev if present */
 601                 rc = roc_nix_inl_dev_rq_get(rq);
 602                 if (rc)
 603                         goto free_mem;
 604         }
 605
 606         plt_nix_dbg("rq=%d pool=%s nb_desc=%d->%d", qid, mp->name, nb_desc,
 607                     cq->nb_desc);
 608
 609         /* Store start of fast path area */
 610         eth_dev->data->rx_queues[qid] = rxq_sp + 1;
 611         eth_dev->data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
 612
 613         /* Calculating delta and freq mult between PTP HI clock and tsc.
 614          * These are needed in deriving raw clock value from tsc counter.
 615          * read_clock eth op returns raw clock value.
 616          */
 617         if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) || dev->ptp_en) {
 618                 rc = cnxk_nix_tsc_convert(dev);
 619                 if (rc) {
 620                         plt_err("Failed to calculate delta and freq mult");
 621                         goto rq_fini;
 622                 }
 623         }
 624
 625         return 0;
 626 free_mem:
 627         plt_free(rxq_sp);
 628 rq_fini:
 629         rc |= roc_nix_rq_fini(rq);
 630 cq_fini:
 631         rc |= roc_nix_cq_fini(cq);
 632 fail:
 633         return rc;
 634 }
 635
 636 static void
 637 cnxk_nix_rx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)
 638 {
 639         void *rxq = eth_dev->data->rx_queues[qid];
 640         struct cnxk_eth_rxq_sp *rxq_sp;
 641         struct cnxk_eth_dev *dev;
 642         struct roc_nix_rq *rq;
 643         struct roc_nix_cq *cq;
 644         int rc;
 645
 646         if (!rxq)
 647                 return;
 648
 649         rxq_sp = cnxk_eth_rxq_to_sp(rxq);
 650         dev = rxq_sp->dev;
 651         rq = &dev->rqs[qid];
 652
 653         plt_nix_dbg("Releasing rxq %u", qid);
 654
 655         /* Release rq reference for inline dev if present */
 656         if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)
 657                 roc_nix_inl_dev_rq_put(rq);
 658
 659         /* Cleanup ROC RQ */
 660         rc = roc_nix_rq_fini(rq);
 661         if (rc)
 662                 plt_err("Failed to cleanup rq, rc=%d", rc);
 663
 664         /* Cleanup ROC CQ */
 665         cq = &dev->cqs[qid];
 666         rc = roc_nix_cq_fini(cq);
 667         if (rc)
 668                 plt_err("Failed to cleanup cq, rc=%d", rc);
 669
 670         /* Finally free fast path area */
 671         plt_free(rxq_sp);
 672 }
 673
 674 uint32_t
 675 cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
 676                        uint8_t rss_level)
 677 {
 678         uint32_t flow_key_type[RSS_MAX_LEVELS][6] = {
 679                 {FLOW_KEY_TYPE_IPV4, FLOW_KEY_TYPE_IPV6, FLOW_KEY_TYPE_TCP,
 680                  FLOW_KEY_TYPE_UDP, FLOW_KEY_TYPE_SCTP, FLOW_KEY_TYPE_ETH_DMAC},
 681                 {FLOW_KEY_TYPE_INNR_IPV4, FLOW_KEY_TYPE_INNR_IPV6,
 682                  FLOW_KEY_TYPE_INNR_TCP, FLOW_KEY_TYPE_INNR_UDP,
 683                  FLOW_KEY_TYPE_INNR_SCTP, FLOW_KEY_TYPE_INNR_ETH_DMAC},
 684                 {FLOW_KEY_TYPE_IPV4 | FLOW_KEY_TYPE_INNR_IPV4,
 685                  FLOW_KEY_TYPE_IPV6 | FLOW_KEY_TYPE_INNR_IPV6,
 686                  FLOW_KEY_TYPE_TCP | FLOW_KEY_TYPE_INNR_TCP,
 687                  FLOW_KEY_TYPE_UDP | FLOW_KEY_TYPE_INNR_UDP,
 688                  FLOW_KEY_TYPE_SCTP | FLOW_KEY_TYPE_INNR_SCTP,
 689                  FLOW_KEY_TYPE_ETH_DMAC | FLOW_KEY_TYPE_INNR_ETH_DMAC}
 690         };
 691         uint32_t flowkey_cfg = 0;
 692
 693         dev->ethdev_rss_hf = ethdev_rss;
 694
 695         if (ethdev_rss & RTE_ETH_RSS_L2_PAYLOAD &&
 696             dev->npc.switch_header_type == ROC_PRIV_FLAGS_LEN_90B) {
 697                 flowkey_cfg |= FLOW_KEY_TYPE_CH_LEN_90B;
 698         }
 699
 700         if (ethdev_rss & RTE_ETH_RSS_C_VLAN)
 701                 flowkey_cfg |= FLOW_KEY_TYPE_VLAN;
 702
 703         if (ethdev_rss & RTE_ETH_RSS_L3_SRC_ONLY)
 704                 flowkey_cfg |= FLOW_KEY_TYPE_L3_SRC;
 705
 706         if (ethdev_rss & RTE_ETH_RSS_L3_DST_ONLY)
 707                 flowkey_cfg |= FLOW_KEY_TYPE_L3_DST;
 708
 709         if (ethdev_rss & RTE_ETH_RSS_L4_SRC_ONLY)
 710                 flowkey_cfg |= FLOW_KEY_TYPE_L4_SRC;
 711
 712         if (ethdev_rss & RTE_ETH_RSS_L4_DST_ONLY)
 713                 flowkey_cfg |= FLOW_KEY_TYPE_L4_DST;
 714
 715         if (ethdev_rss & RSS_IPV4_ENABLE)
 716                 flowkey_cfg |= flow_key_type[rss_level][RSS_IPV4_INDEX];
 717
 718         if (ethdev_rss & RSS_IPV6_ENABLE)
 719                 flowkey_cfg |= flow_key_type[rss_level][RSS_IPV6_INDEX];
 720
 721         if (ethdev_rss & RTE_ETH_RSS_TCP)
 722                 flowkey_cfg |= flow_key_type[rss_level][RSS_TCP_INDEX];
 723
 724         if (ethdev_rss & RTE_ETH_RSS_UDP)
 725                 flowkey_cfg |= flow_key_type[rss_level][RSS_UDP_INDEX];
 726
 727         if (ethdev_rss & RTE_ETH_RSS_SCTP)
 728                 flowkey_cfg |= flow_key_type[rss_level][RSS_SCTP_INDEX];
 729
 730         if (ethdev_rss & RTE_ETH_RSS_L2_PAYLOAD)
 731                 flowkey_cfg |= flow_key_type[rss_level][RSS_DMAC_INDEX];
 732
 733         if (ethdev_rss & RSS_IPV6_EX_ENABLE)
 734                 flowkey_cfg |= FLOW_KEY_TYPE_IPV6_EXT;
 735
 736         if (ethdev_rss & RTE_ETH_RSS_PORT)
 737                 flowkey_cfg |= FLOW_KEY_TYPE_PORT;
 738
 739         if (ethdev_rss & RTE_ETH_RSS_NVGRE)
 740                 flowkey_cfg |= FLOW_KEY_TYPE_NVGRE;
 741
 742         if (ethdev_rss & RTE_ETH_RSS_VXLAN)
 743                 flowkey_cfg |= FLOW_KEY_TYPE_VXLAN;
 744
 745         if (ethdev_rss & RTE_ETH_RSS_GENEVE)
 746                 flowkey_cfg |= FLOW_KEY_TYPE_GENEVE;
 747
 748         if (ethdev_rss & RTE_ETH_RSS_GTPU)
 749                 flowkey_cfg |= FLOW_KEY_TYPE_GTPU;
 750
 751         return flowkey_cfg;
 752 }
 753
 754 static void
 755 nix_free_queue_mem(struct cnxk_eth_dev *dev)
 756 {
 757         plt_free(dev->rqs);
 758         plt_free(dev->cqs);
 759         plt_free(dev->sqs);
 760         dev->rqs = NULL;
 761         dev->cqs = NULL;
 762         dev->sqs = NULL;
 763 }
 764
 765 static int
 766 nix_ingress_policer_setup(struct cnxk_eth_dev *dev)
 767 {
 768         TAILQ_INIT(&dev->mtr_profiles);
 769         TAILQ_INIT(&dev->mtr_policy);
 770         TAILQ_INIT(&dev->mtr);
 771
 772         return 0;
 773 }
 774
 775 static int
 776 nix_rss_default_setup(struct cnxk_eth_dev *dev)
 777 {
 778         struct rte_eth_dev *eth_dev = dev->eth_dev;
 779         uint8_t rss_hash_level;
 780         uint32_t flowkey_cfg;
 781         uint64_t rss_hf;
 782
 783         rss_hf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
 784         rss_hash_level = RTE_ETH_RSS_LEVEL(rss_hf);
 785         if (rss_hash_level)
 786                 rss_hash_level -= 1;
 787
 788         flowkey_cfg = cnxk_rss_ethdev_to_nix(dev, rss_hf, rss_hash_level);
 789         return roc_nix_rss_default_setup(&dev->nix, flowkey_cfg);
 790 }
 791
 792 static int
 793 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
 794 {
 795         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 796         const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
 797         struct cnxk_eth_qconf *tx_qconf = NULL;
 798         struct cnxk_eth_qconf *rx_qconf = NULL;
 799         struct cnxk_eth_rxq_sp *rxq_sp;
 800         struct cnxk_eth_txq_sp *txq_sp;
 801         int i, nb_rxq, nb_txq;
 802         void **txq, **rxq;
 803
 804         nb_rxq = RTE_MIN(dev->nb_rxq, eth_dev->data->nb_rx_queues);
 805         nb_txq = RTE_MIN(dev->nb_txq, eth_dev->data->nb_tx_queues);
 806
 807         tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
 808         if (tx_qconf == NULL) {
 809                 plt_err("Failed to allocate memory for tx_qconf");
 810                 goto fail;
 811         }
 812
 813         rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
 814         if (rx_qconf == NULL) {
 815                 plt_err("Failed to allocate memory for rx_qconf");
 816                 goto fail;
 817         }
 818
 819         txq = eth_dev->data->tx_queues;
 820         for (i = 0; i < nb_txq; i++) {
 821                 if (txq[i] == NULL) {
 822                         tx_qconf[i].valid = false;
 823                         plt_info("txq[%d] is already released", i);
 824                         continue;
 825                 }
 826                 txq_sp = cnxk_eth_txq_to_sp(txq[i]);
 827                 memcpy(&tx_qconf[i], &txq_sp->qconf, sizeof(*tx_qconf));
 828                 tx_qconf[i].valid = true;
 829                 dev_ops->tx_queue_release(eth_dev, i);
 830                 eth_dev->data->tx_queues[i] = NULL;
 831         }
 832
 833         rxq = eth_dev->data->rx_queues;
 834         for (i = 0; i < nb_rxq; i++) {
 835                 if (rxq[i] == NULL) {
 836                         rx_qconf[i].valid = false;
 837                         plt_info("rxq[%d] is already released", i);
 838                         continue;
 839                 }
 840                 rxq_sp = cnxk_eth_rxq_to_sp(rxq[i]);
 841                 memcpy(&rx_qconf[i], &rxq_sp->qconf, sizeof(*rx_qconf));
 842                 rx_qconf[i].valid = true;
 843                 dev_ops->rx_queue_release(eth_dev, i);
 844                 eth_dev->data->rx_queues[i] = NULL;
 845         }
 846
 847         dev->tx_qconf = tx_qconf;
 848         dev->rx_qconf = rx_qconf;
 849         return 0;
 850
 851 fail:
 852         free(tx_qconf);
 853         free(rx_qconf);
 854         return -ENOMEM;
 855 }
 856
 857 static int
 858 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
 859 {
 860         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 861         const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
 862         struct cnxk_eth_qconf *tx_qconf = dev->tx_qconf;
 863         struct cnxk_eth_qconf *rx_qconf = dev->rx_qconf;
 864         int rc, i, nb_rxq, nb_txq;
 865
 866         nb_rxq = RTE_MIN(dev->nb_rxq, eth_dev->data->nb_rx_queues);
 867         nb_txq = RTE_MIN(dev->nb_txq, eth_dev->data->nb_tx_queues);
 868
 869         rc = -ENOMEM;
 870         /* Setup tx & rx queues with previous configuration so
 871          * that the queues can be functional in cases like ports
 872          * are started without re configuring queues.
 873          *
 874          * Usual re config sequence is like below:
 875          * port_configure() {
 876          *      if(reconfigure) {
 877          *              queue_release()
 878          *              queue_setup()
 879          *      }
 880          *      queue_configure() {
 881          *              queue_release()
 882          *              queue_setup()
 883          *      }
 884          * }
 885          * port_start()
 886          *
 887          * In some application's control path, queue_configure() would
 888          * NOT be invoked for TXQs/RXQs in port_configure().
 889          * In such cases, queues can be functional after start as the
 890          * queues are already setup in port_configure().
 891          */
 892         for (i = 0; i < nb_txq; i++) {
 893                 if (!tx_qconf[i].valid)
 894                         continue;
 895                 rc = dev_ops->tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc, 0,
 896                                              &tx_qconf[i].conf.tx);
 897                 if (rc) {
 898                         plt_err("Failed to setup tx queue rc=%d", rc);
 899                         for (i -= 1; i >= 0; i--)
 900                                 dev_ops->tx_queue_release(eth_dev, i);
 901                         goto fail;
 902                 }
 903         }
 904
 905         free(tx_qconf);
 906         tx_qconf = NULL;
 907
 908         for (i = 0; i < nb_rxq; i++) {
 909                 if (!rx_qconf[i].valid)
 910                         continue;
 911                 rc = dev_ops->rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc, 0,
 912                                              &rx_qconf[i].conf.rx,
 913                                              rx_qconf[i].mp);
 914                 if (rc) {
 915                         plt_err("Failed to setup rx queue rc=%d", rc);
 916                         for (i -= 1; i >= 0; i--)
 917                                 dev_ops->rx_queue_release(eth_dev, i);
 918                         goto tx_queue_release;
 919                 }
 920         }
 921
 922         free(rx_qconf);
 923         rx_qconf = NULL;
 924
 925         return 0;
 926
 927 tx_queue_release:
 928         for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
 929                 dev_ops->tx_queue_release(eth_dev, i);
 930 fail:
 931         if (tx_qconf)
 932                 free(tx_qconf);
 933         if (rx_qconf)
 934                 free(rx_qconf);
 935
 936         return rc;
 937 }
 938
 939 static uint16_t
 940 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
 941 {
 942         RTE_SET_USED(queue);
 943         RTE_SET_USED(mbufs);
 944         RTE_SET_USED(pkts);
 945
 946         return 0;
 947 }
 948
 949 static void
 950 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
 951 {
 952         /* These dummy functions are required for supporting
 953          * some applications which reconfigure queues without
 954          * stopping tx burst and rx burst threads(eg kni app)
 955          * When the queues context is saved, txq/rxqs are released
 956          * which caused app crash since rx/tx burst is still
 957          * on different lcores
 958          */
 959         eth_dev->tx_pkt_burst = nix_eth_nop_burst;
 960         eth_dev->rx_pkt_burst = nix_eth_nop_burst;
 961         rte_mb();
 962 }
 963
 964 static int
 965 nix_lso_tun_fmt_update(struct cnxk_eth_dev *dev)
 966 {
 967         uint8_t udp_tun[ROC_NIX_LSO_TUN_MAX];
 968         uint8_t tun[ROC_NIX_LSO_TUN_MAX];
 969         struct roc_nix *nix = &dev->nix;
 970         int rc;
 971
 972         rc = roc_nix_lso_fmt_get(nix, udp_tun, tun);
 973         if (rc)
 974                 return rc;
 975
 976         dev->lso_tun_fmt = ((uint64_t)tun[ROC_NIX_LSO_TUN_V4V4] |
 977                             (uint64_t)tun[ROC_NIX_LSO_TUN_V4V6] << 8 |
 978                             (uint64_t)tun[ROC_NIX_LSO_TUN_V6V4] << 16 |
 979                             (uint64_t)tun[ROC_NIX_LSO_TUN_V6V6] << 24);
 980
 981         dev->lso_tun_fmt |= ((uint64_t)udp_tun[ROC_NIX_LSO_TUN_V4V4] << 32 |
 982                              (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V4V6] << 40 |
 983                              (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V6V4] << 48 |
 984                              (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V6V6] << 56);
 985         return 0;
 986 }
 987
 988 static int
 989 nix_lso_fmt_setup(struct cnxk_eth_dev *dev)
 990 {
 991         struct roc_nix *nix = &dev->nix;
 992         int rc;
 993
 994         /* Nothing much to do if offload is not enabled */
 995         if (!(dev->tx_offloads &
 996               (RTE_ETH_TX_OFFLOAD_TCP_TSO | RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
 997                RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO | RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO)))
 998                 return 0;
 999
1000         /* Setup LSO formats in AF. Its a no-op if other ethdev has
1001          * already set it up
1002          */
1003         rc = roc_nix_lso_fmt_setup(nix);
1004         if (rc)
1005                 return rc;
1006
1007         return nix_lso_tun_fmt_update(dev);
1008 }
1009
1010 int
1011 cnxk_nix_configure(struct rte_eth_dev *eth_dev)
1012 {
1013         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1014         struct rte_eth_dev_data *data = eth_dev->data;
1015         struct rte_eth_conf *conf = &data->dev_conf;
1016         struct rte_eth_rxmode *rxmode = &conf->rxmode;
1017         struct rte_eth_txmode *txmode = &conf->txmode;
1018         char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
1019         struct roc_nix_fc_cfg fc_cfg = {0};
1020         struct roc_nix *nix = &dev->nix;
1021         struct rte_ether_addr *ea;
1022         uint8_t nb_rxq, nb_txq;
1023         uint64_t rx_cfg;
1024         void *qs;
1025         int rc;
1026
1027         rc = -EINVAL;
1028
1029         /* Sanity checks */
1030         if (rte_eal_has_hugepages() == 0) {
1031                 plt_err("Huge page is not configured");
1032                 goto fail_configure;
1033         }
1034
1035         if (conf->dcb_capability_en == 1) {
1036                 plt_err("dcb enable is not supported");
1037                 goto fail_configure;
1038         }
1039
1040         if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1041                 plt_err("Flow director is not supported");
1042                 goto fail_configure;
1043         }
1044
1045         if (rxmode->mq_mode != RTE_ETH_MQ_RX_NONE &&
1046             rxmode->mq_mode != RTE_ETH_MQ_RX_RSS) {
1047                 plt_err("Unsupported mq rx mode %d", rxmode->mq_mode);
1048                 goto fail_configure;
1049         }
1050
1051         if (txmode->mq_mode != RTE_ETH_MQ_TX_NONE) {
1052                 plt_err("Unsupported mq tx mode %d", txmode->mq_mode);
1053                 goto fail_configure;
1054         }
1055
1056         /* Free the resources allocated from the previous configure */
1057         if (dev->configured == 1) {
1058                 /* Unregister queue irq's */
1059                 roc_nix_unregister_queue_irqs(nix);
1060
1061                 /* Unregister CQ irqs if present */
1062                 if (eth_dev->data->dev_conf.intr_conf.rxq)
1063                         roc_nix_unregister_cq_irqs(nix);
1064
1065                 /* Set no-op functions */
1066                 nix_set_nop_rxtx_function(eth_dev);
1067                 /* Store queue config for later */
1068                 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1069                 if (rc)
1070                         goto fail_configure;
1071
1072                 /* Disable and free rte_meter entries */
1073                 rc = nix_meter_fini(dev);
1074                 if (rc)
1075                         goto fail_configure;
1076
1077                 /* Cleanup security support */
1078                 rc = nix_security_release(dev);
1079                 if (rc)
1080                         goto fail_configure;
1081
1082                 roc_nix_tm_fini(nix);
1083                 roc_nix_lf_free(nix);
1084         }
1085
1086         dev->rx_offloads = rxmode->offloads;
1087         dev->tx_offloads = txmode->offloads;
1088
1089         /* Prepare rx cfg */
1090         rx_cfg = ROC_NIX_LF_RX_CFG_DIS_APAD;
1091         if (dev->rx_offloads &
1092             (RTE_ETH_RX_OFFLOAD_TCP_CKSUM | RTE_ETH_RX_OFFLOAD_UDP_CKSUM)) {
1093                 rx_cfg |= ROC_NIX_LF_RX_CFG_CSUM_OL4;
1094                 rx_cfg |= ROC_NIX_LF_RX_CFG_CSUM_IL4;
1095         }
1096         rx_cfg |= (ROC_NIX_LF_RX_CFG_DROP_RE | ROC_NIX_LF_RX_CFG_L2_LEN_ERR |
1097                    ROC_NIX_LF_RX_CFG_LEN_IL4 | ROC_NIX_LF_RX_CFG_LEN_IL3 |
1098                    ROC_NIX_LF_RX_CFG_LEN_OL4 | ROC_NIX_LF_RX_CFG_LEN_OL3);
1099
1100         if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
1101                 rx_cfg |= ROC_NIX_LF_RX_CFG_IP6_UDP_OPT;
1102                 /* Disable drop re if rx offload security is enabled and
1103                  * platform does not support it.
1104                  */
1105                 if (dev->ipsecd_drop_re_dis)
1106                         rx_cfg &= ~(ROC_NIX_LF_RX_CFG_DROP_RE);
1107         }
1108
1109         nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1110         nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1111
1112         /* Alloc a nix lf */
1113         rc = roc_nix_lf_alloc(nix, nb_rxq, nb_txq, rx_cfg);
1114         if (rc) {
1115                 plt_err("Failed to init nix_lf rc=%d", rc);
1116                 goto fail_configure;
1117         }
1118
1119         dev->npc.channel = roc_nix_get_base_chan(nix);
1120
1121         nb_rxq = data->nb_rx_queues;
1122         nb_txq = data->nb_tx_queues;
1123         rc = -ENOMEM;
1124         if (nb_rxq) {
1125                 /* Allocate memory for roc rq's and cq's */
1126                 qs = plt_zmalloc(sizeof(struct roc_nix_rq) * nb_rxq, 0);
1127                 if (!qs) {
1128                         plt_err("Failed to alloc rqs");
1129                         goto free_nix_lf;
1130                 }
1131                 dev->rqs = qs;
1132
1133                 qs = plt_zmalloc(sizeof(struct roc_nix_cq) * nb_rxq, 0);
1134                 if (!qs) {
1135                         plt_err("Failed to alloc cqs");
1136                         goto free_nix_lf;
1137                 }
1138                 dev->cqs = qs;
1139         }
1140
1141         if (nb_txq) {
1142                 /* Allocate memory for roc sq's */
1143                 qs = plt_zmalloc(sizeof(struct roc_nix_sq) * nb_txq, 0);
1144                 if (!qs) {
1145                         plt_err("Failed to alloc sqs");
1146                         goto free_nix_lf;
1147                 }
1148                 dev->sqs = qs;
1149         }
1150
1151         /* Re-enable NIX LF error interrupts */
1152         roc_nix_err_intr_ena_dis(nix, true);
1153         roc_nix_ras_intr_ena_dis(nix, true);
1154
1155         if (nix->rx_ptp_ena &&
1156             dev->npc.switch_header_type == ROC_PRIV_FLAGS_HIGIG) {
1157                 plt_err("Both PTP and switch header enabled");
1158                 goto free_nix_lf;
1159         }
1160
1161         rc = roc_nix_switch_hdr_set(nix, dev->npc.switch_header_type);
1162         if (rc) {
1163                 plt_err("Failed to enable switch type nix_lf rc=%d", rc);
1164                 goto free_nix_lf;
1165         }
1166
1167         /* Setup LSO if needed */
1168         rc = nix_lso_fmt_setup(dev);
1169         if (rc) {
1170                 plt_err("Failed to setup nix lso format fields, rc=%d", rc);
1171                 goto free_nix_lf;
1172         }
1173
1174         /* Configure RSS */
1175         rc = nix_rss_default_setup(dev);
1176         if (rc) {
1177                 plt_err("Failed to configure rss rc=%d", rc);
1178                 goto free_nix_lf;
1179         }
1180
1181         /* Init the default TM scheduler hierarchy */
1182         rc = roc_nix_tm_init(nix);
1183         if (rc) {
1184                 plt_err("Failed to init traffic manager, rc=%d", rc);
1185                 goto free_nix_lf;
1186         }
1187
1188         rc = nix_ingress_policer_setup(dev);
1189         if (rc) {
1190                 plt_err("Failed to setup ingress policer rc=%d", rc);
1191                 goto free_nix_lf;
1192         }
1193
1194         rc = roc_nix_tm_hierarchy_enable(nix, ROC_NIX_TM_DEFAULT, false);
1195         if (rc) {
1196                 plt_err("Failed to enable default tm hierarchy, rc=%d", rc);
1197                 goto tm_fini;
1198         }
1199
1200         /* Register queue IRQs */
1201         rc = roc_nix_register_queue_irqs(nix);
1202         if (rc) {
1203                 plt_err("Failed to register queue interrupts rc=%d", rc);
1204                 goto tm_fini;
1205         }
1206
1207         /* Register cq IRQs */
1208         if (eth_dev->data->dev_conf.intr_conf.rxq) {
1209                 if (eth_dev->data->nb_rx_queues > dev->nix.cints) {
1210                         plt_err("Rx interrupt cannot be enabled, rxq > %d",
1211                                 dev->nix.cints);
1212                         goto q_irq_fini;
1213                 }
1214                 /* Rx interrupt feature cannot work with vector mode because,
1215                  * vector mode does not process packets unless min 4 pkts are
1216                  * received, while cq interrupts are generated even for 1 pkt
1217                  * in the CQ.
1218                  */
1219                 dev->scalar_ena = true;
1220
1221                 rc = roc_nix_register_cq_irqs(nix);
1222                 if (rc) {
1223                         plt_err("Failed to register CQ interrupts rc=%d", rc);
1224                         goto q_irq_fini;
1225                 }
1226         }
1227
1228         /* Configure loop back mode */
1229         rc = roc_nix_mac_loopback_enable(nix,
1230                                          eth_dev->data->dev_conf.lpbk_mode);
1231         if (rc) {
1232                 plt_err("Failed to configure cgx loop back mode rc=%d", rc);
1233                 goto cq_fini;
1234         }
1235
1236         /* Setup Inline security support */
1237         rc = nix_security_setup(dev);
1238         if (rc)
1239                 goto cq_fini;
1240
1241         /* Init flow control configuration */
1242         fc_cfg.type = ROC_NIX_FC_RXCHAN_CFG;
1243         fc_cfg.rxchan_cfg.enable = true;
1244         rc = roc_nix_fc_config_set(nix, &fc_cfg);
1245         if (rc) {
1246                 plt_err("Failed to initialize flow control rc=%d", rc);
1247                 goto cq_fini;
1248         }
1249
1250         /* Update flow control configuration to PMD */
1251         rc = nix_init_flow_ctrl_config(eth_dev);
1252         if (rc) {
1253                 plt_err("Failed to initialize flow control rc=%d", rc);
1254                 goto cq_fini;
1255         }
1256
1257         /*
1258          * Restore queue config when reconfigure followed by
1259          * reconfigure and no queue configure invoked from application case.
1260          */
1261         if (dev->configured == 1) {
1262                 rc = nix_restore_queue_cfg(eth_dev);
1263                 if (rc)
1264                         goto sec_release;
1265         }
1266
1267         /* Update the mac address */
1268         ea = eth_dev->data->mac_addrs;
1269         memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1270         if (rte_is_zero_ether_addr(ea))
1271                 rte_eth_random_addr((uint8_t *)ea);
1272
1273         rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
1274
1275         plt_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
1276                     " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 "",
1277                     eth_dev->data->port_id, ea_fmt, nb_rxq, nb_txq,
1278                     dev->rx_offloads, dev->tx_offloads);
1279
1280         /* All good */
1281         dev->configured = 1;
1282         dev->nb_rxq = data->nb_rx_queues;
1283         dev->nb_txq = data->nb_tx_queues;
1284         return 0;
1285
1286 sec_release:
1287         rc |= nix_security_release(dev);
1288 cq_fini:
1289         roc_nix_unregister_cq_irqs(nix);
1290 q_irq_fini:
1291         roc_nix_unregister_queue_irqs(nix);
1292 tm_fini:
1293         roc_nix_tm_fini(nix);
1294 free_nix_lf:
1295         nix_free_queue_mem(dev);
1296         rc |= roc_nix_lf_free(nix);
1297 fail_configure:
1298         dev->configured = 0;
1299         return rc;
1300 }
1301
1302 int
1303 cnxk_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid)
1304 {
1305         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1306         struct rte_eth_dev_data *data = eth_dev->data;
1307         struct roc_nix_sq *sq = &dev->sqs[qid];
1308         int rc = -EINVAL;
1309
1310         if (data->tx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STARTED)
1311                 return 0;
1312
1313         rc = roc_nix_tm_sq_aura_fc(sq, true);
1314         if (rc) {
1315                 plt_err("Failed to enable sq aura fc, txq=%u, rc=%d", qid, rc);
1316                 goto done;
1317         }
1318
1319         data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STARTED;
1320 done:
1321         return rc;
1322 }
1323
1324 int
1325 cnxk_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid)
1326 {
1327         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1328         struct rte_eth_dev_data *data = eth_dev->data;
1329         struct roc_nix_sq *sq = &dev->sqs[qid];
1330         int rc;
1331
1332         if (data->tx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STOPPED)
1333                 return 0;
1334
1335         rc = roc_nix_tm_sq_aura_fc(sq, false);
1336         if (rc) {
1337                 plt_err("Failed to disable sqb aura fc, txq=%u, rc=%d", qid,
1338                         rc);
1339                 goto done;
1340         }
1341
1342         data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
1343 done:
1344         return rc;
1345 }
1346
1347 static int
1348 cnxk_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid)
1349 {
1350         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1351         struct rte_eth_dev_data *data = eth_dev->data;
1352         struct roc_nix_rq *rq = &dev->rqs[qid];
1353         int rc;
1354
1355         if (data->rx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STARTED)
1356                 return 0;
1357
1358         rc = roc_nix_rq_ena_dis(rq, true);
1359         if (rc) {
1360                 plt_err("Failed to enable rxq=%u, rc=%d", qid, rc);
1361                 goto done;
1362         }
1363
1364         data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STARTED;
1365 done:
1366         return rc;
1367 }
1368
1369 static int
1370 cnxk_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid)
1371 {
1372         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1373         struct rte_eth_dev_data *data = eth_dev->data;
1374         struct roc_nix_rq *rq = &dev->rqs[qid];
1375         int rc;
1376
1377         if (data->rx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STOPPED)
1378                 return 0;
1379
1380         rc = roc_nix_rq_ena_dis(rq, false);
1381         if (rc) {
1382                 plt_err("Failed to disable rxq=%u, rc=%d", qid, rc);
1383                 goto done;
1384         }
1385
1386         data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
1387 done:
1388         return rc;
1389 }
1390
1391 static int
1392 cnxk_nix_dev_stop(struct rte_eth_dev *eth_dev)
1393 {
1394         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1395         const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
1396         struct rte_mbuf *rx_pkts[32];
1397         struct rte_eth_link link;
1398         int count, i, j, rc;
1399         void *rxq;
1400
1401         /* Disable switch hdr pkind */
1402         roc_nix_switch_hdr_set(&dev->nix, 0);
1403
1404         /* Stop link change events */
1405         if (!roc_nix_is_vf_or_sdp(&dev->nix))
1406                 roc_nix_mac_link_event_start_stop(&dev->nix, false);
1407
1408         /* Disable Rx via NPC */
1409         roc_nix_npc_rx_ena_dis(&dev->nix, false);
1410
1411         /* Stop rx queues and free up pkts pending */
1412         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1413                 rc = dev_ops->rx_queue_stop(eth_dev, i);
1414                 if (rc)
1415                         continue;
1416
1417                 rxq = eth_dev->data->rx_queues[i];
1418                 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1419                 while (count) {
1420                         for (j = 0; j < count; j++)
1421                                 rte_pktmbuf_free(rx_pkts[j]);
1422                         count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1423                 }
1424         }
1425
1426         /* Stop tx queues  */
1427         for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1428                 dev_ops->tx_queue_stop(eth_dev, i);
1429
1430         /* Bring down link status internally */
1431         memset(&link, 0, sizeof(link));
1432         rte_eth_linkstatus_set(eth_dev, &link);
1433
1434         return 0;
1435 }
1436
1437 int
1438 cnxk_nix_dev_start(struct rte_eth_dev *eth_dev)
1439 {
1440         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1441         int rc, i;
1442
1443         if (eth_dev->data->nb_rx_queues != 0 && !dev->ptp_en) {
1444                 rc = nix_recalc_mtu(eth_dev);
1445                 if (rc)
1446                         return rc;
1447         }
1448
1449         /* Start rx queues */
1450         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1451                 rc = cnxk_nix_rx_queue_start(eth_dev, i);
1452                 if (rc)
1453                         return rc;
1454         }
1455
1456         /* Start tx queues  */
1457         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1458                 rc = cnxk_nix_tx_queue_start(eth_dev, i);
1459                 if (rc)
1460                         return rc;
1461         }
1462
1463         /* Update Flow control configuration */
1464         rc = nix_update_flow_ctrl_config(eth_dev);
1465         if (rc) {
1466                 plt_err("Failed to enable flow control. error code(%d)", rc);
1467                 return rc;
1468         }
1469
1470         /* Enable Rx in NPC */
1471         rc = roc_nix_npc_rx_ena_dis(&dev->nix, true);
1472         if (rc) {
1473                 plt_err("Failed to enable NPC rx %d", rc);
1474                 return rc;
1475         }
1476
1477         cnxk_nix_toggle_flag_link_cfg(dev, true);
1478
1479         /* Start link change events */
1480         if (!roc_nix_is_vf_or_sdp(&dev->nix)) {
1481                 rc = roc_nix_mac_link_event_start_stop(&dev->nix, true);
1482                 if (rc) {
1483                         plt_err("Failed to start cgx link event %d", rc);
1484                         goto rx_disable;
1485                 }
1486         }
1487
1488         /* Enable PTP if it is requested by the user or already
1489          * enabled on PF owning this VF
1490          */
1491         memset(&dev->tstamp, 0, sizeof(struct cnxk_timesync_info));
1492         if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) || dev->ptp_en)
1493                 cnxk_eth_dev_ops.timesync_enable(eth_dev);
1494         else
1495                 cnxk_eth_dev_ops.timesync_disable(eth_dev);
1496
1497         if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
1498                 rc = rte_mbuf_dyn_rx_timestamp_register
1499                         (&dev->tstamp.tstamp_dynfield_offset,
1500                          &dev->tstamp.rx_tstamp_dynflag);
1501                 if (rc != 0) {
1502                         plt_err("Failed to register Rx timestamp field/flag");
1503                         goto rx_disable;
1504                 }
1505         }
1506
1507         cnxk_nix_toggle_flag_link_cfg(dev, false);
1508
1509         return 0;
1510
1511 rx_disable:
1512         roc_nix_npc_rx_ena_dis(&dev->nix, false);
1513         cnxk_nix_toggle_flag_link_cfg(dev, false);
1514         return rc;
1515 }
1516
1517 static int cnxk_nix_dev_reset(struct rte_eth_dev *eth_dev);
1518 static int cnxk_nix_dev_close(struct rte_eth_dev *eth_dev);
1519
1520 /* CNXK platform independent eth dev ops */
1521 struct eth_dev_ops cnxk_eth_dev_ops = {
1522         .mtu_set = cnxk_nix_mtu_set,
1523         .mac_addr_add = cnxk_nix_mac_addr_add,
1524         .mac_addr_remove = cnxk_nix_mac_addr_del,
1525         .mac_addr_set = cnxk_nix_mac_addr_set,
1526         .dev_infos_get = cnxk_nix_info_get,
1527         .link_update = cnxk_nix_link_update,
1528         .tx_queue_release = cnxk_nix_tx_queue_release,
1529         .rx_queue_release = cnxk_nix_rx_queue_release,
1530         .dev_stop = cnxk_nix_dev_stop,
1531         .dev_close = cnxk_nix_dev_close,
1532         .dev_reset = cnxk_nix_dev_reset,
1533         .tx_queue_start = cnxk_nix_tx_queue_start,
1534         .rx_queue_start = cnxk_nix_rx_queue_start,
1535         .rx_queue_stop = cnxk_nix_rx_queue_stop,
1536         .dev_supported_ptypes_get = cnxk_nix_supported_ptypes_get,
1537         .promiscuous_enable = cnxk_nix_promisc_enable,
1538         .promiscuous_disable = cnxk_nix_promisc_disable,
1539         .allmulticast_enable = cnxk_nix_allmulticast_enable,
1540         .allmulticast_disable = cnxk_nix_allmulticast_disable,
1541         .rx_burst_mode_get = cnxk_nix_rx_burst_mode_get,
1542         .tx_burst_mode_get = cnxk_nix_tx_burst_mode_get,
1543         .flow_ctrl_get = cnxk_nix_flow_ctrl_get,
1544         .flow_ctrl_set = cnxk_nix_flow_ctrl_set,
1545         .dev_set_link_up = cnxk_nix_set_link_up,
1546         .dev_set_link_down = cnxk_nix_set_link_down,
1547         .get_module_info = cnxk_nix_get_module_info,
1548         .get_module_eeprom = cnxk_nix_get_module_eeprom,
1549         .rx_queue_intr_enable = cnxk_nix_rx_queue_intr_enable,
1550         .rx_queue_intr_disable = cnxk_nix_rx_queue_intr_disable,
1551         .pool_ops_supported = cnxk_nix_pool_ops_supported,
1552         .queue_stats_mapping_set = cnxk_nix_queue_stats_mapping,
1553         .stats_get = cnxk_nix_stats_get,
1554         .stats_reset = cnxk_nix_stats_reset,
1555         .xstats_get = cnxk_nix_xstats_get,
1556         .xstats_get_names = cnxk_nix_xstats_get_names,
1557         .xstats_reset = cnxk_nix_xstats_reset,
1558         .xstats_get_by_id = cnxk_nix_xstats_get_by_id,
1559         .xstats_get_names_by_id = cnxk_nix_xstats_get_names_by_id,
1560         .fw_version_get = cnxk_nix_fw_version_get,
1561         .rxq_info_get = cnxk_nix_rxq_info_get,
1562         .txq_info_get = cnxk_nix_txq_info_get,
1563         .tx_done_cleanup = cnxk_nix_tx_done_cleanup,
1564         .flow_ops_get = cnxk_nix_flow_ops_get,
1565         .get_reg = cnxk_nix_dev_get_reg,
1566         .timesync_read_rx_timestamp = cnxk_nix_timesync_read_rx_timestamp,
1567         .timesync_read_tx_timestamp = cnxk_nix_timesync_read_tx_timestamp,
1568         .timesync_read_time = cnxk_nix_timesync_read_time,
1569         .timesync_write_time = cnxk_nix_timesync_write_time,
1570         .timesync_adjust_time = cnxk_nix_timesync_adjust_time,
1571         .read_clock = cnxk_nix_read_clock,
1572         .reta_update = cnxk_nix_reta_update,
1573         .reta_query = cnxk_nix_reta_query,
1574         .rss_hash_update = cnxk_nix_rss_hash_update,
1575         .rss_hash_conf_get = cnxk_nix_rss_hash_conf_get,
1576         .set_mc_addr_list = cnxk_nix_mc_addr_list_configure,
1577         .set_queue_rate_limit = cnxk_nix_tm_set_queue_rate_limit,
1578         .tm_ops_get = cnxk_nix_tm_ops_get,
1579         .mtr_ops_get = cnxk_nix_mtr_ops_get,
1580 };
1581
1582 static int
1583 cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)
1584 {
1585         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1586         struct rte_security_ctx *sec_ctx;
1587         struct roc_nix *nix = &dev->nix;
1588         struct rte_pci_device *pci_dev;
1589         int rc, max_entries;
1590
1591         eth_dev->dev_ops = &cnxk_eth_dev_ops;
1592
1593         /* Alloc security context */
1594         sec_ctx = plt_zmalloc(sizeof(struct rte_security_ctx), 0);
1595         if (!sec_ctx)
1596                 return -ENOMEM;
1597         sec_ctx->device = eth_dev;
1598         sec_ctx->ops = &cnxk_eth_sec_ops;
1599         sec_ctx->flags =
1600                 (RTE_SEC_CTX_F_FAST_SET_MDATA | RTE_SEC_CTX_F_FAST_GET_UDATA);
1601         eth_dev->security_ctx = sec_ctx;
1602         TAILQ_INIT(&dev->inb.list);
1603         TAILQ_INIT(&dev->outb.list);
1604
1605         /* For secondary processes, the primary has done all the work */
1606         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1607                 return 0;
1608
1609         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1610         rte_eth_copy_pci_info(eth_dev, pci_dev);
1611
1612         /* Parse devargs string */
1613         rc = cnxk_ethdev_parse_devargs(eth_dev->device->devargs, dev);
1614         if (rc) {
1615                 plt_err("Failed to parse devargs rc=%d", rc);
1616                 goto error;
1617         }
1618
1619         /* Initialize base roc nix */
1620         nix->pci_dev = pci_dev;
1621         nix->hw_vlan_ins = true;
1622         rc = roc_nix_dev_init(nix);
1623         if (rc) {
1624                 plt_err("Failed to initialize roc nix rc=%d", rc);
1625                 goto error;
1626         }
1627
1628         /* Register up msg callbacks */
1629         roc_nix_mac_link_cb_register(nix, cnxk_eth_dev_link_status_cb);
1630
1631         /* Register up msg callbacks */
1632         roc_nix_mac_link_info_get_cb_register(nix,
1633                                               cnxk_eth_dev_link_status_get_cb);
1634
1635         dev->eth_dev = eth_dev;
1636         dev->configured = 0;
1637         dev->ptype_disable = 0;
1638
1639         /* For vfs, returned max_entries will be 0. but to keep default mac
1640          * address, one entry must be allocated. so setting up to 1.
1641          */
1642         if (roc_nix_is_vf_or_sdp(nix))
1643                 max_entries = 1;
1644         else
1645                 max_entries = roc_nix_mac_max_entries_get(nix);
1646
1647         if (max_entries <= 0) {
1648                 plt_err("Failed to get max entries for mac addr");
1649                 rc = -ENOTSUP;
1650                 goto dev_fini;
1651         }
1652
1653         eth_dev->data->mac_addrs =
1654                 rte_zmalloc("mac_addr", max_entries * RTE_ETHER_ADDR_LEN, 0);
1655         if (eth_dev->data->mac_addrs == NULL) {
1656                 plt_err("Failed to allocate memory for mac addr");
1657                 rc = -ENOMEM;
1658                 goto dev_fini;
1659         }
1660
1661         dev->max_mac_entries = max_entries;
1662         dev->dmac_filter_count = 1;
1663
1664         /* Get mac address */
1665         rc = roc_nix_npc_mac_addr_get(nix, dev->mac_addr);
1666         if (rc) {
1667                 plt_err("Failed to get mac addr, rc=%d", rc);
1668                 goto free_mac_addrs;
1669         }
1670
1671         /* Update the mac address */
1672         memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1673
1674         if (!roc_nix_is_vf_or_sdp(nix)) {
1675                 /* Sync same MAC address to CGX/RPM table */
1676                 rc = roc_nix_mac_addr_set(nix, dev->mac_addr);
1677                 if (rc) {
1678                         plt_err("Failed to set mac addr, rc=%d", rc);
1679                         goto free_mac_addrs;
1680                 }
1681         }
1682
1683         /* Union of all capabilities supported by CNXK.
1684          * Platform specific capabilities will be
1685          * updated later.
1686          */
1687         dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
1688         dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
1689         dev->speed_capa = nix_get_speed_capa(dev);
1690
1691         /* Initialize roc npc */
1692         dev->npc.roc_nix = nix;
1693         rc = roc_npc_init(&dev->npc);
1694         if (rc)
1695                 goto free_mac_addrs;
1696
1697         plt_nix_dbg("Port=%d pf=%d vf=%d ver=%s hwcap=0x%" PRIx64
1698                     " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
1699                     eth_dev->data->port_id, roc_nix_get_pf(nix),
1700                     roc_nix_get_vf(nix), CNXK_ETH_DEV_PMD_VERSION, dev->hwcap,
1701                     dev->rx_offload_capa, dev->tx_offload_capa);
1702         return 0;
1703
1704 free_mac_addrs:
1705         rte_free(eth_dev->data->mac_addrs);
1706 dev_fini:
1707         roc_nix_dev_fini(nix);
1708 error:
1709         plt_err("Failed to init nix eth_dev rc=%d", rc);
1710         return rc;
1711 }
1712
1713 static int
1714 cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool reset)
1715 {
1716         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1717         const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
1718         struct roc_nix *nix = &dev->nix;
1719         int rc, i;
1720
1721         plt_free(eth_dev->security_ctx);
1722         eth_dev->security_ctx = NULL;
1723
1724         /* Nothing to be done for secondary processes */
1725         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1726                 return 0;
1727
1728         /* Clear the flag since we are closing down */
1729         dev->configured = 0;
1730
1731         roc_nix_npc_rx_ena_dis(nix, false);
1732
1733         /* Disable and free rte_meter entries */
1734         nix_meter_fini(dev);
1735
1736         /* Disable and free rte_flow entries */
1737         roc_npc_fini(&dev->npc);
1738
1739         /* Disable link status events */
1740         roc_nix_mac_link_event_start_stop(nix, false);
1741
1742         /* Unregister the link update op, this is required to stop VFs from
1743          * receiving link status updates on exit path.
1744          */
1745         roc_nix_mac_link_cb_unregister(nix);
1746
1747         /* Free up SQs */
1748         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1749                 dev_ops->tx_queue_release(eth_dev, i);
1750                 eth_dev->data->tx_queues[i] = NULL;
1751         }
1752         eth_dev->data->nb_tx_queues = 0;
1753
1754         /* Free up RQ's and CQ's */
1755         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1756                 dev_ops->rx_queue_release(eth_dev, i);
1757                 eth_dev->data->rx_queues[i] = NULL;
1758         }
1759         eth_dev->data->nb_rx_queues = 0;
1760
1761         /* Free security resources */
1762         nix_security_release(dev);
1763
1764         /* Free tm resources */
1765         roc_nix_tm_fini(nix);
1766
1767         /* Unregister queue irqs */
1768         roc_nix_unregister_queue_irqs(nix);
1769
1770         /* Unregister cq irqs */
1771         if (eth_dev->data->dev_conf.intr_conf.rxq)
1772                 roc_nix_unregister_cq_irqs(nix);
1773
1774         /* Free ROC RQ's, SQ's and CQ's memory */
1775         nix_free_queue_mem(dev);
1776
1777         /* Free nix lf resources */
1778         rc = roc_nix_lf_free(nix);
1779         if (rc)
1780                 plt_err("Failed to free nix lf, rc=%d", rc);
1781
1782         rte_free(eth_dev->data->mac_addrs);
1783         eth_dev->data->mac_addrs = NULL;
1784
1785         rc = roc_nix_dev_fini(nix);
1786         /* Can be freed later by PMD if NPA LF is in use */
1787         if (rc == -EAGAIN) {
1788                 if (!reset)
1789                         eth_dev->data->dev_private = NULL;
1790                 return 0;
1791         } else if (rc) {
1792                 plt_err("Failed in nix dev fini, rc=%d", rc);
1793         }
1794
1795         return rc;
1796 }
1797
1798 static int
1799 cnxk_nix_dev_close(struct rte_eth_dev *eth_dev)
1800 {
1801         cnxk_eth_dev_uninit(eth_dev, false);
1802         return 0;
1803 }
1804
1805 static int
1806 cnxk_nix_dev_reset(struct rte_eth_dev *eth_dev)
1807 {
1808         int rc;
1809
1810         rc = cnxk_eth_dev_uninit(eth_dev, true);
1811         if (rc)
1812                 return rc;
1813
1814         return cnxk_eth_dev_init(eth_dev);
1815 }
1816
1817 int
1818 cnxk_nix_remove(struct rte_pci_device *pci_dev)
1819 {
1820         struct rte_eth_dev *eth_dev;
1821         struct roc_nix *nix;
1822         int rc = -EINVAL;
1823
1824         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
1825         if (eth_dev) {
1826                 /* Cleanup eth dev */
1827                 rc = cnxk_eth_dev_uninit(eth_dev, false);
1828                 if (rc)
1829                         return rc;
1830
1831                 rte_eth_dev_release_port(eth_dev);
1832         }
1833
1834         /* Nothing to be done for secondary processes */
1835         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1836                 return 0;
1837
1838         /* Check if this device is hosting common resource */
1839         nix = roc_idev_npa_nix_get();
1840         if (nix->pci_dev != pci_dev)
1841                 return 0;
1842
1843         /* Try nix fini now */
1844         rc = roc_nix_dev_fini(nix);
1845         if (rc == -EAGAIN) {
1846                 plt_info("%s: common resource in use by other devices",
1847                          pci_dev->name);
1848                 goto exit;
1849         } else if (rc) {
1850                 plt_err("Failed in nix dev fini, rc=%d", rc);
1851                 goto exit;
1852         }
1853
1854         /* Free device pointer as rte_ethdev does not have it anymore */
1855         rte_free(nix);
1856 exit:
1857         return rc;
1858 }
1859
1860 int
1861 cnxk_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1862 {
1863         int rc;
1864
1865         RTE_SET_USED(pci_drv);
1866
1867         rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct cnxk_eth_dev),
1868                                            cnxk_eth_dev_init);
1869
1870         /* On error on secondary, recheck if port exists in primary or
1871          * in mid of detach state.
1872          */
1873         if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
1874                 if (!rte_eth_dev_allocated(pci_dev->device.name))
1875                         return 0;
1876         return rc;
1877 }