drivers/net/cnxk/cnxk_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4 #include <cnxk_ethdev.h>
   5
   6 static inline uint64_t
   7 nix_get_rx_offload_capa(struct cnxk_eth_dev *dev)
   8 {
   9         uint64_t capa = CNXK_NIX_RX_OFFLOAD_CAPA;
  10
  11         if (roc_nix_is_vf_or_sdp(&dev->nix) ||
  12             dev->npc.switch_header_type == ROC_PRIV_FLAGS_HIGIG)
  13                 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
  14
  15         return capa;
  16 }
  17
  18 static inline uint64_t
  19 nix_get_tx_offload_capa(struct cnxk_eth_dev *dev)
  20 {
  21         RTE_SET_USED(dev);
  22         return CNXK_NIX_TX_OFFLOAD_CAPA;
  23 }
  24
  25 static inline uint32_t
  26 nix_get_speed_capa(struct cnxk_eth_dev *dev)
  27 {
  28         uint32_t speed_capa;
  29
  30         /* Auto negotiation disabled */
  31         speed_capa = ETH_LINK_SPEED_FIXED;
  32         if (!roc_nix_is_vf_or_sdp(&dev->nix) && !roc_nix_is_lbk(&dev->nix)) {
  33                 speed_capa |= ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
  34                               ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
  35                               ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
  36         }
  37
  38         return speed_capa;
  39 }
  40
  41 int
  42 cnxk_nix_inb_mode_set(struct cnxk_eth_dev *dev, bool use_inl_dev)
  43 {
  44         struct roc_nix *nix = &dev->nix;
  45
  46         if (dev->inb.inl_dev == use_inl_dev)
  47                 return 0;
  48
  49         plt_nix_dbg("Security sessions(%u) still active, inl=%u!!!",
  50                     dev->inb.nb_sess, !!dev->inb.inl_dev);
  51
  52         /* Change the mode */
  53         dev->inb.inl_dev = use_inl_dev;
  54
  55         /* Update RoC for NPC rule insertion */
  56         roc_nix_inb_mode_set(nix, use_inl_dev);
  57
  58         /* Setup lookup mem */
  59         return cnxk_nix_lookup_mem_sa_base_set(dev);
  60 }
  61
  62 static int
  63 nix_security_setup(struct cnxk_eth_dev *dev)
  64 {
  65         struct roc_nix *nix = &dev->nix;
  66         int i, rc = 0;
  67
  68         if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
  69                 /* Setup Inline Inbound */
  70                 rc = roc_nix_inl_inb_init(nix);
  71                 if (rc) {
  72                         plt_err("Failed to initialize nix inline inb, rc=%d",
  73                                 rc);
  74                         return rc;
  75                 }
  76
  77                 /* By default pick using inline device for poll mode.
  78                  * Will be overridden when event mode rq's are setup.
  79                  */
  80                 cnxk_nix_inb_mode_set(dev, true);
  81         }
  82
  83         if (dev->tx_offloads & DEV_TX_OFFLOAD_SECURITY ||
  84             dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
  85                 struct plt_bitmap *bmap;
  86                 size_t bmap_sz;
  87                 void *mem;
  88
  89                 /* Setup enough descriptors for all tx queues */
  90                 nix->outb_nb_desc = dev->outb.nb_desc;
  91                 nix->outb_nb_crypto_qs = dev->outb.nb_crypto_qs;
  92
  93                 /* Setup Inline Outbound */
  94                 rc = roc_nix_inl_outb_init(nix);
  95                 if (rc) {
  96                         plt_err("Failed to initialize nix inline outb, rc=%d",
  97                                 rc);
  98                         goto cleanup;
  99                 }
 100
 101                 dev->outb.lf_base = roc_nix_inl_outb_lf_base_get(nix);
 102
 103                 /* Skip the rest if DEV_TX_OFFLOAD_SECURITY is not enabled */
 104                 if (!(dev->tx_offloads & DEV_TX_OFFLOAD_SECURITY))
 105                         goto done;
 106
 107                 rc = -ENOMEM;
 108                 /* Allocate a bitmap to alloc and free sa indexes */
 109                 bmap_sz = plt_bitmap_get_memory_footprint(dev->outb.max_sa);
 110                 mem = plt_zmalloc(bmap_sz, PLT_CACHE_LINE_SIZE);
 111                 if (mem == NULL) {
 112                         plt_err("Outbound SA bmap alloc failed");
 113
 114                         rc |= roc_nix_inl_outb_fini(nix);
 115                         goto cleanup;
 116                 }
 117
 118                 rc = -EIO;
 119                 bmap = plt_bitmap_init(dev->outb.max_sa, mem, bmap_sz);
 120                 if (!bmap) {
 121                         plt_err("Outbound SA bmap init failed");
 122
 123                         rc |= roc_nix_inl_outb_fini(nix);
 124                         plt_free(mem);
 125                         goto cleanup;
 126                 }
 127
 128                 for (i = 0; i < dev->outb.max_sa; i++)
 129                         plt_bitmap_set(bmap, i);
 130
 131                 dev->outb.sa_base = roc_nix_inl_outb_sa_base_get(nix);
 132                 dev->outb.sa_bmap_mem = mem;
 133                 dev->outb.sa_bmap = bmap;
 134         }
 135
 136 done:
 137         return 0;
 138 cleanup:
 139         if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY)
 140                 rc |= roc_nix_inl_inb_fini(nix);
 141         return rc;
 142 }
 143
 144 static int
 145 nix_security_release(struct cnxk_eth_dev *dev)
 146 {
 147         struct rte_eth_dev *eth_dev = dev->eth_dev;
 148         struct cnxk_eth_sec_sess *eth_sec, *tvar;
 149         struct roc_nix *nix = &dev->nix;
 150         int rc, ret = 0;
 151
 152         /* Cleanup Inline inbound */
 153         if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
 154                 /* Destroy inbound sessions */
 155                 tvar = NULL;
 156                 RTE_TAILQ_FOREACH_SAFE(eth_sec, &dev->inb.list, entry, tvar)
 157                         cnxk_eth_sec_ops.session_destroy(eth_dev,
 158                                                          eth_sec->sess);
 159
 160                 /* Clear lookup mem */
 161                 cnxk_nix_lookup_mem_sa_base_clear(dev);
 162
 163                 rc = roc_nix_inl_inb_fini(nix);
 164                 if (rc)
 165                         plt_err("Failed to cleanup nix inline inb, rc=%d", rc);
 166                 ret |= rc;
 167         }
 168
 169         /* Cleanup Inline outbound */
 170         if (dev->tx_offloads & DEV_TX_OFFLOAD_SECURITY ||
 171             dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
 172                 /* Destroy outbound sessions */
 173                 tvar = NULL;
 174                 RTE_TAILQ_FOREACH_SAFE(eth_sec, &dev->outb.list, entry, tvar)
 175                         cnxk_eth_sec_ops.session_destroy(eth_dev,
 176                                                          eth_sec->sess);
 177
 178                 rc = roc_nix_inl_outb_fini(nix);
 179                 if (rc)
 180                         plt_err("Failed to cleanup nix inline outb, rc=%d", rc);
 181                 ret |= rc;
 182
 183                 plt_bitmap_free(dev->outb.sa_bmap);
 184                 plt_free(dev->outb.sa_bmap_mem);
 185                 dev->outb.sa_bmap = NULL;
 186                 dev->outb.sa_bmap_mem = NULL;
 187         }
 188
 189         dev->inb.inl_dev = false;
 190         roc_nix_inb_mode_set(nix, false);
 191         dev->nb_rxq_sso = 0;
 192         dev->inb.nb_sess = 0;
 193         dev->outb.nb_sess = 0;
 194         return ret;
 195 }
 196
 197 static void
 198 nix_enable_mseg_on_jumbo(struct cnxk_eth_rxq_sp *rxq)
 199 {
 200         struct rte_pktmbuf_pool_private *mbp_priv;
 201         struct rte_eth_dev *eth_dev;
 202         struct cnxk_eth_dev *dev;
 203         uint32_t buffsz;
 204
 205         dev = rxq->dev;
 206         eth_dev = dev->eth_dev;
 207
 208         /* Get rx buffer size */
 209         mbp_priv = rte_mempool_get_priv(rxq->qconf.mp);
 210         buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
 211
 212         if (eth_dev->data->mtu + (uint32_t)CNXK_NIX_L2_OVERHEAD > buffsz) {
 213                 dev->rx_offloads |= DEV_RX_OFFLOAD_SCATTER;
 214                 dev->tx_offloads |= DEV_TX_OFFLOAD_MULTI_SEGS;
 215         }
 216 }
 217
 218 int
 219 nix_recalc_mtu(struct rte_eth_dev *eth_dev)
 220 {
 221         struct rte_eth_dev_data *data = eth_dev->data;
 222         struct cnxk_eth_rxq_sp *rxq;
 223         int rc;
 224
 225         rxq = ((struct cnxk_eth_rxq_sp *)data->rx_queues[0]) - 1;
 226         /* Setup scatter mode if needed by jumbo */
 227         nix_enable_mseg_on_jumbo(rxq);
 228
 229         rc = cnxk_nix_mtu_set(eth_dev, data->mtu);
 230         if (rc)
 231                 plt_err("Failed to set default MTU size, rc=%d", rc);
 232
 233         return rc;
 234 }
 235
 236 static int
 237 nix_init_flow_ctrl_config(struct rte_eth_dev *eth_dev)
 238 {
 239         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 240         struct cnxk_fc_cfg *fc = &dev->fc_cfg;
 241         struct rte_eth_fc_conf fc_conf = {0};
 242         int rc;
 243
 244         /* Both Rx & Tx flow ctrl get enabled(RTE_FC_FULL) in HW
 245          * by AF driver, update those info in PMD structure.
 246          */
 247         rc = cnxk_nix_flow_ctrl_get(eth_dev, &fc_conf);
 248         if (rc)
 249                 goto exit;
 250
 251         fc->mode = fc_conf.mode;
 252         fc->rx_pause = (fc_conf.mode == RTE_FC_FULL) ||
 253                         (fc_conf.mode == RTE_FC_RX_PAUSE);
 254         fc->tx_pause = (fc_conf.mode == RTE_FC_FULL) ||
 255                         (fc_conf.mode == RTE_FC_TX_PAUSE);
 256
 257 exit:
 258         return rc;
 259 }
 260
 261 static int
 262 nix_update_flow_ctrl_config(struct rte_eth_dev *eth_dev)
 263 {
 264         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 265         struct cnxk_fc_cfg *fc = &dev->fc_cfg;
 266         struct rte_eth_fc_conf fc_cfg = {0};
 267
 268         if (roc_nix_is_vf_or_sdp(&dev->nix))
 269                 return 0;
 270
 271         fc_cfg.mode = fc->mode;
 272
 273         /* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */
 274         if (roc_model_is_cn96_ax() &&
 275             dev->npc.switch_header_type != ROC_PRIV_FLAGS_HIGIG &&
 276             (fc_cfg.mode == RTE_FC_FULL || fc_cfg.mode == RTE_FC_RX_PAUSE)) {
 277                 fc_cfg.mode =
 278                                 (fc_cfg.mode == RTE_FC_FULL ||
 279                                 fc_cfg.mode == RTE_FC_TX_PAUSE) ?
 280                                 RTE_FC_TX_PAUSE : RTE_FC_NONE;
 281         }
 282
 283         return cnxk_nix_flow_ctrl_set(eth_dev, &fc_cfg);
 284 }
 285
 286 uint64_t
 287 cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev)
 288 {
 289         uint16_t port_id = dev->eth_dev->data->port_id;
 290         struct rte_mbuf mb_def;
 291         uint64_t *tmp;
 292
 293         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
 294         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
 295                                  offsetof(struct rte_mbuf, data_off) !=
 296                          2);
 297         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
 298                                  offsetof(struct rte_mbuf, data_off) !=
 299                          4);
 300         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
 301                                  offsetof(struct rte_mbuf, data_off) !=
 302                          6);
 303         mb_def.nb_segs = 1;
 304         mb_def.data_off = RTE_PKTMBUF_HEADROOM +
 305                           (dev->ptp_en * CNXK_NIX_TIMESYNC_RX_OFFSET);
 306         mb_def.port = port_id;
 307         rte_mbuf_refcnt_set(&mb_def, 1);
 308
 309         /* Prevent compiler reordering: rearm_data covers previous fields */
 310         rte_compiler_barrier();
 311         tmp = (uint64_t *)&mb_def.rearm_data;
 312
 313         return *tmp;
 314 }
 315
 316 static inline uint8_t
 317 nix_sq_max_sqe_sz(struct cnxk_eth_dev *dev)
 318 {
 319         /*
 320          * Maximum three segments can be supported with W8, Choose
 321          * NIX_MAXSQESZ_W16 for multi segment offload.
 322          */
 323         if (dev->tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
 324                 return NIX_MAXSQESZ_W16;
 325         else
 326                 return NIX_MAXSQESZ_W8;
 327 }
 328
 329 int
 330 cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 331                         uint16_t nb_desc, uint16_t fp_tx_q_sz,
 332                         const struct rte_eth_txconf *tx_conf)
 333 {
 334         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 335         const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
 336         struct cnxk_eth_txq_sp *txq_sp;
 337         struct roc_nix_sq *sq;
 338         size_t txq_sz;
 339         int rc;
 340
 341         /* Free memory prior to re-allocation if needed. */
 342         if (eth_dev->data->tx_queues[qid] != NULL) {
 343                 plt_nix_dbg("Freeing memory prior to re-allocation %d", qid);
 344                 dev_ops->tx_queue_release(eth_dev, qid);
 345                 eth_dev->data->tx_queues[qid] = NULL;
 346         }
 347
 348         /* When Tx Security offload is enabled, increase tx desc count by
 349          * max possible outbound desc count.
 350          */
 351         if (dev->tx_offloads & DEV_TX_OFFLOAD_SECURITY)
 352                 nb_desc += dev->outb.nb_desc;
 353
 354         /* Setup ROC SQ */
 355         sq = &dev->sqs[qid];
 356         sq->qid = qid;
 357         sq->nb_desc = nb_desc;
 358         sq->max_sqe_sz = nix_sq_max_sqe_sz(dev);
 359
 360         rc = roc_nix_sq_init(&dev->nix, sq);
 361         if (rc) {
 362                 plt_err("Failed to init sq=%d, rc=%d", qid, rc);
 363                 return rc;
 364         }
 365
 366         rc = -ENOMEM;
 367         txq_sz = sizeof(struct cnxk_eth_txq_sp) + fp_tx_q_sz;
 368         txq_sp = plt_zmalloc(txq_sz, PLT_CACHE_LINE_SIZE);
 369         if (!txq_sp) {
 370                 plt_err("Failed to alloc tx queue mem");
 371                 rc |= roc_nix_sq_fini(sq);
 372                 return rc;
 373         }
 374
 375         txq_sp->dev = dev;
 376         txq_sp->qid = qid;
 377         txq_sp->qconf.conf.tx = *tx_conf;
 378         /* Queue config should reflect global offloads */
 379         txq_sp->qconf.conf.tx.offloads = dev->tx_offloads;
 380         txq_sp->qconf.nb_desc = nb_desc;
 381
 382         plt_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " lmt_addr=%p"
 383                     " nb_sqb_bufs=%d sqes_per_sqb_log2=%d",
 384                     qid, sq->fc, dev->tx_offloads, sq->lmt_addr,
 385                     sq->nb_sqb_bufs, sq->sqes_per_sqb_log2);
 386
 387         /* Store start of fast path area */
 388         eth_dev->data->tx_queues[qid] = txq_sp + 1;
 389         eth_dev->data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
 390         return 0;
 391 }
 392
 393 static void
 394 cnxk_nix_tx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)
 395 {
 396         void *txq = eth_dev->data->tx_queues[qid];
 397         struct cnxk_eth_txq_sp *txq_sp;
 398         struct cnxk_eth_dev *dev;
 399         struct roc_nix_sq *sq;
 400         int rc;
 401
 402         if (!txq)
 403                 return;
 404
 405         txq_sp = cnxk_eth_txq_to_sp(txq);
 406
 407         dev = txq_sp->dev;
 408
 409         plt_nix_dbg("Releasing txq %u", qid);
 410
 411         /* Cleanup ROC SQ */
 412         sq = &dev->sqs[qid];
 413         rc = roc_nix_sq_fini(sq);
 414         if (rc)
 415                 plt_err("Failed to cleanup sq, rc=%d", rc);
 416
 417         /* Finally free */
 418         plt_free(txq_sp);
 419 }
 420
 421 int
 422 cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 423                         uint16_t nb_desc, uint16_t fp_rx_q_sz,
 424                         const struct rte_eth_rxconf *rx_conf,
 425                         struct rte_mempool *mp)
 426 {
 427         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 428         struct roc_nix *nix = &dev->nix;
 429         struct cnxk_eth_rxq_sp *rxq_sp;
 430         struct rte_mempool_ops *ops;
 431         const char *platform_ops;
 432         struct roc_nix_rq *rq;
 433         struct roc_nix_cq *cq;
 434         uint16_t first_skip;
 435         int rc = -EINVAL;
 436         size_t rxq_sz;
 437
 438         /* Sanity checks */
 439         if (rx_conf->rx_deferred_start == 1) {
 440                 plt_err("Deferred Rx start is not supported");
 441                 goto fail;
 442         }
 443
 444         platform_ops = rte_mbuf_platform_mempool_ops();
 445         /* This driver needs cnxk_npa mempool ops to work */
 446         ops = rte_mempool_get_ops(mp->ops_index);
 447         if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
 448                 plt_err("mempool ops should be of cnxk_npa type");
 449                 goto fail;
 450         }
 451
 452         if (mp->pool_id == 0) {
 453                 plt_err("Invalid pool_id");
 454                 goto fail;
 455         }
 456
 457         /* Free memory prior to re-allocation if needed */
 458         if (eth_dev->data->rx_queues[qid] != NULL) {
 459                 const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
 460
 461                 plt_nix_dbg("Freeing memory prior to re-allocation %d", qid);
 462                 dev_ops->rx_queue_release(eth_dev, qid);
 463                 eth_dev->data->rx_queues[qid] = NULL;
 464         }
 465
 466         /* Clam up cq limit to size of packet pool aura for LBK
 467          * to avoid meta packet drop as LBK does not currently support
 468          * backpressure.
 469          */
 470         if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY && roc_nix_is_lbk(nix)) {
 471                 uint64_t pkt_pool_limit = roc_nix_inl_dev_rq_limit_get();
 472
 473                 /* Use current RQ's aura limit if inl rq is not available */
 474                 if (!pkt_pool_limit)
 475                         pkt_pool_limit = roc_npa_aura_op_limit_get(mp->pool_id);
 476                 nb_desc = RTE_MAX(nb_desc, pkt_pool_limit);
 477         }
 478
 479         /* Setup ROC CQ */
 480         cq = &dev->cqs[qid];
 481         cq->qid = qid;
 482         cq->nb_desc = nb_desc;
 483         rc = roc_nix_cq_init(&dev->nix, cq);
 484         if (rc) {
 485                 plt_err("Failed to init roc cq for rq=%d, rc=%d", qid, rc);
 486                 goto fail;
 487         }
 488
 489         /* Setup ROC RQ */
 490         rq = &dev->rqs[qid];
 491         rq->qid = qid;
 492         rq->aura_handle = mp->pool_id;
 493         rq->flow_tag_width = 32;
 494         rq->sso_ena = false;
 495
 496         /* Calculate first mbuf skip */
 497         first_skip = (sizeof(struct rte_mbuf));
 498         first_skip += RTE_PKTMBUF_HEADROOM;
 499         first_skip += rte_pktmbuf_priv_size(mp);
 500         rq->first_skip = first_skip;
 501         rq->later_skip = sizeof(struct rte_mbuf);
 502         rq->lpb_size = mp->elt_size;
 503
 504         /* Enable Inline IPSec on RQ, will not be used for Poll mode */
 505         if (roc_nix_inl_inb_is_enabled(nix))
 506                 rq->ipsech_ena = true;
 507
 508         rc = roc_nix_rq_init(&dev->nix, rq, !!eth_dev->data->dev_started);
 509         if (rc) {
 510                 plt_err("Failed to init roc rq for rq=%d, rc=%d", qid, rc);
 511                 goto cq_fini;
 512         }
 513
 514         /* Allocate and setup fast path rx queue */
 515         rc = -ENOMEM;
 516         rxq_sz = sizeof(struct cnxk_eth_rxq_sp) + fp_rx_q_sz;
 517         rxq_sp = plt_zmalloc(rxq_sz, PLT_CACHE_LINE_SIZE);
 518         if (!rxq_sp) {
 519                 plt_err("Failed to alloc rx queue for rq=%d", qid);
 520                 goto rq_fini;
 521         }
 522
 523         /* Setup slow path fields */
 524         rxq_sp->dev = dev;
 525         rxq_sp->qid = qid;
 526         rxq_sp->qconf.conf.rx = *rx_conf;
 527         /* Queue config should reflect global offloads */
 528         rxq_sp->qconf.conf.rx.offloads = dev->rx_offloads;
 529         rxq_sp->qconf.nb_desc = nb_desc;
 530         rxq_sp->qconf.mp = mp;
 531
 532         if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
 533                 /* Setup rq reference for inline dev if present */
 534                 rc = roc_nix_inl_dev_rq_get(rq);
 535                 if (rc)
 536                         goto free_mem;
 537         }
 538
 539         plt_nix_dbg("rq=%d pool=%s nb_desc=%d->%d", qid, mp->name, nb_desc,
 540                     cq->nb_desc);
 541
 542         /* Store start of fast path area */
 543         eth_dev->data->rx_queues[qid] = rxq_sp + 1;
 544         eth_dev->data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
 545
 546         /* Calculating delta and freq mult between PTP HI clock and tsc.
 547          * These are needed in deriving raw clock value from tsc counter.
 548          * read_clock eth op returns raw clock value.
 549          */
 550         if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) || dev->ptp_en) {
 551                 rc = cnxk_nix_tsc_convert(dev);
 552                 if (rc) {
 553                         plt_err("Failed to calculate delta and freq mult");
 554                         goto rq_fini;
 555                 }
 556         }
 557
 558         return 0;
 559 free_mem:
 560         plt_free(rxq_sp);
 561 rq_fini:
 562         rc |= roc_nix_rq_fini(rq);
 563 cq_fini:
 564         rc |= roc_nix_cq_fini(cq);
 565 fail:
 566         return rc;
 567 }
 568
 569 static void
 570 cnxk_nix_rx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)
 571 {
 572         void *rxq = eth_dev->data->rx_queues[qid];
 573         struct cnxk_eth_rxq_sp *rxq_sp;
 574         struct cnxk_eth_dev *dev;
 575         struct roc_nix_rq *rq;
 576         struct roc_nix_cq *cq;
 577         int rc;
 578
 579         if (!rxq)
 580                 return;
 581
 582         rxq_sp = cnxk_eth_rxq_to_sp(rxq);
 583         dev = rxq_sp->dev;
 584         rq = &dev->rqs[qid];
 585
 586         plt_nix_dbg("Releasing rxq %u", qid);
 587
 588         /* Release rq reference for inline dev if present */
 589         if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY)
 590                 roc_nix_inl_dev_rq_put(rq);
 591
 592         /* Cleanup ROC RQ */
 593         rc = roc_nix_rq_fini(rq);
 594         if (rc)
 595                 plt_err("Failed to cleanup rq, rc=%d", rc);
 596
 597         /* Cleanup ROC CQ */
 598         cq = &dev->cqs[qid];
 599         rc = roc_nix_cq_fini(cq);
 600         if (rc)
 601                 plt_err("Failed to cleanup cq, rc=%d", rc);
 602
 603         /* Finally free fast path area */
 604         plt_free(rxq_sp);
 605 }
 606
 607 uint32_t
 608 cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
 609                        uint8_t rss_level)
 610 {
 611         uint32_t flow_key_type[RSS_MAX_LEVELS][6] = {
 612                 {FLOW_KEY_TYPE_IPV4, FLOW_KEY_TYPE_IPV6, FLOW_KEY_TYPE_TCP,
 613                  FLOW_KEY_TYPE_UDP, FLOW_KEY_TYPE_SCTP, FLOW_KEY_TYPE_ETH_DMAC},
 614                 {FLOW_KEY_TYPE_INNR_IPV4, FLOW_KEY_TYPE_INNR_IPV6,
 615                  FLOW_KEY_TYPE_INNR_TCP, FLOW_KEY_TYPE_INNR_UDP,
 616                  FLOW_KEY_TYPE_INNR_SCTP, FLOW_KEY_TYPE_INNR_ETH_DMAC},
 617                 {FLOW_KEY_TYPE_IPV4 | FLOW_KEY_TYPE_INNR_IPV4,
 618                  FLOW_KEY_TYPE_IPV6 | FLOW_KEY_TYPE_INNR_IPV6,
 619                  FLOW_KEY_TYPE_TCP | FLOW_KEY_TYPE_INNR_TCP,
 620                  FLOW_KEY_TYPE_UDP | FLOW_KEY_TYPE_INNR_UDP,
 621                  FLOW_KEY_TYPE_SCTP | FLOW_KEY_TYPE_INNR_SCTP,
 622                  FLOW_KEY_TYPE_ETH_DMAC | FLOW_KEY_TYPE_INNR_ETH_DMAC}
 623         };
 624         uint32_t flowkey_cfg = 0;
 625
 626         dev->ethdev_rss_hf = ethdev_rss;
 627
 628         if (ethdev_rss & ETH_RSS_L2_PAYLOAD &&
 629             dev->npc.switch_header_type == ROC_PRIV_FLAGS_LEN_90B) {
 630                 flowkey_cfg |= FLOW_KEY_TYPE_CH_LEN_90B;
 631         }
 632
 633         if (ethdev_rss & ETH_RSS_C_VLAN)
 634                 flowkey_cfg |= FLOW_KEY_TYPE_VLAN;
 635
 636         if (ethdev_rss & ETH_RSS_L3_SRC_ONLY)
 637                 flowkey_cfg |= FLOW_KEY_TYPE_L3_SRC;
 638
 639         if (ethdev_rss & ETH_RSS_L3_DST_ONLY)
 640                 flowkey_cfg |= FLOW_KEY_TYPE_L3_DST;
 641
 642         if (ethdev_rss & ETH_RSS_L4_SRC_ONLY)
 643                 flowkey_cfg |= FLOW_KEY_TYPE_L4_SRC;
 644
 645         if (ethdev_rss & ETH_RSS_L4_DST_ONLY)
 646                 flowkey_cfg |= FLOW_KEY_TYPE_L4_DST;
 647
 648         if (ethdev_rss & RSS_IPV4_ENABLE)
 649                 flowkey_cfg |= flow_key_type[rss_level][RSS_IPV4_INDEX];
 650
 651         if (ethdev_rss & RSS_IPV6_ENABLE)
 652                 flowkey_cfg |= flow_key_type[rss_level][RSS_IPV6_INDEX];
 653
 654         if (ethdev_rss & ETH_RSS_TCP)
 655                 flowkey_cfg |= flow_key_type[rss_level][RSS_TCP_INDEX];
 656
 657         if (ethdev_rss & ETH_RSS_UDP)
 658                 flowkey_cfg |= flow_key_type[rss_level][RSS_UDP_INDEX];
 659
 660         if (ethdev_rss & ETH_RSS_SCTP)
 661                 flowkey_cfg |= flow_key_type[rss_level][RSS_SCTP_INDEX];
 662
 663         if (ethdev_rss & ETH_RSS_L2_PAYLOAD)
 664                 flowkey_cfg |= flow_key_type[rss_level][RSS_DMAC_INDEX];
 665
 666         if (ethdev_rss & RSS_IPV6_EX_ENABLE)
 667                 flowkey_cfg |= FLOW_KEY_TYPE_IPV6_EXT;
 668
 669         if (ethdev_rss & ETH_RSS_PORT)
 670                 flowkey_cfg |= FLOW_KEY_TYPE_PORT;
 671
 672         if (ethdev_rss & ETH_RSS_NVGRE)
 673                 flowkey_cfg |= FLOW_KEY_TYPE_NVGRE;
 674
 675         if (ethdev_rss & ETH_RSS_VXLAN)
 676                 flowkey_cfg |= FLOW_KEY_TYPE_VXLAN;
 677
 678         if (ethdev_rss & ETH_RSS_GENEVE)
 679                 flowkey_cfg |= FLOW_KEY_TYPE_GENEVE;
 680
 681         if (ethdev_rss & ETH_RSS_GTPU)
 682                 flowkey_cfg |= FLOW_KEY_TYPE_GTPU;
 683
 684         return flowkey_cfg;
 685 }
 686
 687 static void
 688 nix_free_queue_mem(struct cnxk_eth_dev *dev)
 689 {
 690         plt_free(dev->rqs);
 691         plt_free(dev->cqs);
 692         plt_free(dev->sqs);
 693         dev->rqs = NULL;
 694         dev->cqs = NULL;
 695         dev->sqs = NULL;
 696 }
 697
 698 static int
 699 nix_ingress_policer_setup(struct cnxk_eth_dev *dev)
 700 {
 701         TAILQ_INIT(&dev->mtr_profiles);
 702         TAILQ_INIT(&dev->mtr_policy);
 703
 704         return 0;
 705 }
 706
 707 static int
 708 nix_rss_default_setup(struct cnxk_eth_dev *dev)
 709 {
 710         struct rte_eth_dev *eth_dev = dev->eth_dev;
 711         uint8_t rss_hash_level;
 712         uint32_t flowkey_cfg;
 713         uint64_t rss_hf;
 714
 715         rss_hf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
 716         rss_hash_level = ETH_RSS_LEVEL(rss_hf);
 717         if (rss_hash_level)
 718                 rss_hash_level -= 1;
 719
 720         flowkey_cfg = cnxk_rss_ethdev_to_nix(dev, rss_hf, rss_hash_level);
 721         return roc_nix_rss_default_setup(&dev->nix, flowkey_cfg);
 722 }
 723
 724 static int
 725 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
 726 {
 727         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 728         const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
 729         struct cnxk_eth_qconf *tx_qconf = NULL;
 730         struct cnxk_eth_qconf *rx_qconf = NULL;
 731         struct cnxk_eth_rxq_sp *rxq_sp;
 732         struct cnxk_eth_txq_sp *txq_sp;
 733         int i, nb_rxq, nb_txq;
 734         void **txq, **rxq;
 735
 736         nb_rxq = RTE_MIN(dev->nb_rxq, eth_dev->data->nb_rx_queues);
 737         nb_txq = RTE_MIN(dev->nb_txq, eth_dev->data->nb_tx_queues);
 738
 739         tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
 740         if (tx_qconf == NULL) {
 741                 plt_err("Failed to allocate memory for tx_qconf");
 742                 goto fail;
 743         }
 744
 745         rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
 746         if (rx_qconf == NULL) {
 747                 plt_err("Failed to allocate memory for rx_qconf");
 748                 goto fail;
 749         }
 750
 751         txq = eth_dev->data->tx_queues;
 752         for (i = 0; i < nb_txq; i++) {
 753                 if (txq[i] == NULL) {
 754                         tx_qconf[i].valid = false;
 755                         plt_info("txq[%d] is already released", i);
 756                         continue;
 757                 }
 758                 txq_sp = cnxk_eth_txq_to_sp(txq[i]);
 759                 memcpy(&tx_qconf[i], &txq_sp->qconf, sizeof(*tx_qconf));
 760                 tx_qconf[i].valid = true;
 761                 dev_ops->tx_queue_release(eth_dev, i);
 762                 eth_dev->data->tx_queues[i] = NULL;
 763         }
 764
 765         rxq = eth_dev->data->rx_queues;
 766         for (i = 0; i < nb_rxq; i++) {
 767                 if (rxq[i] == NULL) {
 768                         rx_qconf[i].valid = false;
 769                         plt_info("rxq[%d] is already released", i);
 770                         continue;
 771                 }
 772                 rxq_sp = cnxk_eth_rxq_to_sp(rxq[i]);
 773                 memcpy(&rx_qconf[i], &rxq_sp->qconf, sizeof(*rx_qconf));
 774                 rx_qconf[i].valid = true;
 775                 dev_ops->rx_queue_release(eth_dev, i);
 776                 eth_dev->data->rx_queues[i] = NULL;
 777         }
 778
 779         dev->tx_qconf = tx_qconf;
 780         dev->rx_qconf = rx_qconf;
 781         return 0;
 782
 783 fail:
 784         free(tx_qconf);
 785         free(rx_qconf);
 786         return -ENOMEM;
 787 }
 788
 789 static int
 790 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
 791 {
 792         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 793         const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
 794         struct cnxk_eth_qconf *tx_qconf = dev->tx_qconf;
 795         struct cnxk_eth_qconf *rx_qconf = dev->rx_qconf;
 796         int rc, i, nb_rxq, nb_txq;
 797
 798         nb_rxq = RTE_MIN(dev->nb_rxq, eth_dev->data->nb_rx_queues);
 799         nb_txq = RTE_MIN(dev->nb_txq, eth_dev->data->nb_tx_queues);
 800
 801         rc = -ENOMEM;
 802         /* Setup tx & rx queues with previous configuration so
 803          * that the queues can be functional in cases like ports
 804          * are started without re configuring queues.
 805          *
 806          * Usual re config sequence is like below:
 807          * port_configure() {
 808          *      if(reconfigure) {
 809          *              queue_release()
 810          *              queue_setup()
 811          *      }
 812          *      queue_configure() {
 813          *              queue_release()
 814          *              queue_setup()
 815          *      }
 816          * }
 817          * port_start()
 818          *
 819          * In some application's control path, queue_configure() would
 820          * NOT be invoked for TXQs/RXQs in port_configure().
 821          * In such cases, queues can be functional after start as the
 822          * queues are already setup in port_configure().
 823          */
 824         for (i = 0; i < nb_txq; i++) {
 825                 if (!tx_qconf[i].valid)
 826                         continue;
 827                 rc = dev_ops->tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc, 0,
 828                                              &tx_qconf[i].conf.tx);
 829                 if (rc) {
 830                         plt_err("Failed to setup tx queue rc=%d", rc);
 831                         for (i -= 1; i >= 0; i--)
 832                                 dev_ops->tx_queue_release(eth_dev, i);
 833                         goto fail;
 834                 }
 835         }
 836
 837         free(tx_qconf);
 838         tx_qconf = NULL;
 839
 840         for (i = 0; i < nb_rxq; i++) {
 841                 if (!rx_qconf[i].valid)
 842                         continue;
 843                 rc = dev_ops->rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc, 0,
 844                                              &rx_qconf[i].conf.rx,
 845                                              rx_qconf[i].mp);
 846                 if (rc) {
 847                         plt_err("Failed to setup rx queue rc=%d", rc);
 848                         for (i -= 1; i >= 0; i--)
 849                                 dev_ops->rx_queue_release(eth_dev, i);
 850                         goto tx_queue_release;
 851                 }
 852         }
 853
 854         free(rx_qconf);
 855         rx_qconf = NULL;
 856
 857         return 0;
 858
 859 tx_queue_release:
 860         for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
 861                 dev_ops->tx_queue_release(eth_dev, i);
 862 fail:
 863         if (tx_qconf)
 864                 free(tx_qconf);
 865         if (rx_qconf)
 866                 free(rx_qconf);
 867
 868         return rc;
 869 }
 870
 871 static uint16_t
 872 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
 873 {
 874         RTE_SET_USED(queue);
 875         RTE_SET_USED(mbufs);
 876         RTE_SET_USED(pkts);
 877
 878         return 0;
 879 }
 880
 881 static void
 882 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
 883 {
 884         /* These dummy functions are required for supporting
 885          * some applications which reconfigure queues without
 886          * stopping tx burst and rx burst threads(eg kni app)
 887          * When the queues context is saved, txq/rxqs are released
 888          * which caused app crash since rx/tx burst is still
 889          * on different lcores
 890          */
 891         eth_dev->tx_pkt_burst = nix_eth_nop_burst;
 892         eth_dev->rx_pkt_burst = nix_eth_nop_burst;
 893         rte_mb();
 894 }
 895
 896 static int
 897 nix_lso_tun_fmt_update(struct cnxk_eth_dev *dev)
 898 {
 899         uint8_t udp_tun[ROC_NIX_LSO_TUN_MAX];
 900         uint8_t tun[ROC_NIX_LSO_TUN_MAX];
 901         struct roc_nix *nix = &dev->nix;
 902         int rc;
 903
 904         rc = roc_nix_lso_fmt_get(nix, udp_tun, tun);
 905         if (rc)
 906                 return rc;
 907
 908         dev->lso_tun_fmt = ((uint64_t)tun[ROC_NIX_LSO_TUN_V4V4] |
 909                             (uint64_t)tun[ROC_NIX_LSO_TUN_V4V6] << 8 |
 910                             (uint64_t)tun[ROC_NIX_LSO_TUN_V6V4] << 16 |
 911                             (uint64_t)tun[ROC_NIX_LSO_TUN_V6V6] << 24);
 912
 913         dev->lso_tun_fmt |= ((uint64_t)udp_tun[ROC_NIX_LSO_TUN_V4V4] << 32 |
 914                              (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V4V6] << 40 |
 915                              (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V6V4] << 48 |
 916                              (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V6V6] << 56);
 917         return 0;
 918 }
 919
 920 static int
 921 nix_lso_fmt_setup(struct cnxk_eth_dev *dev)
 922 {
 923         struct roc_nix *nix = &dev->nix;
 924         int rc;
 925
 926         /* Nothing much to do if offload is not enabled */
 927         if (!(dev->tx_offloads &
 928               (DEV_TX_OFFLOAD_TCP_TSO | DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 929                DEV_TX_OFFLOAD_GENEVE_TNL_TSO | DEV_TX_OFFLOAD_GRE_TNL_TSO)))
 930                 return 0;
 931
 932         /* Setup LSO formats in AF. Its a no-op if other ethdev has
 933          * already set it up
 934          */
 935         rc = roc_nix_lso_fmt_setup(nix);
 936         if (rc)
 937                 return rc;
 938
 939         return nix_lso_tun_fmt_update(dev);
 940 }
 941
 942 int
 943 cnxk_nix_configure(struct rte_eth_dev *eth_dev)
 944 {
 945         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 946         struct rte_eth_dev_data *data = eth_dev->data;
 947         struct rte_eth_conf *conf = &data->dev_conf;
 948         struct rte_eth_rxmode *rxmode = &conf->rxmode;
 949         struct rte_eth_txmode *txmode = &conf->txmode;
 950         char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
 951         struct roc_nix_fc_cfg fc_cfg = {0};
 952         struct roc_nix *nix = &dev->nix;
 953         struct rte_ether_addr *ea;
 954         uint8_t nb_rxq, nb_txq;
 955         uint64_t rx_cfg;
 956         void *qs;
 957         int rc;
 958
 959         rc = -EINVAL;
 960
 961         /* Sanity checks */
 962         if (rte_eal_has_hugepages() == 0) {
 963                 plt_err("Huge page is not configured");
 964                 goto fail_configure;
 965         }
 966
 967         if (conf->dcb_capability_en == 1) {
 968                 plt_err("dcb enable is not supported");
 969                 goto fail_configure;
 970         }
 971
 972         if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
 973                 plt_err("Flow director is not supported");
 974                 goto fail_configure;
 975         }
 976
 977         if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
 978             rxmode->mq_mode != ETH_MQ_RX_RSS) {
 979                 plt_err("Unsupported mq rx mode %d", rxmode->mq_mode);
 980                 goto fail_configure;
 981         }
 982
 983         if (txmode->mq_mode != ETH_MQ_TX_NONE) {
 984                 plt_err("Unsupported mq tx mode %d", txmode->mq_mode);
 985                 goto fail_configure;
 986         }
 987
 988         /* Free the resources allocated from the previous configure */
 989         if (dev->configured == 1) {
 990                 /* Unregister queue irq's */
 991                 roc_nix_unregister_queue_irqs(nix);
 992
 993                 /* Unregister CQ irqs if present */
 994                 if (eth_dev->data->dev_conf.intr_conf.rxq)
 995                         roc_nix_unregister_cq_irqs(nix);
 996
 997                 /* Set no-op functions */
 998                 nix_set_nop_rxtx_function(eth_dev);
 999                 /* Store queue config for later */
1000                 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1001                 if (rc)
1002                         goto fail_configure;
1003
1004                 /* Cleanup security support */
1005                 rc = nix_security_release(dev);
1006                 if (rc)
1007                         goto fail_configure;
1008
1009                 roc_nix_tm_fini(nix);
1010                 roc_nix_lf_free(nix);
1011         }
1012
1013         dev->rx_offloads = rxmode->offloads;
1014         dev->tx_offloads = txmode->offloads;
1015
1016         /* Prepare rx cfg */
1017         rx_cfg = ROC_NIX_LF_RX_CFG_DIS_APAD;
1018         if (dev->rx_offloads &
1019             (DEV_RX_OFFLOAD_TCP_CKSUM | DEV_RX_OFFLOAD_UDP_CKSUM)) {
1020                 rx_cfg |= ROC_NIX_LF_RX_CFG_CSUM_OL4;
1021                 rx_cfg |= ROC_NIX_LF_RX_CFG_CSUM_IL4;
1022         }
1023         rx_cfg |= (ROC_NIX_LF_RX_CFG_DROP_RE | ROC_NIX_LF_RX_CFG_L2_LEN_ERR |
1024                    ROC_NIX_LF_RX_CFG_LEN_IL4 | ROC_NIX_LF_RX_CFG_LEN_IL3 |
1025                    ROC_NIX_LF_RX_CFG_LEN_OL4 | ROC_NIX_LF_RX_CFG_LEN_OL3);
1026
1027         if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
1028                 rx_cfg |= ROC_NIX_LF_RX_CFG_IP6_UDP_OPT;
1029                 /* Disable drop re if rx offload security is enabled and
1030                  * platform does not support it.
1031                  */
1032                 if (dev->ipsecd_drop_re_dis)
1033                         rx_cfg &= ~(ROC_NIX_LF_RX_CFG_DROP_RE);
1034         }
1035
1036         nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1037         nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1038
1039         /* Alloc a nix lf */
1040         rc = roc_nix_lf_alloc(nix, nb_rxq, nb_txq, rx_cfg);
1041         if (rc) {
1042                 plt_err("Failed to init nix_lf rc=%d", rc);
1043                 goto fail_configure;
1044         }
1045
1046         dev->npc.channel = roc_nix_get_base_chan(nix);
1047
1048         nb_rxq = data->nb_rx_queues;
1049         nb_txq = data->nb_tx_queues;
1050         rc = -ENOMEM;
1051         if (nb_rxq) {
1052                 /* Allocate memory for roc rq's and cq's */
1053                 qs = plt_zmalloc(sizeof(struct roc_nix_rq) * nb_rxq, 0);
1054                 if (!qs) {
1055                         plt_err("Failed to alloc rqs");
1056                         goto free_nix_lf;
1057                 }
1058                 dev->rqs = qs;
1059
1060                 qs = plt_zmalloc(sizeof(struct roc_nix_cq) * nb_rxq, 0);
1061                 if (!qs) {
1062                         plt_err("Failed to alloc cqs");
1063                         goto free_nix_lf;
1064                 }
1065                 dev->cqs = qs;
1066         }
1067
1068         if (nb_txq) {
1069                 /* Allocate memory for roc sq's */
1070                 qs = plt_zmalloc(sizeof(struct roc_nix_sq) * nb_txq, 0);
1071                 if (!qs) {
1072                         plt_err("Failed to alloc sqs");
1073                         goto free_nix_lf;
1074                 }
1075                 dev->sqs = qs;
1076         }
1077
1078         /* Re-enable NIX LF error interrupts */
1079         roc_nix_err_intr_ena_dis(nix, true);
1080         roc_nix_ras_intr_ena_dis(nix, true);
1081
1082         if (nix->rx_ptp_ena &&
1083             dev->npc.switch_header_type == ROC_PRIV_FLAGS_HIGIG) {
1084                 plt_err("Both PTP and switch header enabled");
1085                 goto free_nix_lf;
1086         }
1087
1088         rc = roc_nix_switch_hdr_set(nix, dev->npc.switch_header_type);
1089         if (rc) {
1090                 plt_err("Failed to enable switch type nix_lf rc=%d", rc);
1091                 goto free_nix_lf;
1092         }
1093
1094         /* Setup LSO if needed */
1095         rc = nix_lso_fmt_setup(dev);
1096         if (rc) {
1097                 plt_err("Failed to setup nix lso format fields, rc=%d", rc);
1098                 goto free_nix_lf;
1099         }
1100
1101         /* Configure RSS */
1102         rc = nix_rss_default_setup(dev);
1103         if (rc) {
1104                 plt_err("Failed to configure rss rc=%d", rc);
1105                 goto free_nix_lf;
1106         }
1107
1108         /* Init the default TM scheduler hierarchy */
1109         rc = roc_nix_tm_init(nix);
1110         if (rc) {
1111                 plt_err("Failed to init traffic manager, rc=%d", rc);
1112                 goto free_nix_lf;
1113         }
1114
1115         rc = nix_ingress_policer_setup(dev);
1116         if (rc) {
1117                 plt_err("Failed to setup ingress policer rc=%d", rc);
1118                 goto free_nix_lf;
1119         }
1120
1121         rc = roc_nix_tm_hierarchy_enable(nix, ROC_NIX_TM_DEFAULT, false);
1122         if (rc) {
1123                 plt_err("Failed to enable default tm hierarchy, rc=%d", rc);
1124                 goto tm_fini;
1125         }
1126
1127         /* Register queue IRQs */
1128         rc = roc_nix_register_queue_irqs(nix);
1129         if (rc) {
1130                 plt_err("Failed to register queue interrupts rc=%d", rc);
1131                 goto tm_fini;
1132         }
1133
1134         /* Register cq IRQs */
1135         if (eth_dev->data->dev_conf.intr_conf.rxq) {
1136                 if (eth_dev->data->nb_rx_queues > dev->nix.cints) {
1137                         plt_err("Rx interrupt cannot be enabled, rxq > %d",
1138                                 dev->nix.cints);
1139                         goto q_irq_fini;
1140                 }
1141                 /* Rx interrupt feature cannot work with vector mode because,
1142                  * vector mode does not process packets unless min 4 pkts are
1143                  * received, while cq interrupts are generated even for 1 pkt
1144                  * in the CQ.
1145                  */
1146                 dev->scalar_ena = true;
1147
1148                 rc = roc_nix_register_cq_irqs(nix);
1149                 if (rc) {
1150                         plt_err("Failed to register CQ interrupts rc=%d", rc);
1151                         goto q_irq_fini;
1152                 }
1153         }
1154
1155         /* Configure loop back mode */
1156         rc = roc_nix_mac_loopback_enable(nix,
1157                                          eth_dev->data->dev_conf.lpbk_mode);
1158         if (rc) {
1159                 plt_err("Failed to configure cgx loop back mode rc=%d", rc);
1160                 goto cq_fini;
1161         }
1162
1163         /* Init flow control configuration */
1164         fc_cfg.cq_cfg_valid = false;
1165         fc_cfg.rxchan_cfg.enable = true;
1166         rc = roc_nix_fc_config_set(nix, &fc_cfg);
1167         if (rc) {
1168                 plt_err("Failed to initialize flow control rc=%d", rc);
1169                 goto cq_fini;
1170         }
1171
1172         /* Update flow control configuration to PMD */
1173         rc = nix_init_flow_ctrl_config(eth_dev);
1174         if (rc) {
1175                 plt_err("Failed to initialize flow control rc=%d", rc);
1176                 goto cq_fini;
1177         }
1178
1179         /* Setup Inline security support */
1180         rc = nix_security_setup(dev);
1181         if (rc)
1182                 goto cq_fini;
1183
1184         /*
1185          * Restore queue config when reconfigure followed by
1186          * reconfigure and no queue configure invoked from application case.
1187          */
1188         if (dev->configured == 1) {
1189                 rc = nix_restore_queue_cfg(eth_dev);
1190                 if (rc)
1191                         goto sec_release;
1192         }
1193
1194         /* Update the mac address */
1195         ea = eth_dev->data->mac_addrs;
1196         memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1197         if (rte_is_zero_ether_addr(ea))
1198                 rte_eth_random_addr((uint8_t *)ea);
1199
1200         rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
1201
1202         plt_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
1203                     " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 "",
1204                     eth_dev->data->port_id, ea_fmt, nb_rxq, nb_txq,
1205                     dev->rx_offloads, dev->tx_offloads);
1206
1207         /* All good */
1208         dev->configured = 1;
1209         dev->nb_rxq = data->nb_rx_queues;
1210         dev->nb_txq = data->nb_tx_queues;
1211         return 0;
1212
1213 sec_release:
1214         rc |= nix_security_release(dev);
1215 cq_fini:
1216         roc_nix_unregister_cq_irqs(nix);
1217 q_irq_fini:
1218         roc_nix_unregister_queue_irqs(nix);
1219 tm_fini:
1220         roc_nix_tm_fini(nix);
1221 free_nix_lf:
1222         nix_free_queue_mem(dev);
1223         rc |= roc_nix_lf_free(nix);
1224 fail_configure:
1225         dev->configured = 0;
1226         return rc;
1227 }
1228
1229 int
1230 cnxk_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid)
1231 {
1232         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1233         struct rte_eth_dev_data *data = eth_dev->data;
1234         struct roc_nix_sq *sq = &dev->sqs[qid];
1235         int rc = -EINVAL;
1236
1237         if (data->tx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STARTED)
1238                 return 0;
1239
1240         rc = roc_nix_tm_sq_aura_fc(sq, true);
1241         if (rc) {
1242                 plt_err("Failed to enable sq aura fc, txq=%u, rc=%d", qid, rc);
1243                 goto done;
1244         }
1245
1246         data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STARTED;
1247 done:
1248         return rc;
1249 }
1250
1251 int
1252 cnxk_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid)
1253 {
1254         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1255         struct rte_eth_dev_data *data = eth_dev->data;
1256         struct roc_nix_sq *sq = &dev->sqs[qid];
1257         int rc;
1258
1259         if (data->tx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STOPPED)
1260                 return 0;
1261
1262         rc = roc_nix_tm_sq_aura_fc(sq, false);
1263         if (rc) {
1264                 plt_err("Failed to disable sqb aura fc, txq=%u, rc=%d", qid,
1265                         rc);
1266                 goto done;
1267         }
1268
1269         data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
1270 done:
1271         return rc;
1272 }
1273
1274 static int
1275 cnxk_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid)
1276 {
1277         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1278         struct rte_eth_dev_data *data = eth_dev->data;
1279         struct roc_nix_rq *rq = &dev->rqs[qid];
1280         int rc;
1281
1282         if (data->rx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STARTED)
1283                 return 0;
1284
1285         rc = roc_nix_rq_ena_dis(rq, true);
1286         if (rc) {
1287                 plt_err("Failed to enable rxq=%u, rc=%d", qid, rc);
1288                 goto done;
1289         }
1290
1291         data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STARTED;
1292 done:
1293         return rc;
1294 }
1295
1296 static int
1297 cnxk_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid)
1298 {
1299         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1300         struct rte_eth_dev_data *data = eth_dev->data;
1301         struct roc_nix_rq *rq = &dev->rqs[qid];
1302         int rc;
1303
1304         if (data->rx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STOPPED)
1305                 return 0;
1306
1307         rc = roc_nix_rq_ena_dis(rq, false);
1308         if (rc) {
1309                 plt_err("Failed to disable rxq=%u, rc=%d", qid, rc);
1310                 goto done;
1311         }
1312
1313         data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
1314 done:
1315         return rc;
1316 }
1317
1318 static int
1319 cnxk_nix_dev_stop(struct rte_eth_dev *eth_dev)
1320 {
1321         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1322         const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
1323         struct rte_mbuf *rx_pkts[32];
1324         struct rte_eth_link link;
1325         int count, i, j, rc;
1326         void *rxq;
1327
1328         /* Disable switch hdr pkind */
1329         roc_nix_switch_hdr_set(&dev->nix, 0);
1330
1331         /* Stop link change events */
1332         if (!roc_nix_is_vf_or_sdp(&dev->nix))
1333                 roc_nix_mac_link_event_start_stop(&dev->nix, false);
1334
1335         /* Disable Rx via NPC */
1336         roc_nix_npc_rx_ena_dis(&dev->nix, false);
1337
1338         /* Stop rx queues and free up pkts pending */
1339         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1340                 rc = dev_ops->rx_queue_stop(eth_dev, i);
1341                 if (rc)
1342                         continue;
1343
1344                 rxq = eth_dev->data->rx_queues[i];
1345                 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1346                 while (count) {
1347                         for (j = 0; j < count; j++)
1348                                 rte_pktmbuf_free(rx_pkts[j]);
1349                         count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1350                 }
1351         }
1352
1353         /* Stop tx queues  */
1354         for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1355                 dev_ops->tx_queue_stop(eth_dev, i);
1356
1357         /* Bring down link status internally */
1358         memset(&link, 0, sizeof(link));
1359         rte_eth_linkstatus_set(eth_dev, &link);
1360
1361         return 0;
1362 }
1363
1364 int
1365 cnxk_nix_dev_start(struct rte_eth_dev *eth_dev)
1366 {
1367         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1368         int rc, i;
1369
1370         if (eth_dev->data->nb_rx_queues != 0 && !dev->ptp_en) {
1371                 rc = nix_recalc_mtu(eth_dev);
1372                 if (rc)
1373                         return rc;
1374         }
1375
1376         /* Start rx queues */
1377         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1378                 rc = cnxk_nix_rx_queue_start(eth_dev, i);
1379                 if (rc)
1380                         return rc;
1381         }
1382
1383         /* Start tx queues  */
1384         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1385                 rc = cnxk_nix_tx_queue_start(eth_dev, i);
1386                 if (rc)
1387                         return rc;
1388         }
1389
1390         /* Update Flow control configuration */
1391         rc = nix_update_flow_ctrl_config(eth_dev);
1392         if (rc) {
1393                 plt_err("Failed to enable flow control. error code(%d)", rc);
1394                 return rc;
1395         }
1396
1397         /* Enable Rx in NPC */
1398         rc = roc_nix_npc_rx_ena_dis(&dev->nix, true);
1399         if (rc) {
1400                 plt_err("Failed to enable NPC rx %d", rc);
1401                 return rc;
1402         }
1403
1404         cnxk_nix_toggle_flag_link_cfg(dev, true);
1405
1406         /* Start link change events */
1407         if (!roc_nix_is_vf_or_sdp(&dev->nix)) {
1408                 rc = roc_nix_mac_link_event_start_stop(&dev->nix, true);
1409                 if (rc) {
1410                         plt_err("Failed to start cgx link event %d", rc);
1411                         goto rx_disable;
1412                 }
1413         }
1414
1415         /* Enable PTP if it is requested by the user or already
1416          * enabled on PF owning this VF
1417          */
1418         memset(&dev->tstamp, 0, sizeof(struct cnxk_timesync_info));
1419         if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) || dev->ptp_en)
1420                 cnxk_eth_dev_ops.timesync_enable(eth_dev);
1421         else
1422                 cnxk_eth_dev_ops.timesync_disable(eth_dev);
1423
1424         if (dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) {
1425                 rc = rte_mbuf_dyn_rx_timestamp_register
1426                         (&dev->tstamp.tstamp_dynfield_offset,
1427                          &dev->tstamp.rx_tstamp_dynflag);
1428                 if (rc != 0) {
1429                         plt_err("Failed to register Rx timestamp field/flag");
1430                         goto rx_disable;
1431                 }
1432         }
1433
1434         cnxk_nix_toggle_flag_link_cfg(dev, false);
1435
1436         return 0;
1437
1438 rx_disable:
1439         roc_nix_npc_rx_ena_dis(&dev->nix, false);
1440         cnxk_nix_toggle_flag_link_cfg(dev, false);
1441         return rc;
1442 }
1443
1444 static int cnxk_nix_dev_reset(struct rte_eth_dev *eth_dev);
1445 static int cnxk_nix_dev_close(struct rte_eth_dev *eth_dev);
1446
1447 /* CNXK platform independent eth dev ops */
1448 struct eth_dev_ops cnxk_eth_dev_ops = {
1449         .mtu_set = cnxk_nix_mtu_set,
1450         .mac_addr_add = cnxk_nix_mac_addr_add,
1451         .mac_addr_remove = cnxk_nix_mac_addr_del,
1452         .mac_addr_set = cnxk_nix_mac_addr_set,
1453         .dev_infos_get = cnxk_nix_info_get,
1454         .link_update = cnxk_nix_link_update,
1455         .tx_queue_release = cnxk_nix_tx_queue_release,
1456         .rx_queue_release = cnxk_nix_rx_queue_release,
1457         .dev_stop = cnxk_nix_dev_stop,
1458         .dev_close = cnxk_nix_dev_close,
1459         .dev_reset = cnxk_nix_dev_reset,
1460         .tx_queue_start = cnxk_nix_tx_queue_start,
1461         .rx_queue_start = cnxk_nix_rx_queue_start,
1462         .rx_queue_stop = cnxk_nix_rx_queue_stop,
1463         .dev_supported_ptypes_get = cnxk_nix_supported_ptypes_get,
1464         .promiscuous_enable = cnxk_nix_promisc_enable,
1465         .promiscuous_disable = cnxk_nix_promisc_disable,
1466         .allmulticast_enable = cnxk_nix_allmulticast_enable,
1467         .allmulticast_disable = cnxk_nix_allmulticast_disable,
1468         .rx_burst_mode_get = cnxk_nix_rx_burst_mode_get,
1469         .tx_burst_mode_get = cnxk_nix_tx_burst_mode_get,
1470         .flow_ctrl_get = cnxk_nix_flow_ctrl_get,
1471         .flow_ctrl_set = cnxk_nix_flow_ctrl_set,
1472         .dev_set_link_up = cnxk_nix_set_link_up,
1473         .dev_set_link_down = cnxk_nix_set_link_down,
1474         .get_module_info = cnxk_nix_get_module_info,
1475         .get_module_eeprom = cnxk_nix_get_module_eeprom,
1476         .rx_queue_intr_enable = cnxk_nix_rx_queue_intr_enable,
1477         .rx_queue_intr_disable = cnxk_nix_rx_queue_intr_disable,
1478         .pool_ops_supported = cnxk_nix_pool_ops_supported,
1479         .queue_stats_mapping_set = cnxk_nix_queue_stats_mapping,
1480         .stats_get = cnxk_nix_stats_get,
1481         .stats_reset = cnxk_nix_stats_reset,
1482         .xstats_get = cnxk_nix_xstats_get,
1483         .xstats_get_names = cnxk_nix_xstats_get_names,
1484         .xstats_reset = cnxk_nix_xstats_reset,
1485         .xstats_get_by_id = cnxk_nix_xstats_get_by_id,
1486         .xstats_get_names_by_id = cnxk_nix_xstats_get_names_by_id,
1487         .fw_version_get = cnxk_nix_fw_version_get,
1488         .rxq_info_get = cnxk_nix_rxq_info_get,
1489         .txq_info_get = cnxk_nix_txq_info_get,
1490         .tx_done_cleanup = cnxk_nix_tx_done_cleanup,
1491         .flow_ops_get = cnxk_nix_flow_ops_get,
1492         .get_reg = cnxk_nix_dev_get_reg,
1493         .timesync_read_rx_timestamp = cnxk_nix_timesync_read_rx_timestamp,
1494         .timesync_read_tx_timestamp = cnxk_nix_timesync_read_tx_timestamp,
1495         .timesync_read_time = cnxk_nix_timesync_read_time,
1496         .timesync_write_time = cnxk_nix_timesync_write_time,
1497         .timesync_adjust_time = cnxk_nix_timesync_adjust_time,
1498         .read_clock = cnxk_nix_read_clock,
1499         .reta_update = cnxk_nix_reta_update,
1500         .reta_query = cnxk_nix_reta_query,
1501         .rss_hash_update = cnxk_nix_rss_hash_update,
1502         .rss_hash_conf_get = cnxk_nix_rss_hash_conf_get,
1503         .set_mc_addr_list = cnxk_nix_mc_addr_list_configure,
1504         .set_queue_rate_limit = cnxk_nix_tm_set_queue_rate_limit,
1505         .tm_ops_get = cnxk_nix_tm_ops_get,
1506         .mtr_ops_get = cnxk_nix_mtr_ops_get,
1507 };
1508
1509 static int
1510 cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)
1511 {
1512         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1513         struct rte_security_ctx *sec_ctx;
1514         struct roc_nix *nix = &dev->nix;
1515         struct rte_pci_device *pci_dev;
1516         int rc, max_entries;
1517
1518         eth_dev->dev_ops = &cnxk_eth_dev_ops;
1519
1520         /* Alloc security context */
1521         sec_ctx = plt_zmalloc(sizeof(struct rte_security_ctx), 0);
1522         if (!sec_ctx)
1523                 return -ENOMEM;
1524         sec_ctx->device = eth_dev;
1525         sec_ctx->ops = &cnxk_eth_sec_ops;
1526         sec_ctx->flags =
1527                 (RTE_SEC_CTX_F_FAST_SET_MDATA | RTE_SEC_CTX_F_FAST_GET_UDATA);
1528         eth_dev->security_ctx = sec_ctx;
1529         TAILQ_INIT(&dev->inb.list);
1530         TAILQ_INIT(&dev->outb.list);
1531
1532         /* For secondary processes, the primary has done all the work */
1533         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1534                 return 0;
1535
1536         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1537         rte_eth_copy_pci_info(eth_dev, pci_dev);
1538
1539         /* Parse devargs string */
1540         rc = cnxk_ethdev_parse_devargs(eth_dev->device->devargs, dev);
1541         if (rc) {
1542                 plt_err("Failed to parse devargs rc=%d", rc);
1543                 goto error;
1544         }
1545
1546         /* Initialize base roc nix */
1547         nix->pci_dev = pci_dev;
1548         nix->hw_vlan_ins = true;
1549         rc = roc_nix_dev_init(nix);
1550         if (rc) {
1551                 plt_err("Failed to initialize roc nix rc=%d", rc);
1552                 goto error;
1553         }
1554
1555         /* Register up msg callbacks */
1556         roc_nix_mac_link_cb_register(nix, cnxk_eth_dev_link_status_cb);
1557
1558         /* Register up msg callbacks */
1559         roc_nix_mac_link_info_get_cb_register(nix,
1560                                               cnxk_eth_dev_link_status_get_cb);
1561
1562         dev->eth_dev = eth_dev;
1563         dev->configured = 0;
1564         dev->ptype_disable = 0;
1565
1566         /* For vfs, returned max_entries will be 0. but to keep default mac
1567          * address, one entry must be allocated. so setting up to 1.
1568          */
1569         if (roc_nix_is_vf_or_sdp(nix))
1570                 max_entries = 1;
1571         else
1572                 max_entries = roc_nix_mac_max_entries_get(nix);
1573
1574         if (max_entries <= 0) {
1575                 plt_err("Failed to get max entries for mac addr");
1576                 rc = -ENOTSUP;
1577                 goto dev_fini;
1578         }
1579
1580         eth_dev->data->mac_addrs =
1581                 rte_zmalloc("mac_addr", max_entries * RTE_ETHER_ADDR_LEN, 0);
1582         if (eth_dev->data->mac_addrs == NULL) {
1583                 plt_err("Failed to allocate memory for mac addr");
1584                 rc = -ENOMEM;
1585                 goto dev_fini;
1586         }
1587
1588         dev->max_mac_entries = max_entries;
1589         dev->dmac_filter_count = 1;
1590
1591         /* Get mac address */
1592         rc = roc_nix_npc_mac_addr_get(nix, dev->mac_addr);
1593         if (rc) {
1594                 plt_err("Failed to get mac addr, rc=%d", rc);
1595                 goto free_mac_addrs;
1596         }
1597
1598         /* Update the mac address */
1599         memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1600
1601         if (!roc_nix_is_vf_or_sdp(nix)) {
1602                 /* Sync same MAC address to CGX/RPM table */
1603                 rc = roc_nix_mac_addr_set(nix, dev->mac_addr);
1604                 if (rc) {
1605                         plt_err("Failed to set mac addr, rc=%d", rc);
1606                         goto free_mac_addrs;
1607                 }
1608         }
1609
1610         /* Union of all capabilities supported by CNXK.
1611          * Platform specific capabilities will be
1612          * updated later.
1613          */
1614         dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
1615         dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
1616         dev->speed_capa = nix_get_speed_capa(dev);
1617
1618         /* Initialize roc npc */
1619         dev->npc.roc_nix = nix;
1620         rc = roc_npc_init(&dev->npc);
1621         if (rc)
1622                 goto free_mac_addrs;
1623
1624         plt_nix_dbg("Port=%d pf=%d vf=%d ver=%s hwcap=0x%" PRIx64
1625                     " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
1626                     eth_dev->data->port_id, roc_nix_get_pf(nix),
1627                     roc_nix_get_vf(nix), CNXK_ETH_DEV_PMD_VERSION, dev->hwcap,
1628                     dev->rx_offload_capa, dev->tx_offload_capa);
1629         return 0;
1630
1631 free_mac_addrs:
1632         rte_free(eth_dev->data->mac_addrs);
1633 dev_fini:
1634         roc_nix_dev_fini(nix);
1635 error:
1636         plt_err("Failed to init nix eth_dev rc=%d", rc);
1637         return rc;
1638 }
1639
1640 static int
1641 cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool reset)
1642 {
1643         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
1644         const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
1645         struct roc_nix *nix = &dev->nix;
1646         int rc, i;
1647
1648         plt_free(eth_dev->security_ctx);
1649         eth_dev->security_ctx = NULL;
1650
1651         /* Nothing to be done for secondary processes */
1652         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1653                 return 0;
1654
1655         /* Clear the flag since we are closing down */
1656         dev->configured = 0;
1657
1658         roc_nix_npc_rx_ena_dis(nix, false);
1659
1660         /* Disable and free rte_flow entries */
1661         roc_npc_fini(&dev->npc);
1662
1663         /* Disable link status events */
1664         roc_nix_mac_link_event_start_stop(nix, false);
1665
1666         /* Unregister the link update op, this is required to stop VFs from
1667          * receiving link status updates on exit path.
1668          */
1669         roc_nix_mac_link_cb_unregister(nix);
1670
1671         /* Free up SQs */
1672         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1673                 dev_ops->tx_queue_release(eth_dev, i);
1674                 eth_dev->data->tx_queues[i] = NULL;
1675         }
1676         eth_dev->data->nb_tx_queues = 0;
1677
1678         /* Free up RQ's and CQ's */
1679         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1680                 dev_ops->rx_queue_release(eth_dev, i);
1681                 eth_dev->data->rx_queues[i] = NULL;
1682         }
1683         eth_dev->data->nb_rx_queues = 0;
1684
1685         /* Free security resources */
1686         nix_security_release(dev);
1687
1688         /* Free tm resources */
1689         roc_nix_tm_fini(nix);
1690
1691         /* Unregister queue irqs */
1692         roc_nix_unregister_queue_irqs(nix);
1693
1694         /* Unregister cq irqs */
1695         if (eth_dev->data->dev_conf.intr_conf.rxq)
1696                 roc_nix_unregister_cq_irqs(nix);
1697
1698         /* Free ROC RQ's, SQ's and CQ's memory */
1699         nix_free_queue_mem(dev);
1700
1701         /* Free nix lf resources */
1702         rc = roc_nix_lf_free(nix);
1703         if (rc)
1704                 plt_err("Failed to free nix lf, rc=%d", rc);
1705
1706         rte_free(eth_dev->data->mac_addrs);
1707         eth_dev->data->mac_addrs = NULL;
1708
1709         rc = roc_nix_dev_fini(nix);
1710         /* Can be freed later by PMD if NPA LF is in use */
1711         if (rc == -EAGAIN) {
1712                 if (!reset)
1713                         eth_dev->data->dev_private = NULL;
1714                 return 0;
1715         } else if (rc) {
1716                 plt_err("Failed in nix dev fini, rc=%d", rc);
1717         }
1718
1719         return rc;
1720 }
1721
1722 static int
1723 cnxk_nix_dev_close(struct rte_eth_dev *eth_dev)
1724 {
1725         cnxk_eth_dev_uninit(eth_dev, false);
1726         return 0;
1727 }
1728
1729 static int
1730 cnxk_nix_dev_reset(struct rte_eth_dev *eth_dev)
1731 {
1732         int rc;
1733
1734         rc = cnxk_eth_dev_uninit(eth_dev, true);
1735         if (rc)
1736                 return rc;
1737
1738         return cnxk_eth_dev_init(eth_dev);
1739 }
1740
1741 int
1742 cnxk_nix_remove(struct rte_pci_device *pci_dev)
1743 {
1744         struct rte_eth_dev *eth_dev;
1745         struct roc_nix *nix;
1746         int rc = -EINVAL;
1747
1748         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
1749         if (eth_dev) {
1750                 /* Cleanup eth dev */
1751                 rc = cnxk_eth_dev_uninit(eth_dev, false);
1752                 if (rc)
1753                         return rc;
1754
1755                 rte_eth_dev_release_port(eth_dev);
1756         }
1757
1758         /* Nothing to be done for secondary processes */
1759         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1760                 return 0;
1761
1762         /* Check if this device is hosting common resource */
1763         nix = roc_idev_npa_nix_get();
1764         if (nix->pci_dev != pci_dev)
1765                 return 0;
1766
1767         /* Try nix fini now */
1768         rc = roc_nix_dev_fini(nix);
1769         if (rc == -EAGAIN) {
1770                 plt_info("%s: common resource in use by other devices",
1771                          pci_dev->name);
1772                 goto exit;
1773         } else if (rc) {
1774                 plt_err("Failed in nix dev fini, rc=%d", rc);
1775                 goto exit;
1776         }
1777
1778         /* Free device pointer as rte_ethdev does not have it anymore */
1779         rte_free(nix);
1780 exit:
1781         return rc;
1782 }
1783
1784 int
1785 cnxk_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1786 {
1787         int rc;
1788
1789         RTE_SET_USED(pci_drv);
1790
1791         rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct cnxk_eth_dev),
1792                                            cnxk_eth_dev_init);
1793
1794         /* On error on secondary, recheck if port exists in primary or
1795          * in mid of detach state.
1796          */
1797         if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
1798                 if (!rte_eth_dev_allocated(pci_dev->device.name))
1799                         return 0;
1800         return rc;
1801 }