1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
4 #ifndef __CNXK_ETHDEV_H__
5 #define __CNXK_ETHDEV_H__
10 #include <ethdev_driver.h>
11 #include <ethdev_pci.h>
12 #include <rte_kvargs.h>
14 #include <rte_mbuf_pool_ops.h>
15 #include <rte_mempool.h>
20 #define CNXK_ETH_DEV_PMD_VERSION "1.0"
22 /* Used for struct cnxk_eth_dev::flags */
23 #define CNXK_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
25 /* VLAN tag inserted by NIX_TX_VTAG_ACTION.
26 * In Tx space is always reserved for this in FRS.
28 #define CNXK_NIX_MAX_VTAG_INS 2
29 #define CNXK_NIX_MAX_VTAG_ACT_SIZE (4 * CNXK_NIX_MAX_VTAG_INS)
31 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
32 #define CNXK_NIX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + \
34 CNXK_NIX_MAX_VTAG_ACT_SIZE)
36 #define CNXK_NIX_RX_MIN_DESC 16
37 #define CNXK_NIX_RX_MIN_DESC_ALIGN 16
38 #define CNXK_NIX_RX_NB_SEG_MAX 6
39 #define CNXK_NIX_RX_DEFAULT_RING_SZ 4096
40 /* Max supported SQB count */
41 #define CNXK_NIX_TX_MAX_SQB 512
43 /* If PTP is enabled additional SEND MEM DESC is required which
44 * takes 2 words, hence max 7 iova address are possible
46 #if defined(RTE_LIBRTE_IEEE1588)
47 #define CNXK_NIX_TX_NB_SEG_MAX 7
49 #define CNXK_NIX_TX_NB_SEG_MAX 9
52 #define CNXK_NIX_TX_MSEG_SG_DWORDS \
53 ((RTE_ALIGN_MUL_CEIL(CNXK_NIX_TX_NB_SEG_MAX, 3) / 3) + \
54 CNXK_NIX_TX_NB_SEG_MAX)
56 #define CNXK_NIX_RSS_L3_L4_SRC_DST \
57 (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | ETH_RSS_L4_SRC_ONLY | \
60 #define CNXK_NIX_RSS_OFFLOAD \
61 (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP | \
62 ETH_RSS_SCTP | ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD | \
63 CNXK_NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | ETH_RSS_C_VLAN)
65 #define CNXK_NIX_TX_OFFLOAD_CAPA \
66 (DEV_TX_OFFLOAD_MBUF_FAST_FREE | DEV_TX_OFFLOAD_MT_LOCKFREE | \
67 DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT | \
68 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \
69 DEV_TX_OFFLOAD_TCP_CKSUM | DEV_TX_OFFLOAD_UDP_CKSUM | \
70 DEV_TX_OFFLOAD_SCTP_CKSUM | DEV_TX_OFFLOAD_TCP_TSO | \
71 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
72 DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_MULTI_SEGS | \
73 DEV_TX_OFFLOAD_IPV4_CKSUM)
75 #define CNXK_NIX_RX_OFFLOAD_CAPA \
76 (DEV_RX_OFFLOAD_CHECKSUM | DEV_RX_OFFLOAD_SCTP_CKSUM | \
77 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_SCATTER | \
78 DEV_RX_OFFLOAD_JUMBO_FRAME | DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \
79 DEV_RX_OFFLOAD_RSS_HASH | DEV_RX_OFFLOAD_TIMESTAMP | \
80 DEV_RX_OFFLOAD_VLAN_STRIP)
82 #define RSS_IPV4_ENABLE \
83 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_UDP | \
84 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_SCTP)
86 #define RSS_IPV6_ENABLE \
87 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_UDP | \
88 ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_NONFRAG_IPV6_SCTP)
90 #define RSS_IPV6_EX_ENABLE \
91 (ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | ETH_RSS_IPV6_UDP_EX)
93 #define RSS_MAX_LEVELS 3
95 #define RSS_IPV4_INDEX 0
96 #define RSS_IPV6_INDEX 1
97 #define RSS_TCP_INDEX 2
98 #define RSS_UDP_INDEX 3
99 #define RSS_SCTP_INDEX 4
100 #define RSS_DMAC_INDEX 5
102 /* Default mark value used when none is provided. */
103 #define CNXK_FLOW_ACTION_FLAG_DEFAULT 0xffff
105 /* Default cycle counter mask */
106 #define CNXK_CYCLECOUNTER_MASK 0xffffffffffffffffULL
107 #define CNXK_NIX_TIMESYNC_RX_OFFSET 8
109 #define PTYPE_NON_TUNNEL_WIDTH 16
110 #define PTYPE_TUNNEL_WIDTH 12
111 #define PTYPE_NON_TUNNEL_ARRAY_SZ BIT(PTYPE_NON_TUNNEL_WIDTH)
112 #define PTYPE_TUNNEL_ARRAY_SZ BIT(PTYPE_TUNNEL_WIDTH)
113 #define PTYPE_ARRAY_SZ \
114 ((PTYPE_NON_TUNNEL_ARRAY_SZ + PTYPE_TUNNEL_ARRAY_SZ) * sizeof(uint16_t))
115 /* Fastpath lookup */
116 #define CNXK_NIX_FASTPATH_LOOKUP_MEM "cnxk_nix_fastpath_lookup_mem"
118 #define CNXK_NIX_UDP_TUN_BITMASK \
119 ((1ull << (PKT_TX_TUNNEL_VXLAN >> 45)) | \
120 (1ull << (PKT_TX_TUNNEL_GENEVE >> 45)))
123 enum rte_eth_fc_mode mode;
128 struct cnxk_eth_qconf {
130 struct rte_eth_txconf tx;
131 struct rte_eth_rxconf rx;
133 struct rte_mempool *mp;
138 struct cnxk_timesync_info {
141 uint64_t rx_tstamp_dynflag;
142 int tstamp_dynfield_offset;
143 rte_iova_t tx_tstamp_iova;
145 } __plt_cache_aligned;
147 struct cnxk_eth_dev {
154 /* ROC RQs, SQs and CQs */
155 struct roc_nix_rq *rqs;
156 struct roc_nix_sq *sqs;
157 struct roc_nix_cq *cqs;
159 /* Configured queue count */
164 /* Max macfilter entries */
165 uint8_t dmac_filter_count;
166 uint8_t max_mac_entries;
167 bool dmac_filter_enable;
170 uint8_t ptype_disable;
174 /* Pointer back to rte */
175 struct rte_eth_dev *eth_dev;
177 /* HW capabilities / Limitations */
180 uint64_t cq_min_4k : 1;
185 /* Rx and Tx offload capabilities */
186 uint64_t rx_offload_capa;
187 uint64_t tx_offload_capa;
189 /* Configured Rx and Tx offloads */
190 uint64_t rx_offloads;
191 uint64_t tx_offloads;
192 /* Platform specific offload flags */
193 uint16_t rx_offload_flags;
194 uint16_t tx_offload_flags;
196 /* ETHDEV RSS HF bitmask */
197 uint64_t ethdev_rss_hf;
199 /* Saved qconf before lf realloc */
200 struct cnxk_eth_qconf *tx_qconf;
201 struct cnxk_eth_qconf *rx_qconf;
203 /* Flow control configuration */
204 struct cnxk_fc_cfg fc_cfg;
207 struct cnxk_timesync_info tstamp;
208 struct rte_timecounter systime_tc;
209 struct rte_timecounter rx_tstamp_tc;
210 struct rte_timecounter tx_tstamp_tc;
211 double clk_freq_mult;
214 /* Rx burst for cleanup(Only Primary) */
215 eth_rx_burst_t rx_pkt_burst_no_offload;
217 /* Default mac address */
218 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
220 /* LSO Tunnel format indices */
221 uint64_t lso_tun_fmt;
223 /* Per queue statistics counters */
224 uint32_t txq_stat_map[RTE_ETHDEV_QUEUE_STAT_CNTRS];
225 uint32_t rxq_stat_map[RTE_ETHDEV_QUEUE_STAT_CNTRS];
228 struct cnxk_eth_rxq_sp {
229 struct cnxk_eth_dev *dev;
230 struct cnxk_eth_qconf qconf;
232 } __plt_cache_aligned;
234 struct cnxk_eth_txq_sp {
235 struct cnxk_eth_dev *dev;
236 struct cnxk_eth_qconf qconf;
238 } __plt_cache_aligned;
240 static inline struct cnxk_eth_dev *
241 cnxk_eth_pmd_priv(const struct rte_eth_dev *eth_dev)
243 return eth_dev->data->dev_private;
246 static inline struct cnxk_eth_rxq_sp *
247 cnxk_eth_rxq_to_sp(void *__rxq)
249 return ((struct cnxk_eth_rxq_sp *)__rxq) - 1;
252 static inline struct cnxk_eth_txq_sp *
253 cnxk_eth_txq_to_sp(void *__txq)
255 return ((struct cnxk_eth_txq_sp *)__txq) - 1;
258 /* Common ethdev ops */
259 extern struct eth_dev_ops cnxk_eth_dev_ops;
261 /* Common flow ops */
262 extern struct rte_flow_ops cnxk_flow_ops;
265 int cnxk_nix_probe(struct rte_pci_driver *pci_drv,
266 struct rte_pci_device *pci_dev);
267 int cnxk_nix_remove(struct rte_pci_device *pci_dev);
268 int cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
269 int cnxk_nix_mc_addr_list_configure(struct rte_eth_dev *eth_dev,
270 struct rte_ether_addr *mc_addr_set,
271 uint32_t nb_mc_addr);
272 int cnxk_nix_mac_addr_add(struct rte_eth_dev *eth_dev,
273 struct rte_ether_addr *addr, uint32_t index,
275 void cnxk_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index);
276 int cnxk_nix_mac_addr_set(struct rte_eth_dev *eth_dev,
277 struct rte_ether_addr *addr);
278 int cnxk_nix_promisc_enable(struct rte_eth_dev *eth_dev);
279 int cnxk_nix_promisc_disable(struct rte_eth_dev *eth_dev);
280 int cnxk_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);
281 int cnxk_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);
282 int cnxk_nix_info_get(struct rte_eth_dev *eth_dev,
283 struct rte_eth_dev_info *dev_info);
284 int cnxk_nix_rx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
285 struct rte_eth_burst_mode *mode);
286 int cnxk_nix_tx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
287 struct rte_eth_burst_mode *mode);
288 int cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
289 struct rte_eth_fc_conf *fc_conf);
290 int cnxk_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
291 struct rte_eth_fc_conf *fc_conf);
292 int cnxk_nix_set_link_up(struct rte_eth_dev *eth_dev);
293 int cnxk_nix_set_link_down(struct rte_eth_dev *eth_dev);
294 int cnxk_nix_get_module_info(struct rte_eth_dev *eth_dev,
295 struct rte_eth_dev_module_info *modinfo);
296 int cnxk_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
297 struct rte_dev_eeprom_info *info);
298 int cnxk_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
299 uint16_t rx_queue_id);
300 int cnxk_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
301 uint16_t rx_queue_id);
302 int cnxk_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool);
303 int cnxk_nix_tx_done_cleanup(void *txq, uint32_t free_cnt);
304 int cnxk_nix_flow_ops_get(struct rte_eth_dev *eth_dev,
305 const struct rte_flow_ops **ops);
306 int cnxk_nix_configure(struct rte_eth_dev *eth_dev);
307 int cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
308 uint16_t nb_desc, uint16_t fp_tx_q_sz,
309 const struct rte_eth_txconf *tx_conf);
310 int cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
311 uint16_t nb_desc, uint16_t fp_rx_q_sz,
312 const struct rte_eth_rxconf *rx_conf,
313 struct rte_mempool *mp);
314 int cnxk_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid);
315 int cnxk_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid);
316 int cnxk_nix_dev_start(struct rte_eth_dev *eth_dev);
317 int cnxk_nix_timesync_enable(struct rte_eth_dev *eth_dev);
318 int cnxk_nix_timesync_disable(struct rte_eth_dev *eth_dev);
319 int cnxk_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev,
320 struct timespec *timestamp,
322 int cnxk_nix_timesync_read_tx_timestamp(struct rte_eth_dev *eth_dev,
323 struct timespec *timestamp);
324 int cnxk_nix_timesync_read_time(struct rte_eth_dev *eth_dev,
325 struct timespec *ts);
326 int cnxk_nix_timesync_write_time(struct rte_eth_dev *eth_dev,
327 const struct timespec *ts);
328 int cnxk_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta);
329 int cnxk_nix_tsc_convert(struct cnxk_eth_dev *dev);
330 int cnxk_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *clock);
332 uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev);
333 int cnxk_nix_tm_ops_get(struct rte_eth_dev *eth_dev, void *ops);
334 int cnxk_nix_tm_set_queue_rate_limit(struct rte_eth_dev *eth_dev,
335 uint16_t queue_idx, uint16_t tx_rate);
338 uint32_t cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
340 int cnxk_nix_reta_update(struct rte_eth_dev *eth_dev,
341 struct rte_eth_rss_reta_entry64 *reta_conf,
343 int cnxk_nix_reta_query(struct rte_eth_dev *eth_dev,
344 struct rte_eth_rss_reta_entry64 *reta_conf,
346 int cnxk_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
347 struct rte_eth_rss_conf *rss_conf);
348 int cnxk_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
349 struct rte_eth_rss_conf *rss_conf);
352 void cnxk_nix_toggle_flag_link_cfg(struct cnxk_eth_dev *dev, bool set);
353 void cnxk_eth_dev_link_status_cb(struct roc_nix *nix,
354 struct roc_nix_link_info *link);
355 void cnxk_eth_dev_link_status_get_cb(struct roc_nix *nix,
356 struct roc_nix_link_info *link);
357 int cnxk_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
358 int cnxk_nix_queue_stats_mapping(struct rte_eth_dev *dev, uint16_t queue_id,
359 uint8_t stat_idx, uint8_t is_rx);
360 int cnxk_nix_stats_reset(struct rte_eth_dev *dev);
361 int cnxk_nix_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
362 int cnxk_nix_xstats_get(struct rte_eth_dev *eth_dev,
363 struct rte_eth_xstat *xstats, unsigned int n);
364 int cnxk_nix_xstats_get_names(struct rte_eth_dev *eth_dev,
365 struct rte_eth_xstat_name *xstats_names,
367 int cnxk_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,
368 struct rte_eth_xstat_name *xstats_names,
369 const uint64_t *ids, unsigned int limit);
370 int cnxk_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids,
371 uint64_t *values, unsigned int n);
372 int cnxk_nix_xstats_reset(struct rte_eth_dev *eth_dev);
373 int cnxk_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
375 void cnxk_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid,
376 struct rte_eth_rxq_info *qinfo);
377 void cnxk_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid,
378 struct rte_eth_txq_info *qinfo);
380 /* Lookup configuration */
381 const uint32_t *cnxk_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev);
382 void *cnxk_nix_fastpath_lookup_mem_get(void);
385 int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs,
386 struct cnxk_eth_dev *dev);
389 int cnxk_nix_dev_get_reg(struct rte_eth_dev *eth_dev,
390 struct rte_dev_reg_info *regs);
392 /* Other private functions */
393 int nix_recalc_mtu(struct rte_eth_dev *eth_dev);
396 static __rte_always_inline uint64_t
397 cnxk_pktmbuf_detach(struct rte_mbuf *m)
399 struct rte_mempool *mp = m->pool;
400 uint32_t mbuf_size, buf_len;
405 /* Update refcount of direct mbuf */
406 md = rte_mbuf_from_indirect(m);
407 refcount = rte_mbuf_refcnt_update(md, -1);
409 priv_size = rte_pktmbuf_priv_size(mp);
410 mbuf_size = (uint32_t)(sizeof(struct rte_mbuf) + priv_size);
411 buf_len = rte_pktmbuf_data_room_size(mp);
413 m->priv_size = priv_size;
414 m->buf_addr = (char *)m + mbuf_size;
415 m->buf_iova = rte_mempool_virt2iova(m) + mbuf_size;
416 m->buf_len = (uint16_t)buf_len;
417 rte_pktmbuf_reset_headroom(m);
423 /* Now indirect mbuf is safe to free */
427 rte_mbuf_refcnt_set(md, 1);
438 static __rte_always_inline uint64_t
439 cnxk_nix_prefree_seg(struct rte_mbuf *m)
441 if (likely(rte_mbuf_refcnt_read(m) == 1)) {
442 if (!RTE_MBUF_DIRECT(m))
443 return cnxk_pktmbuf_detach(m);
448 } else if (rte_mbuf_refcnt_update(m, -1) == 0) {
449 if (!RTE_MBUF_DIRECT(m))
450 return cnxk_pktmbuf_detach(m);
452 rte_mbuf_refcnt_set(m, 1);
458 /* Mbuf is having refcount more than 1 so need not to be freed */
462 static inline rte_mbuf_timestamp_t *
463 cnxk_nix_timestamp_dynfield(struct rte_mbuf *mbuf,
464 struct cnxk_timesync_info *info)
466 return RTE_MBUF_DYNFIELD(mbuf, info->tstamp_dynfield_offset,
467 rte_mbuf_timestamp_t *);
470 static __rte_always_inline void
471 cnxk_nix_mbuf_to_tstamp(struct rte_mbuf *mbuf,
472 struct cnxk_timesync_info *tstamp,
473 const uint8_t ts_enable, const uint8_t mseg_enable,
474 uint64_t *tstamp_ptr)
478 mbuf->pkt_len -= CNXK_NIX_TIMESYNC_RX_OFFSET;
479 mbuf->data_len -= CNXK_NIX_TIMESYNC_RX_OFFSET;
482 /* Reading the rx timestamp inserted by CGX, viz at
483 * starting of the packet data.
485 *cnxk_nix_timestamp_dynfield(mbuf, tstamp) =
486 rte_be_to_cpu_64(*tstamp_ptr);
487 /* PKT_RX_IEEE1588_TMST flag needs to be set only in case
488 * PTP packets are received.
490 if (mbuf->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC) {
492 *cnxk_nix_timestamp_dynfield(mbuf, tstamp);
493 tstamp->rx_ready = 1;
494 mbuf->ol_flags |= PKT_RX_IEEE1588_PTP |
495 PKT_RX_IEEE1588_TMST |
496 tstamp->rx_tstamp_dynflag;
501 #endif /* __CNXK_ETHDEV_H__ */