drivers/net/cnxk/cnxk_ethdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4 #ifndef __CNXK_ETHDEV_H__
   5 #define __CNXK_ETHDEV_H__
   6
   7 #include <math.h>
   8 #include <stdint.h>
   9
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_kvargs.h>
  13
  14 #include "roc_api.h"
  15
  16 #define CNXK_ETH_DEV_PMD_VERSION "1.0"
  17
  18 /* VLAN tag inserted by NIX_TX_VTAG_ACTION.
  19  * In Tx space is always reserved for this in FRS.
  20  */
  21 #define CNXK_NIX_MAX_VTAG_INS      2
  22 #define CNXK_NIX_MAX_VTAG_ACT_SIZE (4 * CNXK_NIX_MAX_VTAG_INS)
  23
  24 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
  25 #define CNXK_NIX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8)
  26
  27 #define CNXK_NIX_RX_MIN_DESC        16
  28 #define CNXK_NIX_RX_MIN_DESC_ALIGN  16
  29 #define CNXK_NIX_RX_NB_SEG_MAX      6
  30 #define CNXK_NIX_RX_DEFAULT_RING_SZ 4096
  31 /* Max supported SQB count */
  32 #define CNXK_NIX_TX_MAX_SQB 512
  33
  34 /* If PTP is enabled additional SEND MEM DESC is required which
  35  * takes 2 words, hence max 7 iova address are possible
  36  */
  37 #if defined(RTE_LIBRTE_IEEE1588)
  38 #define CNXK_NIX_TX_NB_SEG_MAX 7
  39 #else
  40 #define CNXK_NIX_TX_NB_SEG_MAX 9
  41 #endif
  42
  43 #define CNXK_NIX_RSS_L3_L4_SRC_DST                                             \
  44         (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | ETH_RSS_L4_SRC_ONLY |     \
  45          ETH_RSS_L4_DST_ONLY)
  46
  47 #define CNXK_NIX_RSS_OFFLOAD                                                   \
  48         (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP |               \
  49          ETH_RSS_SCTP | ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD |                  \
  50          CNXK_NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | ETH_RSS_C_VLAN)
  51
  52 #define CNXK_NIX_TX_OFFLOAD_CAPA                                               \
  53         (DEV_TX_OFFLOAD_MBUF_FAST_FREE | DEV_TX_OFFLOAD_MT_LOCKFREE |          \
  54          DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT |             \
  55          DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_TX_OFFLOAD_OUTER_UDP_CKSUM |    \
  56          DEV_TX_OFFLOAD_TCP_CKSUM | DEV_TX_OFFLOAD_UDP_CKSUM |                 \
  57          DEV_TX_OFFLOAD_SCTP_CKSUM | DEV_TX_OFFLOAD_TCP_TSO |                  \
  58          DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GENEVE_TNL_TSO |        \
  59          DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_MULTI_SEGS |              \
  60          DEV_TX_OFFLOAD_IPV4_CKSUM)
  61
  62 #define CNXK_NIX_RX_OFFLOAD_CAPA                                               \
  63         (DEV_RX_OFFLOAD_CHECKSUM | DEV_RX_OFFLOAD_SCTP_CKSUM |                 \
  64          DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_SCATTER |            \
  65          DEV_RX_OFFLOAD_JUMBO_FRAME | DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |         \
  66          DEV_RX_OFFLOAD_RSS_HASH)
  67
  68 #define RSS_IPV4_ENABLE                                                        \
  69         (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_UDP |         \
  70          ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_SCTP)
  71
  72 #define RSS_IPV6_ENABLE                                                        \
  73         (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_UDP |         \
  74          ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_NONFRAG_IPV6_SCTP)
  75
  76 #define RSS_IPV6_EX_ENABLE                                                     \
  77         (ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | ETH_RSS_IPV6_UDP_EX)
  78
  79 #define RSS_MAX_LEVELS 3
  80
  81 #define RSS_IPV4_INDEX 0
  82 #define RSS_IPV6_INDEX 1
  83 #define RSS_TCP_INDEX  2
  84 #define RSS_UDP_INDEX  3
  85 #define RSS_SCTP_INDEX 4
  86 #define RSS_DMAC_INDEX 5
  87
  88 struct cnxk_eth_qconf {
  89         union {
  90                 struct rte_eth_txconf tx;
  91                 struct rte_eth_rxconf rx;
  92         } conf;
  93         struct rte_mempool *mp;
  94         uint16_t nb_desc;
  95         uint8_t valid;
  96 };
  97
  98 struct cnxk_eth_dev {
  99         /* ROC NIX */
 100         struct roc_nix nix;
 101
 102         /* ROC RQs, SQs and CQs */
 103         struct roc_nix_rq *rqs;
 104         struct roc_nix_sq *sqs;
 105         struct roc_nix_cq *cqs;
 106
 107         /* Configured queue count */
 108         uint16_t nb_rxq;
 109         uint16_t nb_txq;
 110         uint8_t configured;
 111
 112         /* Max macfilter entries */
 113         uint8_t max_mac_entries;
 114
 115         uint16_t flags;
 116         bool scalar_ena;
 117
 118         /* Pointer back to rte */
 119         struct rte_eth_dev *eth_dev;
 120
 121         /* HW capabilities / Limitations */
 122         union {
 123                 struct {
 124                         uint64_t cq_min_4k : 1;
 125                 };
 126                 uint64_t hwcap;
 127         };
 128
 129         /* Rx and Tx offload capabilities */
 130         uint64_t rx_offload_capa;
 131         uint64_t tx_offload_capa;
 132         uint32_t speed_capa;
 133         /* Configured Rx and Tx offloads */
 134         uint64_t rx_offloads;
 135         uint64_t tx_offloads;
 136         /* Platform specific offload flags */
 137         uint16_t rx_offload_flags;
 138         uint16_t tx_offload_flags;
 139
 140         /* ETHDEV RSS HF bitmask */
 141         uint64_t ethdev_rss_hf;
 142
 143         /* Saved qconf before lf realloc */
 144         struct cnxk_eth_qconf *tx_qconf;
 145         struct cnxk_eth_qconf *rx_qconf;
 146
 147         /* Default mac address */
 148         uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
 149
 150         /* LSO Tunnel format indices */
 151         uint64_t lso_tun_fmt;
 152 };
 153
 154 struct cnxk_eth_rxq_sp {
 155         struct cnxk_eth_dev *dev;
 156         struct cnxk_eth_qconf qconf;
 157         uint16_t qid;
 158 } __plt_cache_aligned;
 159
 160 struct cnxk_eth_txq_sp {
 161         struct cnxk_eth_dev *dev;
 162         struct cnxk_eth_qconf qconf;
 163         uint16_t qid;
 164 } __plt_cache_aligned;
 165
 166 static inline struct cnxk_eth_dev *
 167 cnxk_eth_pmd_priv(struct rte_eth_dev *eth_dev)
 168 {
 169         return eth_dev->data->dev_private;
 170 }
 171
 172 static inline struct cnxk_eth_rxq_sp *
 173 cnxk_eth_rxq_to_sp(void *__rxq)
 174 {
 175         return ((struct cnxk_eth_rxq_sp *)__rxq) - 1;
 176 }
 177
 178 static inline struct cnxk_eth_txq_sp *
 179 cnxk_eth_txq_to_sp(void *__txq)
 180 {
 181         return ((struct cnxk_eth_txq_sp *)__txq) - 1;
 182 }
 183
 184 /* Common ethdev ops */
 185 extern struct eth_dev_ops cnxk_eth_dev_ops;
 186
 187 /* Ops */
 188 int cnxk_nix_probe(struct rte_pci_driver *pci_drv,
 189                    struct rte_pci_device *pci_dev);
 190 int cnxk_nix_remove(struct rte_pci_device *pci_dev);
 191 int cnxk_nix_info_get(struct rte_eth_dev *eth_dev,
 192                       struct rte_eth_dev_info *dev_info);
 193 int cnxk_nix_configure(struct rte_eth_dev *eth_dev);
 194
 195 /* RSS */
 196 uint32_t cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
 197                                 uint8_t rss_level);
 198
 199 /* Devargs */
 200 int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs,
 201                               struct cnxk_eth_dev *dev);
 202
 203 #endif /* __CNXK_ETHDEV_H__ */