drivers/net/cnxk/cnxk_ethdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4 #ifndef __CNXK_ETHDEV_H__
   5 #define __CNXK_ETHDEV_H__
   6
   7 #include <math.h>
   8 #include <stdint.h>
   9
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_kvargs.h>
  13 #include <rte_mbuf.h>
  14 #include <rte_mbuf_pool_ops.h>
  15 #include <rte_mempool.h>
  16
  17 #include "roc_api.h"
  18
  19 #define CNXK_ETH_DEV_PMD_VERSION "1.0"
  20
  21 /* Used for struct cnxk_eth_dev::flags */
  22 #define CNXK_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
  23
  24 /* VLAN tag inserted by NIX_TX_VTAG_ACTION.
  25  * In Tx space is always reserved for this in FRS.
  26  */
  27 #define CNXK_NIX_MAX_VTAG_INS      2
  28 #define CNXK_NIX_MAX_VTAG_ACT_SIZE (4 * CNXK_NIX_MAX_VTAG_INS)
  29
  30 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
  31 #define CNXK_NIX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8)
  32
  33 #define CNXK_NIX_RX_MIN_DESC        16
  34 #define CNXK_NIX_RX_MIN_DESC_ALIGN  16
  35 #define CNXK_NIX_RX_NB_SEG_MAX      6
  36 #define CNXK_NIX_RX_DEFAULT_RING_SZ 4096
  37 /* Max supported SQB count */
  38 #define CNXK_NIX_TX_MAX_SQB 512
  39
  40 /* If PTP is enabled additional SEND MEM DESC is required which
  41  * takes 2 words, hence max 7 iova address are possible
  42  */
  43 #if defined(RTE_LIBRTE_IEEE1588)
  44 #define CNXK_NIX_TX_NB_SEG_MAX 7
  45 #else
  46 #define CNXK_NIX_TX_NB_SEG_MAX 9
  47 #endif
  48
  49 #define CNXK_NIX_RSS_L3_L4_SRC_DST                                             \
  50         (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | ETH_RSS_L4_SRC_ONLY |     \
  51          ETH_RSS_L4_DST_ONLY)
  52
  53 #define CNXK_NIX_RSS_OFFLOAD                                                   \
  54         (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP |               \
  55          ETH_RSS_SCTP | ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD |                  \
  56          CNXK_NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | ETH_RSS_C_VLAN)
  57
  58 #define CNXK_NIX_TX_OFFLOAD_CAPA                                               \
  59         (DEV_TX_OFFLOAD_MBUF_FAST_FREE | DEV_TX_OFFLOAD_MT_LOCKFREE |          \
  60          DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT |             \
  61          DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_TX_OFFLOAD_OUTER_UDP_CKSUM |    \
  62          DEV_TX_OFFLOAD_TCP_CKSUM | DEV_TX_OFFLOAD_UDP_CKSUM |                 \
  63          DEV_TX_OFFLOAD_SCTP_CKSUM | DEV_TX_OFFLOAD_TCP_TSO |                  \
  64          DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GENEVE_TNL_TSO |        \
  65          DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_MULTI_SEGS |              \
  66          DEV_TX_OFFLOAD_IPV4_CKSUM)
  67
  68 #define CNXK_NIX_RX_OFFLOAD_CAPA                                               \
  69         (DEV_RX_OFFLOAD_CHECKSUM | DEV_RX_OFFLOAD_SCTP_CKSUM |                 \
  70          DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_SCATTER |            \
  71          DEV_RX_OFFLOAD_JUMBO_FRAME | DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |         \
  72          DEV_RX_OFFLOAD_RSS_HASH)
  73
  74 #define RSS_IPV4_ENABLE                                                        \
  75         (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_UDP |         \
  76          ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_SCTP)
  77
  78 #define RSS_IPV6_ENABLE                                                        \
  79         (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_UDP |         \
  80          ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_NONFRAG_IPV6_SCTP)
  81
  82 #define RSS_IPV6_EX_ENABLE                                                     \
  83         (ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | ETH_RSS_IPV6_UDP_EX)
  84
  85 #define RSS_MAX_LEVELS 3
  86
  87 #define RSS_IPV4_INDEX 0
  88 #define RSS_IPV6_INDEX 1
  89 #define RSS_TCP_INDEX  2
  90 #define RSS_UDP_INDEX  3
  91 #define RSS_SCTP_INDEX 4
  92 #define RSS_DMAC_INDEX 5
  93
  94 /* Default mark value used when none is provided. */
  95 #define CNXK_FLOW_ACTION_FLAG_DEFAULT 0xffff
  96
  97 #define PTYPE_NON_TUNNEL_WIDTH    16
  98 #define PTYPE_TUNNEL_WIDTH        12
  99 #define PTYPE_NON_TUNNEL_ARRAY_SZ BIT(PTYPE_NON_TUNNEL_WIDTH)
 100 #define PTYPE_TUNNEL_ARRAY_SZ     BIT(PTYPE_TUNNEL_WIDTH)
 101 #define PTYPE_ARRAY_SZ                                                         \
 102         ((PTYPE_NON_TUNNEL_ARRAY_SZ + PTYPE_TUNNEL_ARRAY_SZ) * sizeof(uint16_t))
 103 /* Fastpath lookup */
 104 #define CNXK_NIX_FASTPATH_LOOKUP_MEM "cnxk_nix_fastpath_lookup_mem"
 105
 106 #define CNXK_NIX_UDP_TUN_BITMASK                                               \
 107         ((1ull << (PKT_TX_TUNNEL_VXLAN >> 45)) |                               \
 108          (1ull << (PKT_TX_TUNNEL_GENEVE >> 45)))
 109
 110 struct cnxk_eth_qconf {
 111         union {
 112                 struct rte_eth_txconf tx;
 113                 struct rte_eth_rxconf rx;
 114         } conf;
 115         struct rte_mempool *mp;
 116         uint16_t nb_desc;
 117         uint8_t valid;
 118 };
 119
 120 struct cnxk_eth_dev {
 121         /* ROC NIX */
 122         struct roc_nix nix;
 123
 124         /* ROC RQs, SQs and CQs */
 125         struct roc_nix_rq *rqs;
 126         struct roc_nix_sq *sqs;
 127         struct roc_nix_cq *cqs;
 128
 129         /* Configured queue count */
 130         uint16_t nb_rxq;
 131         uint16_t nb_txq;
 132         uint8_t configured;
 133
 134         /* Max macfilter entries */
 135         uint8_t max_mac_entries;
 136
 137         uint16_t flags;
 138         uint8_t ptype_disable;
 139         bool scalar_ena;
 140
 141         /* Pointer back to rte */
 142         struct rte_eth_dev *eth_dev;
 143
 144         /* HW capabilities / Limitations */
 145         union {
 146                 struct {
 147                         uint64_t cq_min_4k : 1;
 148                 };
 149                 uint64_t hwcap;
 150         };
 151
 152         /* Rx and Tx offload capabilities */
 153         uint64_t rx_offload_capa;
 154         uint64_t tx_offload_capa;
 155         uint32_t speed_capa;
 156         /* Configured Rx and Tx offloads */
 157         uint64_t rx_offloads;
 158         uint64_t tx_offloads;
 159         /* Platform specific offload flags */
 160         uint16_t rx_offload_flags;
 161         uint16_t tx_offload_flags;
 162
 163         /* ETHDEV RSS HF bitmask */
 164         uint64_t ethdev_rss_hf;
 165
 166         /* Saved qconf before lf realloc */
 167         struct cnxk_eth_qconf *tx_qconf;
 168         struct cnxk_eth_qconf *rx_qconf;
 169
 170         /* Rx burst for cleanup(Only Primary) */
 171         eth_rx_burst_t rx_pkt_burst_no_offload;
 172
 173         /* Default mac address */
 174         uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
 175
 176         /* LSO Tunnel format indices */
 177         uint64_t lso_tun_fmt;
 178 };
 179
 180 struct cnxk_eth_rxq_sp {
 181         struct cnxk_eth_dev *dev;
 182         struct cnxk_eth_qconf qconf;
 183         uint16_t qid;
 184 } __plt_cache_aligned;
 185
 186 struct cnxk_eth_txq_sp {
 187         struct cnxk_eth_dev *dev;
 188         struct cnxk_eth_qconf qconf;
 189         uint16_t qid;
 190 } __plt_cache_aligned;
 191
 192 static inline struct cnxk_eth_dev *
 193 cnxk_eth_pmd_priv(struct rte_eth_dev *eth_dev)
 194 {
 195         return eth_dev->data->dev_private;
 196 }
 197
 198 static inline struct cnxk_eth_rxq_sp *
 199 cnxk_eth_rxq_to_sp(void *__rxq)
 200 {
 201         return ((struct cnxk_eth_rxq_sp *)__rxq) - 1;
 202 }
 203
 204 static inline struct cnxk_eth_txq_sp *
 205 cnxk_eth_txq_to_sp(void *__txq)
 206 {
 207         return ((struct cnxk_eth_txq_sp *)__txq) - 1;
 208 }
 209
 210 /* Common ethdev ops */
 211 extern struct eth_dev_ops cnxk_eth_dev_ops;
 212
 213 /* Ops */
 214 int cnxk_nix_probe(struct rte_pci_driver *pci_drv,
 215                    struct rte_pci_device *pci_dev);
 216 int cnxk_nix_remove(struct rte_pci_device *pci_dev);
 217 int cnxk_nix_info_get(struct rte_eth_dev *eth_dev,
 218                       struct rte_eth_dev_info *dev_info);
 219 int cnxk_nix_configure(struct rte_eth_dev *eth_dev);
 220 int cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 221                             uint16_t nb_desc, uint16_t fp_tx_q_sz,
 222                             const struct rte_eth_txconf *tx_conf);
 223 int cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 224                             uint16_t nb_desc, uint16_t fp_rx_q_sz,
 225                             const struct rte_eth_rxconf *rx_conf,
 226                             struct rte_mempool *mp);
 227 int cnxk_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid);
 228
 229 uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev);
 230
 231 /* RSS */
 232 uint32_t cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
 233                                 uint8_t rss_level);
 234
 235 /* Link */
 236 void cnxk_eth_dev_link_status_cb(struct roc_nix *nix,
 237                                  struct roc_nix_link_info *link);
 238 int cnxk_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
 239
 240 /* Lookup configuration */
 241 const uint32_t *cnxk_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev);
 242 void *cnxk_nix_fastpath_lookup_mem_get(void);
 243
 244 /* Devargs */
 245 int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs,
 246                               struct cnxk_eth_dev *dev);
 247
 248 /* Inlines */
 249 static __rte_always_inline uint64_t
 250 cnxk_pktmbuf_detach(struct rte_mbuf *m)
 251 {
 252         struct rte_mempool *mp = m->pool;
 253         uint32_t mbuf_size, buf_len;
 254         struct rte_mbuf *md;
 255         uint16_t priv_size;
 256         uint16_t refcount;
 257
 258         /* Update refcount of direct mbuf */
 259         md = rte_mbuf_from_indirect(m);
 260         refcount = rte_mbuf_refcnt_update(md, -1);
 261
 262         priv_size = rte_pktmbuf_priv_size(mp);
 263         mbuf_size = (uint32_t)(sizeof(struct rte_mbuf) + priv_size);
 264         buf_len = rte_pktmbuf_data_room_size(mp);
 265
 266         m->priv_size = priv_size;
 267         m->buf_addr = (char *)m + mbuf_size;
 268         m->buf_iova = rte_mempool_virt2iova(m) + mbuf_size;
 269         m->buf_len = (uint16_t)buf_len;
 270         rte_pktmbuf_reset_headroom(m);
 271         m->data_len = 0;
 272         m->ol_flags = 0;
 273         m->next = NULL;
 274         m->nb_segs = 1;
 275
 276         /* Now indirect mbuf is safe to free */
 277         rte_pktmbuf_free(m);
 278
 279         if (refcount == 0) {
 280                 rte_mbuf_refcnt_set(md, 1);
 281                 md->data_len = 0;
 282                 md->ol_flags = 0;
 283                 md->next = NULL;
 284                 md->nb_segs = 1;
 285                 return 0;
 286         } else {
 287                 return 1;
 288         }
 289 }
 290
 291 static __rte_always_inline uint64_t
 292 cnxk_nix_prefree_seg(struct rte_mbuf *m)
 293 {
 294         if (likely(rte_mbuf_refcnt_read(m) == 1)) {
 295                 if (!RTE_MBUF_DIRECT(m))
 296                         return cnxk_pktmbuf_detach(m);
 297
 298                 m->next = NULL;
 299                 m->nb_segs = 1;
 300                 return 0;
 301         } else if (rte_mbuf_refcnt_update(m, -1) == 0) {
 302                 if (!RTE_MBUF_DIRECT(m))
 303                         return cnxk_pktmbuf_detach(m);
 304
 305                 rte_mbuf_refcnt_set(m, 1);
 306                 m->next = NULL;
 307                 m->nb_segs = 1;
 308                 return 0;
 309         }
 310
 311         /* Mbuf is having refcount more than 1 so need not to be freed */
 312         return 1;
 313 }
 314
 315 #endif /* __CNXK_ETHDEV_H__ */