1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
4 #ifndef __CNXK_ETHDEV_H__
5 #define __CNXK_ETHDEV_H__
10 #include <ethdev_driver.h>
11 #include <ethdev_pci.h>
12 #include <rte_kvargs.h>
14 #include <rte_mbuf_pool_ops.h>
15 #include <rte_mempool.h>
16 #include <rte_mtr_driver.h>
17 #include <rte_security.h>
18 #include <rte_security_driver.h>
19 #include <rte_tailq.h>
24 #define CNXK_ETH_DEV_PMD_VERSION "1.0"
26 /* Used for struct cnxk_eth_dev::flags */
27 #define CNXK_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
29 /* VLAN tag inserted by NIX_TX_VTAG_ACTION.
30 * In Tx space is always reserved for this in FRS.
32 #define CNXK_NIX_MAX_VTAG_INS 2
33 #define CNXK_NIX_MAX_VTAG_ACT_SIZE (4 * CNXK_NIX_MAX_VTAG_INS)
35 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
36 #define CNXK_NIX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + \
38 CNXK_NIX_MAX_VTAG_ACT_SIZE)
40 #define CNXK_NIX_RX_MIN_DESC 16
41 #define CNXK_NIX_RX_MIN_DESC_ALIGN 16
42 #define CNXK_NIX_RX_NB_SEG_MAX 6
43 #define CNXK_NIX_RX_DEFAULT_RING_SZ 4096
44 /* Max supported SQB count */
45 #define CNXK_NIX_TX_MAX_SQB 512
47 /* If PTP is enabled additional SEND MEM DESC is required which
48 * takes 2 words, hence max 7 iova address are possible
50 #if defined(RTE_LIBRTE_IEEE1588)
51 #define CNXK_NIX_TX_NB_SEG_MAX 7
53 #define CNXK_NIX_TX_NB_SEG_MAX 9
56 #define CNXK_NIX_TX_MSEG_SG_DWORDS \
57 ((RTE_ALIGN_MUL_CEIL(CNXK_NIX_TX_NB_SEG_MAX, 3) / 3) + \
58 CNXK_NIX_TX_NB_SEG_MAX)
60 #define CNXK_NIX_RSS_L3_L4_SRC_DST \
61 (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | ETH_RSS_L4_SRC_ONLY | \
64 #define CNXK_NIX_RSS_OFFLOAD \
65 (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP | \
66 ETH_RSS_SCTP | ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD | \
67 CNXK_NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | ETH_RSS_C_VLAN)
69 #define CNXK_NIX_TX_OFFLOAD_CAPA \
70 (DEV_TX_OFFLOAD_MBUF_FAST_FREE | DEV_TX_OFFLOAD_MT_LOCKFREE | \
71 DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT | \
72 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \
73 DEV_TX_OFFLOAD_TCP_CKSUM | DEV_TX_OFFLOAD_UDP_CKSUM | \
74 DEV_TX_OFFLOAD_SCTP_CKSUM | DEV_TX_OFFLOAD_TCP_TSO | \
75 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
76 DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_MULTI_SEGS | \
77 DEV_TX_OFFLOAD_IPV4_CKSUM | DEV_TX_OFFLOAD_SECURITY)
79 #define CNXK_NIX_RX_OFFLOAD_CAPA \
80 (DEV_RX_OFFLOAD_CHECKSUM | DEV_RX_OFFLOAD_SCTP_CKSUM | \
81 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_SCATTER | \
82 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | DEV_RX_OFFLOAD_RSS_HASH | \
83 DEV_RX_OFFLOAD_TIMESTAMP | DEV_RX_OFFLOAD_VLAN_STRIP | \
84 DEV_RX_OFFLOAD_SECURITY)
86 #define RSS_IPV4_ENABLE \
87 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_UDP | \
88 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_SCTP)
90 #define RSS_IPV6_ENABLE \
91 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_UDP | \
92 ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_NONFRAG_IPV6_SCTP)
94 #define RSS_IPV6_EX_ENABLE \
95 (ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | ETH_RSS_IPV6_UDP_EX)
97 #define RSS_MAX_LEVELS 3
99 #define RSS_IPV4_INDEX 0
100 #define RSS_IPV6_INDEX 1
101 #define RSS_TCP_INDEX 2
102 #define RSS_UDP_INDEX 3
103 #define RSS_SCTP_INDEX 4
104 #define RSS_DMAC_INDEX 5
106 /* Default mark value used when none is provided. */
107 #define CNXK_FLOW_ACTION_FLAG_DEFAULT 0xffff
109 /* Default cycle counter mask */
110 #define CNXK_CYCLECOUNTER_MASK 0xffffffffffffffffULL
111 #define CNXK_NIX_TIMESYNC_RX_OFFSET 8
113 #define PTYPE_NON_TUNNEL_WIDTH 16
114 #define PTYPE_TUNNEL_WIDTH 12
115 #define PTYPE_NON_TUNNEL_ARRAY_SZ BIT(PTYPE_NON_TUNNEL_WIDTH)
116 #define PTYPE_TUNNEL_ARRAY_SZ BIT(PTYPE_TUNNEL_WIDTH)
117 #define PTYPE_ARRAY_SZ \
118 ((PTYPE_NON_TUNNEL_ARRAY_SZ + PTYPE_TUNNEL_ARRAY_SZ) * sizeof(uint16_t))
120 /* NIX_RX_PARSE_S's ERRCODE + ERRLEV (12 bits) */
121 #define ERRCODE_ERRLEN_WIDTH 12
122 #define ERR_ARRAY_SZ ((BIT(ERRCODE_ERRLEN_WIDTH)) * sizeof(uint32_t))
124 /* Fastpath lookup */
125 #define CNXK_NIX_FASTPATH_LOOKUP_MEM "cnxk_nix_fastpath_lookup_mem"
127 #define CNXK_NIX_UDP_TUN_BITMASK \
128 ((1ull << (PKT_TX_TUNNEL_VXLAN >> 45)) | \
129 (1ull << (PKT_TX_TUNNEL_GENEVE >> 45)))
131 /* Subtype from inline outbound error event */
132 #define CNXK_ETHDEV_SEC_OUTB_EV_SUB 0xFFUL
134 /* SPI will be in 20 bits of tag */
135 #define CNXK_ETHDEV_SPI_TAG_MASK 0xFFFFFUL
138 enum rte_eth_fc_mode mode;
143 struct cnxk_eth_qconf {
145 struct rte_eth_txconf tx;
146 struct rte_eth_rxconf rx;
148 struct rte_mempool *mp;
153 struct cnxk_timesync_info {
156 uint64_t rx_tstamp_dynflag;
157 int tstamp_dynfield_offset;
158 rte_iova_t tx_tstamp_iova;
160 } __plt_cache_aligned;
162 struct cnxk_meter_node {
163 #define MAX_PRV_MTR_NODES 10
164 TAILQ_ENTRY(cnxk_meter_node) next;
165 /**< Pointer to the next flow meter structure. */
166 uint32_t id; /**< Usr mtr id. */
167 struct cnxk_mtr_profile_node *profile;
168 struct cnxk_mtr_policy_node *policy;
169 uint32_t bpf_id; /**< Hw mtr id. */
173 uint32_t prev_id[MAX_PRV_MTR_NODES]; /**< Prev mtr id for chaining */
175 uint32_t next_id; /**< Next mtr id for chaining */
178 struct rte_mtr_params params;
179 struct roc_nix_bpf_objs profs;
185 enum rte_eth_hash_function func;
194 struct policy_actions {
195 uint32_t action_fate;
199 struct action_rss *rss_desc;
203 struct cnxk_mtr_policy_node {
204 TAILQ_ENTRY(cnxk_mtr_policy_node) next;
205 /**< Pointer to the next flow meter structure. */
206 uint32_t id; /**< Policy id */
207 uint32_t mtr_id; /** Meter id */
208 struct rte_mtr_meter_policy_params policy;
209 struct policy_actions actions[RTE_COLORS];
213 struct cnxk_mtr_profile_node {
214 TAILQ_ENTRY(cnxk_mtr_profile_node) next;
215 struct rte_mtr_meter_profile profile; /**< Profile detail. */
216 uint32_t ref_cnt; /**< Use count. */
217 uint32_t id; /**< Profile id. */
220 TAILQ_HEAD(cnxk_mtr_profiles, cnxk_mtr_profile_node);
221 TAILQ_HEAD(cnxk_mtr_policy, cnxk_mtr_policy_node);
222 TAILQ_HEAD(cnxk_mtr, cnxk_meter_node);
224 /* Security session private data */
225 struct cnxk_eth_sec_sess {
227 TAILQ_ENTRY(cnxk_eth_sec_sess) entry;
229 /* Inbound SA is from NIX_RX_IPSEC_SA_BASE or
230 * Outbound SA from roc_nix_inl_outb_sa_base_get()
240 /* Back pointer to session */
241 struct rte_security_session *sess;
246 /* Inbound session on inl dev */
250 TAILQ_HEAD(cnxk_eth_sec_sess_list, cnxk_eth_sec_sess);
252 /* Inbound security data */
253 struct cnxk_eth_dev_sec_inb {
254 /* IPSec inbound max SPI */
257 /* Using inbound with inline device */
260 /* Device argument to force inline device for inb */
263 /* Active sessions */
266 /* List of sessions */
267 struct cnxk_eth_sec_sess_list list;
270 /* Outbound security data */
271 struct cnxk_eth_dev_sec_outb {
272 /* IPSec outbound max SA */
275 /* Per CPT LF descriptor count */
279 struct plt_bitmap *sa_bmap;
281 /* SA bitmap memory */
288 struct roc_cpt_lf *lf_base;
290 /* Crypto queues => CPT lf count */
291 uint16_t nb_crypto_qs;
293 /* Active sessions */
296 /* List of sessions */
297 struct cnxk_eth_sec_sess_list list;
300 struct cnxk_eth_dev {
307 /* ROC RQs, SQs and CQs */
308 struct roc_nix_rq *rqs;
309 struct roc_nix_sq *sqs;
310 struct roc_nix_cq *cqs;
312 /* Configured queue count */
318 /* Max macfilter entries */
319 uint8_t dmac_filter_count;
320 uint8_t max_mac_entries;
321 bool dmac_filter_enable;
324 uint8_t ptype_disable;
328 /* Pointer back to rte */
329 struct rte_eth_dev *eth_dev;
331 /* HW capabilities / Limitations */
334 uint64_t cq_min_4k : 1;
335 uint64_t ipsecd_drop_re_dis : 1;
340 /* Rx and Tx offload capabilities */
341 uint64_t rx_offload_capa;
342 uint64_t tx_offload_capa;
344 /* Configured Rx and Tx offloads */
345 uint64_t rx_offloads;
346 uint64_t tx_offloads;
347 /* Platform specific offload flags */
348 uint16_t rx_offload_flags;
349 uint16_t tx_offload_flags;
351 /* ETHDEV RSS HF bitmask */
352 uint64_t ethdev_rss_hf;
354 /* Saved qconf before lf realloc */
355 struct cnxk_eth_qconf *tx_qconf;
356 struct cnxk_eth_qconf *rx_qconf;
358 /* Flow control configuration */
359 struct cnxk_fc_cfg fc_cfg;
362 struct cnxk_timesync_info tstamp;
363 struct rte_timecounter systime_tc;
364 struct rte_timecounter rx_tstamp_tc;
365 struct rte_timecounter tx_tstamp_tc;
366 double clk_freq_mult;
369 /* Ingress policer */
370 enum roc_nix_bpf_color precolor_tbl[ROC_NIX_BPF_PRE_COLOR_MAX];
371 struct cnxk_mtr_profiles mtr_profiles;
372 struct cnxk_mtr_policy mtr_policy;
375 /* Rx burst for cleanup(Only Primary) */
376 eth_rx_burst_t rx_pkt_burst_no_offload;
378 /* Default mac address */
379 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
381 /* LSO Tunnel format indices */
382 uint64_t lso_tun_fmt;
384 /* Per queue statistics counters */
385 uint32_t txq_stat_map[RTE_ETHDEV_QUEUE_STAT_CNTRS];
386 uint32_t rxq_stat_map[RTE_ETHDEV_QUEUE_STAT_CNTRS];
389 struct cnxk_eth_dev_sec_inb inb;
390 struct cnxk_eth_dev_sec_outb outb;
393 struct cnxk_eth_rxq_sp {
394 struct cnxk_eth_dev *dev;
395 struct cnxk_eth_qconf qconf;
397 } __plt_cache_aligned;
399 struct cnxk_eth_txq_sp {
400 struct cnxk_eth_dev *dev;
401 struct cnxk_eth_qconf qconf;
403 } __plt_cache_aligned;
405 static inline struct cnxk_eth_dev *
406 cnxk_eth_pmd_priv(const struct rte_eth_dev *eth_dev)
408 return eth_dev->data->dev_private;
411 static inline struct cnxk_eth_rxq_sp *
412 cnxk_eth_rxq_to_sp(void *__rxq)
414 return ((struct cnxk_eth_rxq_sp *)__rxq) - 1;
417 static inline struct cnxk_eth_txq_sp *
418 cnxk_eth_txq_to_sp(void *__txq)
420 return ((struct cnxk_eth_txq_sp *)__txq) - 1;
423 /* Common ethdev ops */
424 extern struct eth_dev_ops cnxk_eth_dev_ops;
426 /* Common flow ops */
427 extern struct rte_flow_ops cnxk_flow_ops;
429 /* Common security ops */
430 extern struct rte_security_ops cnxk_eth_sec_ops;
433 int cnxk_nix_probe(struct rte_pci_driver *pci_drv,
434 struct rte_pci_device *pci_dev);
435 int cnxk_nix_remove(struct rte_pci_device *pci_dev);
436 int cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
437 int cnxk_nix_mc_addr_list_configure(struct rte_eth_dev *eth_dev,
438 struct rte_ether_addr *mc_addr_set,
439 uint32_t nb_mc_addr);
440 int cnxk_nix_mac_addr_add(struct rte_eth_dev *eth_dev,
441 struct rte_ether_addr *addr, uint32_t index,
443 void cnxk_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index);
444 int cnxk_nix_mac_addr_set(struct rte_eth_dev *eth_dev,
445 struct rte_ether_addr *addr);
446 int cnxk_nix_promisc_enable(struct rte_eth_dev *eth_dev);
447 int cnxk_nix_promisc_disable(struct rte_eth_dev *eth_dev);
448 int cnxk_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);
449 int cnxk_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);
450 int cnxk_nix_info_get(struct rte_eth_dev *eth_dev,
451 struct rte_eth_dev_info *dev_info);
452 int cnxk_nix_rx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
453 struct rte_eth_burst_mode *mode);
454 int cnxk_nix_tx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
455 struct rte_eth_burst_mode *mode);
456 int cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
457 struct rte_eth_fc_conf *fc_conf);
458 int cnxk_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
459 struct rte_eth_fc_conf *fc_conf);
460 int cnxk_nix_set_link_up(struct rte_eth_dev *eth_dev);
461 int cnxk_nix_set_link_down(struct rte_eth_dev *eth_dev);
462 int cnxk_nix_get_module_info(struct rte_eth_dev *eth_dev,
463 struct rte_eth_dev_module_info *modinfo);
464 int cnxk_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
465 struct rte_dev_eeprom_info *info);
466 int cnxk_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
467 uint16_t rx_queue_id);
468 int cnxk_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
469 uint16_t rx_queue_id);
470 int cnxk_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool);
471 int cnxk_nix_tx_done_cleanup(void *txq, uint32_t free_cnt);
472 int cnxk_nix_flow_ops_get(struct rte_eth_dev *eth_dev,
473 const struct rte_flow_ops **ops);
474 int cnxk_nix_configure(struct rte_eth_dev *eth_dev);
475 int cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
476 uint16_t nb_desc, uint16_t fp_tx_q_sz,
477 const struct rte_eth_txconf *tx_conf);
478 int cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
479 uint16_t nb_desc, uint16_t fp_rx_q_sz,
480 const struct rte_eth_rxconf *rx_conf,
481 struct rte_mempool *mp);
482 int cnxk_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid);
483 int cnxk_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid);
484 int cnxk_nix_dev_start(struct rte_eth_dev *eth_dev);
485 int cnxk_nix_timesync_enable(struct rte_eth_dev *eth_dev);
486 int cnxk_nix_timesync_disable(struct rte_eth_dev *eth_dev);
487 int cnxk_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev,
488 struct timespec *timestamp,
490 int cnxk_nix_timesync_read_tx_timestamp(struct rte_eth_dev *eth_dev,
491 struct timespec *timestamp);
492 int cnxk_nix_timesync_read_time(struct rte_eth_dev *eth_dev,
493 struct timespec *ts);
494 int cnxk_nix_timesync_write_time(struct rte_eth_dev *eth_dev,
495 const struct timespec *ts);
496 int cnxk_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta);
497 int cnxk_nix_tsc_convert(struct cnxk_eth_dev *dev);
498 int cnxk_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *clock);
500 uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev);
501 int cnxk_nix_tm_ops_get(struct rte_eth_dev *eth_dev, void *ops);
502 int cnxk_nix_tm_set_queue_rate_limit(struct rte_eth_dev *eth_dev,
503 uint16_t queue_idx, uint16_t tx_rate);
506 int cnxk_nix_mtr_ops_get(struct rte_eth_dev *dev, void *ops);
509 uint32_t cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
511 int cnxk_nix_reta_update(struct rte_eth_dev *eth_dev,
512 struct rte_eth_rss_reta_entry64 *reta_conf,
514 int cnxk_nix_reta_query(struct rte_eth_dev *eth_dev,
515 struct rte_eth_rss_reta_entry64 *reta_conf,
517 int cnxk_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
518 struct rte_eth_rss_conf *rss_conf);
519 int cnxk_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
520 struct rte_eth_rss_conf *rss_conf);
523 void cnxk_nix_toggle_flag_link_cfg(struct cnxk_eth_dev *dev, bool set);
524 void cnxk_eth_dev_link_status_cb(struct roc_nix *nix,
525 struct roc_nix_link_info *link);
526 void cnxk_eth_dev_link_status_get_cb(struct roc_nix *nix,
527 struct roc_nix_link_info *link);
528 int cnxk_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
529 int cnxk_nix_queue_stats_mapping(struct rte_eth_dev *dev, uint16_t queue_id,
530 uint8_t stat_idx, uint8_t is_rx);
531 int cnxk_nix_stats_reset(struct rte_eth_dev *dev);
532 int cnxk_nix_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
533 int cnxk_nix_xstats_get(struct rte_eth_dev *eth_dev,
534 struct rte_eth_xstat *xstats, unsigned int n);
535 int cnxk_nix_xstats_get_names(struct rte_eth_dev *eth_dev,
536 struct rte_eth_xstat_name *xstats_names,
538 int cnxk_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,
540 struct rte_eth_xstat_name *xstats_names,
542 int cnxk_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids,
543 uint64_t *values, unsigned int n);
544 int cnxk_nix_xstats_reset(struct rte_eth_dev *eth_dev);
545 int cnxk_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
547 void cnxk_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid,
548 struct rte_eth_rxq_info *qinfo);
549 void cnxk_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid,
550 struct rte_eth_txq_info *qinfo);
552 /* Lookup configuration */
553 const uint32_t *cnxk_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev);
554 void *cnxk_nix_fastpath_lookup_mem_get(void);
557 int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs,
558 struct cnxk_eth_dev *dev);
561 int cnxk_nix_dev_get_reg(struct rte_eth_dev *eth_dev,
562 struct rte_dev_reg_info *regs);
564 int cnxk_eth_outb_sa_idx_get(struct cnxk_eth_dev *dev, uint32_t *idx_p);
565 int cnxk_eth_outb_sa_idx_put(struct cnxk_eth_dev *dev, uint32_t idx);
566 int cnxk_nix_lookup_mem_sa_base_set(struct cnxk_eth_dev *dev);
567 int cnxk_nix_lookup_mem_sa_base_clear(struct cnxk_eth_dev *dev);
569 int cnxk_nix_inb_mode_set(struct cnxk_eth_dev *dev, bool use_inl_dev);
570 struct cnxk_eth_sec_sess *cnxk_eth_sec_sess_get_by_spi(struct cnxk_eth_dev *dev,
571 uint32_t spi, bool inb);
572 struct cnxk_eth_sec_sess *
573 cnxk_eth_sec_sess_get_by_sess(struct cnxk_eth_dev *dev,
574 struct rte_security_session *sess);
576 /* Other private functions */
577 int nix_recalc_mtu(struct rte_eth_dev *eth_dev);
580 static __rte_always_inline uint64_t
581 cnxk_pktmbuf_detach(struct rte_mbuf *m)
583 struct rte_mempool *mp = m->pool;
584 uint32_t mbuf_size, buf_len;
589 /* Update refcount of direct mbuf */
590 md = rte_mbuf_from_indirect(m);
591 refcount = rte_mbuf_refcnt_update(md, -1);
593 priv_size = rte_pktmbuf_priv_size(mp);
594 mbuf_size = (uint32_t)(sizeof(struct rte_mbuf) + priv_size);
595 buf_len = rte_pktmbuf_data_room_size(mp);
597 m->priv_size = priv_size;
598 m->buf_addr = (char *)m + mbuf_size;
599 m->buf_iova = rte_mempool_virt2iova(m) + mbuf_size;
600 m->buf_len = (uint16_t)buf_len;
601 rte_pktmbuf_reset_headroom(m);
607 /* Now indirect mbuf is safe to free */
611 rte_mbuf_refcnt_set(md, 1);
622 static __rte_always_inline uint64_t
623 cnxk_nix_prefree_seg(struct rte_mbuf *m)
625 if (likely(rte_mbuf_refcnt_read(m) == 1)) {
626 if (!RTE_MBUF_DIRECT(m))
627 return cnxk_pktmbuf_detach(m);
632 } else if (rte_mbuf_refcnt_update(m, -1) == 0) {
633 if (!RTE_MBUF_DIRECT(m))
634 return cnxk_pktmbuf_detach(m);
636 rte_mbuf_refcnt_set(m, 1);
642 /* Mbuf is having refcount more than 1 so need not to be freed */
646 static inline rte_mbuf_timestamp_t *
647 cnxk_nix_timestamp_dynfield(struct rte_mbuf *mbuf,
648 struct cnxk_timesync_info *info)
650 return RTE_MBUF_DYNFIELD(mbuf, info->tstamp_dynfield_offset,
651 rte_mbuf_timestamp_t *);
654 static __rte_always_inline void
655 cnxk_nix_mbuf_to_tstamp(struct rte_mbuf *mbuf,
656 struct cnxk_timesync_info *tstamp,
657 const uint8_t ts_enable, const uint8_t mseg_enable,
658 uint64_t *tstamp_ptr)
662 mbuf->pkt_len -= CNXK_NIX_TIMESYNC_RX_OFFSET;
663 mbuf->data_len -= CNXK_NIX_TIMESYNC_RX_OFFSET;
666 /* Reading the rx timestamp inserted by CGX, viz at
667 * starting of the packet data.
669 *cnxk_nix_timestamp_dynfield(mbuf, tstamp) =
670 rte_be_to_cpu_64(*tstamp_ptr);
671 /* PKT_RX_IEEE1588_TMST flag needs to be set only in case
672 * PTP packets are received.
674 if (mbuf->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC) {
676 *cnxk_nix_timestamp_dynfield(mbuf, tstamp);
677 tstamp->rx_ready = 1;
678 mbuf->ol_flags |= PKT_RX_IEEE1588_PTP |
679 PKT_RX_IEEE1588_TMST |
680 tstamp->rx_tstamp_dynflag;
685 static __rte_always_inline uintptr_t
686 cnxk_nix_sa_base_get(uint16_t port, const void *lookup_mem)
688 uintptr_t sa_base_tbl;
690 sa_base_tbl = (uintptr_t)lookup_mem;
691 sa_base_tbl += PTYPE_ARRAY_SZ + ERR_ARRAY_SZ;
692 return *((const uintptr_t *)sa_base_tbl + port);
695 #endif /* __CNXK_ETHDEV_H__ */