drivers/net/cnxk/cnxk_ethdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4 #ifndef __CNXK_ETHDEV_H__
   5 #define __CNXK_ETHDEV_H__
   6
   7 #include <math.h>
   8 #include <stdint.h>
   9
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_kvargs.h>
  13 #include <rte_mbuf.h>
  14 #include <rte_mbuf_pool_ops.h>
  15 #include <rte_mempool.h>
  16 #include <rte_time.h>
  17
  18 #include "roc_api.h"
  19
  20 #define CNXK_ETH_DEV_PMD_VERSION "1.0"
  21
  22 /* Used for struct cnxk_eth_dev::flags */
  23 #define CNXK_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
  24
  25 /* VLAN tag inserted by NIX_TX_VTAG_ACTION.
  26  * In Tx space is always reserved for this in FRS.
  27  */
  28 #define CNXK_NIX_MAX_VTAG_INS      2
  29 #define CNXK_NIX_MAX_VTAG_ACT_SIZE (4 * CNXK_NIX_MAX_VTAG_INS)
  30
  31 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
  32 #define CNXK_NIX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + \
  33                               RTE_ETHER_CRC_LEN + \
  34                               CNXK_NIX_MAX_VTAG_ACT_SIZE)
  35
  36 #define CNXK_NIX_RX_MIN_DESC        16
  37 #define CNXK_NIX_RX_MIN_DESC_ALIGN  16
  38 #define CNXK_NIX_RX_NB_SEG_MAX      6
  39 #define CNXK_NIX_RX_DEFAULT_RING_SZ 4096
  40 /* Max supported SQB count */
  41 #define CNXK_NIX_TX_MAX_SQB 512
  42
  43 /* If PTP is enabled additional SEND MEM DESC is required which
  44  * takes 2 words, hence max 7 iova address are possible
  45  */
  46 #if defined(RTE_LIBRTE_IEEE1588)
  47 #define CNXK_NIX_TX_NB_SEG_MAX 7
  48 #else
  49 #define CNXK_NIX_TX_NB_SEG_MAX 9
  50 #endif
  51
  52 #define CNXK_NIX_TX_MSEG_SG_DWORDS                                             \
  53         ((RTE_ALIGN_MUL_CEIL(CNXK_NIX_TX_NB_SEG_MAX, 3) / 3) +                 \
  54          CNXK_NIX_TX_NB_SEG_MAX)
  55
  56 #define CNXK_NIX_RSS_L3_L4_SRC_DST                                             \
  57         (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | ETH_RSS_L4_SRC_ONLY |     \
  58          ETH_RSS_L4_DST_ONLY)
  59
  60 #define CNXK_NIX_RSS_OFFLOAD                                                   \
  61         (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP |               \
  62          ETH_RSS_SCTP | ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD |                  \
  63          CNXK_NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | ETH_RSS_C_VLAN)
  64
  65 #define CNXK_NIX_TX_OFFLOAD_CAPA                                               \
  66         (DEV_TX_OFFLOAD_MBUF_FAST_FREE | DEV_TX_OFFLOAD_MT_LOCKFREE |          \
  67          DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT |             \
  68          DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_TX_OFFLOAD_OUTER_UDP_CKSUM |    \
  69          DEV_TX_OFFLOAD_TCP_CKSUM | DEV_TX_OFFLOAD_UDP_CKSUM |                 \
  70          DEV_TX_OFFLOAD_SCTP_CKSUM | DEV_TX_OFFLOAD_TCP_TSO |                  \
  71          DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GENEVE_TNL_TSO |        \
  72          DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_MULTI_SEGS |              \
  73          DEV_TX_OFFLOAD_IPV4_CKSUM)
  74
  75 #define CNXK_NIX_RX_OFFLOAD_CAPA                                               \
  76         (DEV_RX_OFFLOAD_CHECKSUM | DEV_RX_OFFLOAD_SCTP_CKSUM |                 \
  77          DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_SCATTER |            \
  78          DEV_RX_OFFLOAD_JUMBO_FRAME | DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |         \
  79          DEV_RX_OFFLOAD_RSS_HASH | DEV_RX_OFFLOAD_TIMESTAMP |                  \
  80          DEV_RX_OFFLOAD_VLAN_STRIP)
  81
  82 #define RSS_IPV4_ENABLE                                                        \
  83         (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_UDP |         \
  84          ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_SCTP)
  85
  86 #define RSS_IPV6_ENABLE                                                        \
  87         (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_UDP |         \
  88          ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_NONFRAG_IPV6_SCTP)
  89
  90 #define RSS_IPV6_EX_ENABLE                                                     \
  91         (ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | ETH_RSS_IPV6_UDP_EX)
  92
  93 #define RSS_MAX_LEVELS 3
  94
  95 #define RSS_IPV4_INDEX 0
  96 #define RSS_IPV6_INDEX 1
  97 #define RSS_TCP_INDEX  2
  98 #define RSS_UDP_INDEX  3
  99 #define RSS_SCTP_INDEX 4
 100 #define RSS_DMAC_INDEX 5
 101
 102 /* Default mark value used when none is provided. */
 103 #define CNXK_FLOW_ACTION_FLAG_DEFAULT 0xffff
 104
 105 /* Default cycle counter mask */
 106 #define CNXK_CYCLECOUNTER_MASK     0xffffffffffffffffULL
 107 #define CNXK_NIX_TIMESYNC_RX_OFFSET 8
 108
 109 #define PTYPE_NON_TUNNEL_WIDTH    16
 110 #define PTYPE_TUNNEL_WIDTH        12
 111 #define PTYPE_NON_TUNNEL_ARRAY_SZ BIT(PTYPE_NON_TUNNEL_WIDTH)
 112 #define PTYPE_TUNNEL_ARRAY_SZ     BIT(PTYPE_TUNNEL_WIDTH)
 113 #define PTYPE_ARRAY_SZ                                                         \
 114         ((PTYPE_NON_TUNNEL_ARRAY_SZ + PTYPE_TUNNEL_ARRAY_SZ) * sizeof(uint16_t))
 115 /* Fastpath lookup */
 116 #define CNXK_NIX_FASTPATH_LOOKUP_MEM "cnxk_nix_fastpath_lookup_mem"
 117
 118 #define CNXK_NIX_UDP_TUN_BITMASK                                               \
 119         ((1ull << (PKT_TX_TUNNEL_VXLAN >> 45)) |                               \
 120          (1ull << (PKT_TX_TUNNEL_GENEVE >> 45)))
 121
 122 struct cnxk_fc_cfg {
 123         enum rte_eth_fc_mode mode;
 124         uint8_t rx_pause;
 125         uint8_t tx_pause;
 126 };
 127
 128 struct cnxk_eth_qconf {
 129         union {
 130                 struct rte_eth_txconf tx;
 131                 struct rte_eth_rxconf rx;
 132         } conf;
 133         struct rte_mempool *mp;
 134         uint16_t nb_desc;
 135         uint8_t valid;
 136 };
 137
 138 struct cnxk_timesync_info {
 139         uint64_t rx_tstamp_dynflag;
 140         rte_iova_t tx_tstamp_iova;
 141         uint64_t *tx_tstamp;
 142         uint64_t rx_tstamp;
 143         int tstamp_dynfield_offset;
 144         uint8_t tx_ready;
 145         uint8_t rx_ready;
 146 } __plt_cache_aligned;
 147
 148 struct cnxk_eth_dev {
 149         /* ROC NIX */
 150         struct roc_nix nix;
 151
 152         /* ROC NPC */
 153         struct roc_npc npc;
 154
 155         /* ROC RQs, SQs and CQs */
 156         struct roc_nix_rq *rqs;
 157         struct roc_nix_sq *sqs;
 158         struct roc_nix_cq *cqs;
 159
 160         /* Configured queue count */
 161         uint16_t nb_rxq;
 162         uint16_t nb_txq;
 163         uint8_t configured;
 164
 165         /* Max macfilter entries */
 166         uint8_t dmac_filter_count;
 167         uint8_t max_mac_entries;
 168         bool dmac_filter_enable;
 169
 170         uint16_t flags;
 171         uint8_t ptype_disable;
 172         bool scalar_ena;
 173         bool ptp_en;
 174
 175         /* Pointer back to rte */
 176         struct rte_eth_dev *eth_dev;
 177
 178         /* HW capabilities / Limitations */
 179         union {
 180                 struct {
 181                         uint64_t cq_min_4k : 1;
 182                 };
 183                 uint64_t hwcap;
 184         };
 185
 186         /* Rx and Tx offload capabilities */
 187         uint64_t rx_offload_capa;
 188         uint64_t tx_offload_capa;
 189         uint32_t speed_capa;
 190         /* Configured Rx and Tx offloads */
 191         uint64_t rx_offloads;
 192         uint64_t tx_offloads;
 193         /* Platform specific offload flags */
 194         uint16_t rx_offload_flags;
 195         uint16_t tx_offload_flags;
 196
 197         /* ETHDEV RSS HF bitmask */
 198         uint64_t ethdev_rss_hf;
 199
 200         /* Saved qconf before lf realloc */
 201         struct cnxk_eth_qconf *tx_qconf;
 202         struct cnxk_eth_qconf *rx_qconf;
 203
 204         /* Flow control configuration */
 205         struct cnxk_fc_cfg fc_cfg;
 206
 207         /* PTP Counters */
 208         struct cnxk_timesync_info tstamp;
 209         struct rte_timecounter systime_tc;
 210         struct rte_timecounter rx_tstamp_tc;
 211         struct rte_timecounter tx_tstamp_tc;
 212         double clk_freq_mult;
 213         uint64_t clk_delta;
 214
 215         /* Rx burst for cleanup(Only Primary) */
 216         eth_rx_burst_t rx_pkt_burst_no_offload;
 217
 218         /* Default mac address */
 219         uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
 220
 221         /* LSO Tunnel format indices */
 222         uint64_t lso_tun_fmt;
 223
 224         /* Per queue statistics counters */
 225         uint32_t txq_stat_map[RTE_ETHDEV_QUEUE_STAT_CNTRS];
 226         uint32_t rxq_stat_map[RTE_ETHDEV_QUEUE_STAT_CNTRS];
 227 };
 228
 229 struct cnxk_eth_rxq_sp {
 230         struct cnxk_eth_dev *dev;
 231         struct cnxk_eth_qconf qconf;
 232         uint16_t qid;
 233 } __plt_cache_aligned;
 234
 235 struct cnxk_eth_txq_sp {
 236         struct cnxk_eth_dev *dev;
 237         struct cnxk_eth_qconf qconf;
 238         uint16_t qid;
 239 } __plt_cache_aligned;
 240
 241 static inline struct cnxk_eth_dev *
 242 cnxk_eth_pmd_priv(struct rte_eth_dev *eth_dev)
 243 {
 244         return eth_dev->data->dev_private;
 245 }
 246
 247 static inline struct cnxk_eth_rxq_sp *
 248 cnxk_eth_rxq_to_sp(void *__rxq)
 249 {
 250         return ((struct cnxk_eth_rxq_sp *)__rxq) - 1;
 251 }
 252
 253 static inline struct cnxk_eth_txq_sp *
 254 cnxk_eth_txq_to_sp(void *__txq)
 255 {
 256         return ((struct cnxk_eth_txq_sp *)__txq) - 1;
 257 }
 258
 259 /* Common ethdev ops */
 260 extern struct eth_dev_ops cnxk_eth_dev_ops;
 261
 262 /* Common flow ops */
 263 extern struct rte_flow_ops cnxk_flow_ops;
 264
 265 /* Ops */
 266 int cnxk_nix_probe(struct rte_pci_driver *pci_drv,
 267                    struct rte_pci_device *pci_dev);
 268 int cnxk_nix_remove(struct rte_pci_device *pci_dev);
 269 int cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
 270 int cnxk_nix_mc_addr_list_configure(struct rte_eth_dev *eth_dev,
 271                                     struct rte_ether_addr *mc_addr_set,
 272                                     uint32_t nb_mc_addr);
 273 int cnxk_nix_mac_addr_add(struct rte_eth_dev *eth_dev,
 274                           struct rte_ether_addr *addr, uint32_t index,
 275                           uint32_t pool);
 276 void cnxk_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index);
 277 int cnxk_nix_mac_addr_set(struct rte_eth_dev *eth_dev,
 278                           struct rte_ether_addr *addr);
 279 int cnxk_nix_promisc_enable(struct rte_eth_dev *eth_dev);
 280 int cnxk_nix_promisc_disable(struct rte_eth_dev *eth_dev);
 281 int cnxk_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);
 282 int cnxk_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);
 283 int cnxk_nix_info_get(struct rte_eth_dev *eth_dev,
 284                       struct rte_eth_dev_info *dev_info);
 285 int cnxk_nix_rx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
 286                                struct rte_eth_burst_mode *mode);
 287 int cnxk_nix_tx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
 288                                struct rte_eth_burst_mode *mode);
 289 int cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
 290                            struct rte_eth_fc_conf *fc_conf);
 291 int cnxk_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
 292                            struct rte_eth_fc_conf *fc_conf);
 293 int cnxk_nix_set_link_up(struct rte_eth_dev *eth_dev);
 294 int cnxk_nix_set_link_down(struct rte_eth_dev *eth_dev);
 295 int cnxk_nix_get_module_info(struct rte_eth_dev *eth_dev,
 296                              struct rte_eth_dev_module_info *modinfo);
 297 int cnxk_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
 298                                struct rte_dev_eeprom_info *info);
 299 int cnxk_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
 300                                   uint16_t rx_queue_id);
 301 int cnxk_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
 302                                    uint16_t rx_queue_id);
 303 int cnxk_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool);
 304 int cnxk_nix_tx_done_cleanup(void *txq, uint32_t free_cnt);
 305 int cnxk_nix_flow_ops_get(struct rte_eth_dev *eth_dev,
 306                           const struct rte_flow_ops **ops);
 307 int cnxk_nix_configure(struct rte_eth_dev *eth_dev);
 308 int cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 309                             uint16_t nb_desc, uint16_t fp_tx_q_sz,
 310                             const struct rte_eth_txconf *tx_conf);
 311 int cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 312                             uint16_t nb_desc, uint16_t fp_rx_q_sz,
 313                             const struct rte_eth_rxconf *rx_conf,
 314                             struct rte_mempool *mp);
 315 int cnxk_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid);
 316 int cnxk_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid);
 317 int cnxk_nix_dev_start(struct rte_eth_dev *eth_dev);
 318 int cnxk_nix_timesync_enable(struct rte_eth_dev *eth_dev);
 319 int cnxk_nix_timesync_disable(struct rte_eth_dev *eth_dev);
 320 int cnxk_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev,
 321                                         struct timespec *timestamp,
 322                                         uint32_t flags);
 323 int cnxk_nix_timesync_read_tx_timestamp(struct rte_eth_dev *eth_dev,
 324                                         struct timespec *timestamp);
 325 int cnxk_nix_timesync_read_time(struct rte_eth_dev *eth_dev,
 326                                 struct timespec *ts);
 327 int cnxk_nix_timesync_write_time(struct rte_eth_dev *eth_dev,
 328                                  const struct timespec *ts);
 329 int cnxk_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta);
 330 int cnxk_nix_tsc_convert(struct cnxk_eth_dev *dev);
 331 int cnxk_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *clock);
 332
 333 uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev);
 334
 335 /* RSS */
 336 uint32_t cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
 337                                 uint8_t rss_level);
 338 int cnxk_nix_reta_update(struct rte_eth_dev *eth_dev,
 339                          struct rte_eth_rss_reta_entry64 *reta_conf,
 340                          uint16_t reta_size);
 341 int cnxk_nix_reta_query(struct rte_eth_dev *eth_dev,
 342                         struct rte_eth_rss_reta_entry64 *reta_conf,
 343                         uint16_t reta_size);
 344 int cnxk_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
 345                              struct rte_eth_rss_conf *rss_conf);
 346 int cnxk_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
 347                                struct rte_eth_rss_conf *rss_conf);
 348
 349 /* Link */
 350 void cnxk_nix_toggle_flag_link_cfg(struct cnxk_eth_dev *dev, bool set);
 351 void cnxk_eth_dev_link_status_cb(struct roc_nix *nix,
 352                                  struct roc_nix_link_info *link);
 353 int cnxk_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
 354 int cnxk_nix_queue_stats_mapping(struct rte_eth_dev *dev, uint16_t queue_id,
 355                                  uint8_t stat_idx, uint8_t is_rx);
 356 int cnxk_nix_stats_reset(struct rte_eth_dev *dev);
 357 int cnxk_nix_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 358 int cnxk_nix_xstats_get(struct rte_eth_dev *eth_dev,
 359                         struct rte_eth_xstat *xstats, unsigned int n);
 360 int cnxk_nix_xstats_get_names(struct rte_eth_dev *eth_dev,
 361                               struct rte_eth_xstat_name *xstats_names,
 362                               unsigned int limit);
 363 int cnxk_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,
 364                                     struct rte_eth_xstat_name *xstats_names,
 365                                     const uint64_t *ids, unsigned int limit);
 366 int cnxk_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids,
 367                               uint64_t *values, unsigned int n);
 368 int cnxk_nix_xstats_reset(struct rte_eth_dev *eth_dev);
 369 int cnxk_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
 370                             size_t fw_size);
 371 void cnxk_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid,
 372                            struct rte_eth_rxq_info *qinfo);
 373 void cnxk_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid,
 374                            struct rte_eth_txq_info *qinfo);
 375
 376 /* Lookup configuration */
 377 const uint32_t *cnxk_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev);
 378 void *cnxk_nix_fastpath_lookup_mem_get(void);
 379
 380 /* Devargs */
 381 int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs,
 382                               struct cnxk_eth_dev *dev);
 383
 384 /* Debug */
 385 int cnxk_nix_dev_get_reg(struct rte_eth_dev *eth_dev,
 386                          struct rte_dev_reg_info *regs);
 387
 388 /* Other private functions */
 389 int nix_recalc_mtu(struct rte_eth_dev *eth_dev);
 390
 391 /* Inlines */
 392 static __rte_always_inline uint64_t
 393 cnxk_pktmbuf_detach(struct rte_mbuf *m)
 394 {
 395         struct rte_mempool *mp = m->pool;
 396         uint32_t mbuf_size, buf_len;
 397         struct rte_mbuf *md;
 398         uint16_t priv_size;
 399         uint16_t refcount;
 400
 401         /* Update refcount of direct mbuf */
 402         md = rte_mbuf_from_indirect(m);
 403         refcount = rte_mbuf_refcnt_update(md, -1);
 404
 405         priv_size = rte_pktmbuf_priv_size(mp);
 406         mbuf_size = (uint32_t)(sizeof(struct rte_mbuf) + priv_size);
 407         buf_len = rte_pktmbuf_data_room_size(mp);
 408
 409         m->priv_size = priv_size;
 410         m->buf_addr = (char *)m + mbuf_size;
 411         m->buf_iova = rte_mempool_virt2iova(m) + mbuf_size;
 412         m->buf_len = (uint16_t)buf_len;
 413         rte_pktmbuf_reset_headroom(m);
 414         m->data_len = 0;
 415         m->ol_flags = 0;
 416         m->next = NULL;
 417         m->nb_segs = 1;
 418
 419         /* Now indirect mbuf is safe to free */
 420         rte_pktmbuf_free(m);
 421
 422         if (refcount == 0) {
 423                 rte_mbuf_refcnt_set(md, 1);
 424                 md->data_len = 0;
 425                 md->ol_flags = 0;
 426                 md->next = NULL;
 427                 md->nb_segs = 1;
 428                 return 0;
 429         } else {
 430                 return 1;
 431         }
 432 }
 433
 434 static __rte_always_inline uint64_t
 435 cnxk_nix_prefree_seg(struct rte_mbuf *m)
 436 {
 437         if (likely(rte_mbuf_refcnt_read(m) == 1)) {
 438                 if (!RTE_MBUF_DIRECT(m))
 439                         return cnxk_pktmbuf_detach(m);
 440
 441                 m->next = NULL;
 442                 m->nb_segs = 1;
 443                 return 0;
 444         } else if (rte_mbuf_refcnt_update(m, -1) == 0) {
 445                 if (!RTE_MBUF_DIRECT(m))
 446                         return cnxk_pktmbuf_detach(m);
 447
 448                 rte_mbuf_refcnt_set(m, 1);
 449                 m->next = NULL;
 450                 m->nb_segs = 1;
 451                 return 0;
 452         }
 453
 454         /* Mbuf is having refcount more than 1 so need not to be freed */
 455         return 1;
 456 }
 457
 458 static inline rte_mbuf_timestamp_t *
 459 cnxk_nix_timestamp_dynfield(struct rte_mbuf *mbuf,
 460                             struct cnxk_timesync_info *info)
 461 {
 462         return RTE_MBUF_DYNFIELD(mbuf, info->tstamp_dynfield_offset,
 463                                  rte_mbuf_timestamp_t *);
 464 }
 465
 466 static __rte_always_inline void
 467 cnxk_nix_mbuf_to_tstamp(struct rte_mbuf *mbuf,
 468                         struct cnxk_timesync_info *tstamp, bool ts_enable,
 469                         uint64_t *tstamp_ptr)
 470 {
 471         if (ts_enable &&
 472             (mbuf->data_off ==
 473              RTE_PKTMBUF_HEADROOM + CNXK_NIX_TIMESYNC_RX_OFFSET)) {
 474                 mbuf->pkt_len -= CNXK_NIX_TIMESYNC_RX_OFFSET;
 475
 476                 /* Reading the rx timestamp inserted by CGX, viz at
 477                  * starting of the packet data.
 478                  */
 479                 *cnxk_nix_timestamp_dynfield(mbuf, tstamp) =
 480                         rte_be_to_cpu_64(*tstamp_ptr);
 481                 /* PKT_RX_IEEE1588_TMST flag needs to be set only in case
 482                  * PTP packets are received.
 483                  */
 484                 if (mbuf->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC) {
 485                         tstamp->rx_tstamp =
 486                                 *cnxk_nix_timestamp_dynfield(mbuf, tstamp);
 487                         tstamp->rx_ready = 1;
 488                         mbuf->ol_flags |= PKT_RX_IEEE1588_PTP |
 489                                           PKT_RX_IEEE1588_TMST |
 490                                           tstamp->rx_tstamp_dynflag;
 491                 }
 492         }
 493 }
 494
 495 #endif /* __CNXK_ETHDEV_H__ */