drivers/net/cnxk/cnxk_ethdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4 #ifndef __CNXK_ETHDEV_H__
   5 #define __CNXK_ETHDEV_H__
   6
   7 #include <math.h>
   8 #include <stdint.h>
   9
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_kvargs.h>
  13
  14 #include "roc_api.h"
  15
  16 #define CNXK_ETH_DEV_PMD_VERSION "1.0"
  17
  18 /* VLAN tag inserted by NIX_TX_VTAG_ACTION.
  19  * In Tx space is always reserved for this in FRS.
  20  */
  21 #define CNXK_NIX_MAX_VTAG_INS      2
  22 #define CNXK_NIX_MAX_VTAG_ACT_SIZE (4 * CNXK_NIX_MAX_VTAG_INS)
  23
  24 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
  25 #define CNXK_NIX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8)
  26
  27 #define CNXK_NIX_RX_MIN_DESC        16
  28 #define CNXK_NIX_RX_MIN_DESC_ALIGN  16
  29 #define CNXK_NIX_RX_NB_SEG_MAX      6
  30 #define CNXK_NIX_RX_DEFAULT_RING_SZ 4096
  31 /* Max supported SQB count */
  32 #define CNXK_NIX_TX_MAX_SQB 512
  33
  34 /* If PTP is enabled additional SEND MEM DESC is required which
  35  * takes 2 words, hence max 7 iova address are possible
  36  */
  37 #if defined(RTE_LIBRTE_IEEE1588)
  38 #define CNXK_NIX_TX_NB_SEG_MAX 7
  39 #else
  40 #define CNXK_NIX_TX_NB_SEG_MAX 9
  41 #endif
  42
  43 #define CNXK_NIX_RSS_L3_L4_SRC_DST                                             \
  44         (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | ETH_RSS_L4_SRC_ONLY |     \
  45          ETH_RSS_L4_DST_ONLY)
  46
  47 #define CNXK_NIX_RSS_OFFLOAD                                                   \
  48         (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP |               \
  49          ETH_RSS_SCTP | ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD |                  \
  50          CNXK_NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | ETH_RSS_C_VLAN)
  51
  52 #define CNXK_NIX_TX_OFFLOAD_CAPA                                               \
  53         (DEV_TX_OFFLOAD_MBUF_FAST_FREE | DEV_TX_OFFLOAD_MT_LOCKFREE |          \
  54          DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT |             \
  55          DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_TX_OFFLOAD_OUTER_UDP_CKSUM |    \
  56          DEV_TX_OFFLOAD_TCP_CKSUM | DEV_TX_OFFLOAD_UDP_CKSUM |                 \
  57          DEV_TX_OFFLOAD_SCTP_CKSUM | DEV_TX_OFFLOAD_TCP_TSO |                  \
  58          DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GENEVE_TNL_TSO |        \
  59          DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_MULTI_SEGS |              \
  60          DEV_TX_OFFLOAD_IPV4_CKSUM)
  61
  62 #define CNXK_NIX_RX_OFFLOAD_CAPA                                               \
  63         (DEV_RX_OFFLOAD_CHECKSUM | DEV_RX_OFFLOAD_SCTP_CKSUM |                 \
  64          DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_SCATTER |            \
  65          DEV_RX_OFFLOAD_JUMBO_FRAME | DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |         \
  66          DEV_RX_OFFLOAD_RSS_HASH)
  67
  68 struct cnxk_eth_dev {
  69         /* ROC NIX */
  70         struct roc_nix nix;
  71
  72         /* Max macfilter entries */
  73         uint8_t max_mac_entries;
  74
  75         uint16_t flags;
  76         bool scalar_ena;
  77
  78         /* Pointer back to rte */
  79         struct rte_eth_dev *eth_dev;
  80
  81         /* HW capabilities / Limitations */
  82         union {
  83                 struct {
  84                         uint64_t cq_min_4k : 1;
  85                 };
  86                 uint64_t hwcap;
  87         };
  88
  89         /* Rx and Tx offload capabilities */
  90         uint64_t rx_offload_capa;
  91         uint64_t tx_offload_capa;
  92         uint32_t speed_capa;
  93
  94         /* Default mac address */
  95         uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
  96 };
  97
  98 static inline struct cnxk_eth_dev *
  99 cnxk_eth_pmd_priv(struct rte_eth_dev *eth_dev)
 100 {
 101         return eth_dev->data->dev_private;
 102 }
 103
 104 /* Common ethdev ops */
 105 extern struct eth_dev_ops cnxk_eth_dev_ops;
 106
 107 /* Ops */
 108 int cnxk_nix_probe(struct rte_pci_driver *pci_drv,
 109                    struct rte_pci_device *pci_dev);
 110 int cnxk_nix_remove(struct rte_pci_device *pci_dev);
 111 int cnxk_nix_info_get(struct rte_eth_dev *eth_dev,
 112                       struct rte_eth_dev_info *dev_info);
 113
 114 /* Devargs */
 115 int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs,
 116                               struct cnxk_eth_dev *dev);
 117
 118 #endif /* __CNXK_ETHDEV_H__ */