drivers/net/cnxk/cnxk_ethdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4 #ifndef __CNXK_ETHDEV_H__
   5 #define __CNXK_ETHDEV_H__
   6
   7 #include <math.h>
   8 #include <stdint.h>
   9
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_kvargs.h>
  13
  14 #include "roc_api.h"
  15
  16 #define CNXK_ETH_DEV_PMD_VERSION "1.0"
  17
  18 /* Max supported SQB count */
  19 #define CNXK_NIX_TX_MAX_SQB 512
  20
  21 #define CNXK_NIX_TX_OFFLOAD_CAPA                                               \
  22         (DEV_TX_OFFLOAD_MBUF_FAST_FREE | DEV_TX_OFFLOAD_MT_LOCKFREE |          \
  23          DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT |             \
  24          DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_TX_OFFLOAD_OUTER_UDP_CKSUM |    \
  25          DEV_TX_OFFLOAD_TCP_CKSUM | DEV_TX_OFFLOAD_UDP_CKSUM |                 \
  26          DEV_TX_OFFLOAD_SCTP_CKSUM | DEV_TX_OFFLOAD_TCP_TSO |                  \
  27          DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GENEVE_TNL_TSO |        \
  28          DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_MULTI_SEGS |              \
  29          DEV_TX_OFFLOAD_IPV4_CKSUM)
  30
  31 #define CNXK_NIX_RX_OFFLOAD_CAPA                                               \
  32         (DEV_RX_OFFLOAD_CHECKSUM | DEV_RX_OFFLOAD_SCTP_CKSUM |                 \
  33          DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_SCATTER |            \
  34          DEV_RX_OFFLOAD_JUMBO_FRAME | DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |         \
  35          DEV_RX_OFFLOAD_RSS_HASH)
  36
  37 struct cnxk_eth_dev {
  38         /* ROC NIX */
  39         struct roc_nix nix;
  40
  41         /* Max macfilter entries */
  42         uint8_t max_mac_entries;
  43
  44         uint16_t flags;
  45         bool scalar_ena;
  46
  47         /* Pointer back to rte */
  48         struct rte_eth_dev *eth_dev;
  49
  50         /* HW capabilities / Limitations */
  51         union {
  52                 struct {
  53                         uint64_t cq_min_4k : 1;
  54                 };
  55                 uint64_t hwcap;
  56         };
  57
  58         /* Rx and Tx offload capabilities */
  59         uint64_t rx_offload_capa;
  60         uint64_t tx_offload_capa;
  61         uint32_t speed_capa;
  62
  63         /* Default mac address */
  64         uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
  65 };
  66
  67 static inline struct cnxk_eth_dev *
  68 cnxk_eth_pmd_priv(struct rte_eth_dev *eth_dev)
  69 {
  70         return eth_dev->data->dev_private;
  71 }
  72
  73 /* Common ethdev ops */
  74 extern struct eth_dev_ops cnxk_eth_dev_ops;
  75
  76 /* Ops */
  77 int cnxk_nix_probe(struct rte_pci_driver *pci_drv,
  78                    struct rte_pci_device *pci_dev);
  79 int cnxk_nix_remove(struct rte_pci_device *pci_dev);
  80
  81 /* Devargs */
  82 int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs,
  83                               struct cnxk_eth_dev *dev);
  84
  85 #endif /* __CNXK_ETHDEV_H__ */