drivers/net/cnxk/cnxk_ethdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4 #ifndef __CNXK_ETHDEV_H__
   5 #define __CNXK_ETHDEV_H__
   6
   7 #include <math.h>
   8 #include <stdint.h>
   9
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_kvargs.h>
  13 #include <rte_mbuf.h>
  14 #include <rte_mbuf_pool_ops.h>
  15 #include <rte_mempool.h>
  16
  17 #include "roc_api.h"
  18
  19 #define CNXK_ETH_DEV_PMD_VERSION "1.0"
  20
  21 /* Used for struct cnxk_eth_dev::flags */
  22 #define CNXK_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
  23
  24 /* VLAN tag inserted by NIX_TX_VTAG_ACTION.
  25  * In Tx space is always reserved for this in FRS.
  26  */
  27 #define CNXK_NIX_MAX_VTAG_INS      2
  28 #define CNXK_NIX_MAX_VTAG_ACT_SIZE (4 * CNXK_NIX_MAX_VTAG_INS)
  29
  30 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
  31 #define CNXK_NIX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8)
  32
  33 #define CNXK_NIX_RX_MIN_DESC        16
  34 #define CNXK_NIX_RX_MIN_DESC_ALIGN  16
  35 #define CNXK_NIX_RX_NB_SEG_MAX      6
  36 #define CNXK_NIX_RX_DEFAULT_RING_SZ 4096
  37 /* Max supported SQB count */
  38 #define CNXK_NIX_TX_MAX_SQB 512
  39
  40 /* If PTP is enabled additional SEND MEM DESC is required which
  41  * takes 2 words, hence max 7 iova address are possible
  42  */
  43 #if defined(RTE_LIBRTE_IEEE1588)
  44 #define CNXK_NIX_TX_NB_SEG_MAX 7
  45 #else
  46 #define CNXK_NIX_TX_NB_SEG_MAX 9
  47 #endif
  48
  49 #define CNXK_NIX_RSS_L3_L4_SRC_DST                                             \
  50         (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | ETH_RSS_L4_SRC_ONLY |     \
  51          ETH_RSS_L4_DST_ONLY)
  52
  53 #define CNXK_NIX_RSS_OFFLOAD                                                   \
  54         (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP |               \
  55          ETH_RSS_SCTP | ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD |                  \
  56          CNXK_NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | ETH_RSS_C_VLAN)
  57
  58 #define CNXK_NIX_TX_OFFLOAD_CAPA                                               \
  59         (DEV_TX_OFFLOAD_MBUF_FAST_FREE | DEV_TX_OFFLOAD_MT_LOCKFREE |          \
  60          DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT |             \
  61          DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_TX_OFFLOAD_OUTER_UDP_CKSUM |    \
  62          DEV_TX_OFFLOAD_TCP_CKSUM | DEV_TX_OFFLOAD_UDP_CKSUM |                 \
  63          DEV_TX_OFFLOAD_SCTP_CKSUM | DEV_TX_OFFLOAD_TCP_TSO |                  \
  64          DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GENEVE_TNL_TSO |        \
  65          DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_MULTI_SEGS |              \
  66          DEV_TX_OFFLOAD_IPV4_CKSUM)
  67
  68 #define CNXK_NIX_RX_OFFLOAD_CAPA                                               \
  69         (DEV_RX_OFFLOAD_CHECKSUM | DEV_RX_OFFLOAD_SCTP_CKSUM |                 \
  70          DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_SCATTER |            \
  71          DEV_RX_OFFLOAD_JUMBO_FRAME | DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |         \
  72          DEV_RX_OFFLOAD_RSS_HASH)
  73
  74 #define RSS_IPV4_ENABLE                                                        \
  75         (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_UDP |         \
  76          ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_SCTP)
  77
  78 #define RSS_IPV6_ENABLE                                                        \
  79         (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_UDP |         \
  80          ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_NONFRAG_IPV6_SCTP)
  81
  82 #define RSS_IPV6_EX_ENABLE                                                     \
  83         (ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | ETH_RSS_IPV6_UDP_EX)
  84
  85 #define RSS_MAX_LEVELS 3
  86
  87 #define RSS_IPV4_INDEX 0
  88 #define RSS_IPV6_INDEX 1
  89 #define RSS_TCP_INDEX  2
  90 #define RSS_UDP_INDEX  3
  91 #define RSS_SCTP_INDEX 4
  92 #define RSS_DMAC_INDEX 5
  93
  94 #define PTYPE_NON_TUNNEL_WIDTH    16
  95 #define PTYPE_TUNNEL_WIDTH        12
  96 #define PTYPE_NON_TUNNEL_ARRAY_SZ BIT(PTYPE_NON_TUNNEL_WIDTH)
  97 #define PTYPE_TUNNEL_ARRAY_SZ     BIT(PTYPE_TUNNEL_WIDTH)
  98 #define PTYPE_ARRAY_SZ                                                         \
  99         ((PTYPE_NON_TUNNEL_ARRAY_SZ + PTYPE_TUNNEL_ARRAY_SZ) * sizeof(uint16_t))
 100 /* Fastpath lookup */
 101 #define CNXK_NIX_FASTPATH_LOOKUP_MEM "cnxk_nix_fastpath_lookup_mem"
 102
 103 struct cnxk_eth_qconf {
 104         union {
 105                 struct rte_eth_txconf tx;
 106                 struct rte_eth_rxconf rx;
 107         } conf;
 108         struct rte_mempool *mp;
 109         uint16_t nb_desc;
 110         uint8_t valid;
 111 };
 112
 113 struct cnxk_eth_dev {
 114         /* ROC NIX */
 115         struct roc_nix nix;
 116
 117         /* ROC RQs, SQs and CQs */
 118         struct roc_nix_rq *rqs;
 119         struct roc_nix_sq *sqs;
 120         struct roc_nix_cq *cqs;
 121
 122         /* Configured queue count */
 123         uint16_t nb_rxq;
 124         uint16_t nb_txq;
 125         uint8_t configured;
 126
 127         /* Max macfilter entries */
 128         uint8_t max_mac_entries;
 129
 130         uint16_t flags;
 131         uint8_t ptype_disable;
 132         bool scalar_ena;
 133
 134         /* Pointer back to rte */
 135         struct rte_eth_dev *eth_dev;
 136
 137         /* HW capabilities / Limitations */
 138         union {
 139                 struct {
 140                         uint64_t cq_min_4k : 1;
 141                 };
 142                 uint64_t hwcap;
 143         };
 144
 145         /* Rx and Tx offload capabilities */
 146         uint64_t rx_offload_capa;
 147         uint64_t tx_offload_capa;
 148         uint32_t speed_capa;
 149         /* Configured Rx and Tx offloads */
 150         uint64_t rx_offloads;
 151         uint64_t tx_offloads;
 152         /* Platform specific offload flags */
 153         uint16_t rx_offload_flags;
 154         uint16_t tx_offload_flags;
 155
 156         /* ETHDEV RSS HF bitmask */
 157         uint64_t ethdev_rss_hf;
 158
 159         /* Saved qconf before lf realloc */
 160         struct cnxk_eth_qconf *tx_qconf;
 161         struct cnxk_eth_qconf *rx_qconf;
 162
 163         /* Default mac address */
 164         uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
 165
 166         /* LSO Tunnel format indices */
 167         uint64_t lso_tun_fmt;
 168 };
 169
 170 struct cnxk_eth_rxq_sp {
 171         struct cnxk_eth_dev *dev;
 172         struct cnxk_eth_qconf qconf;
 173         uint16_t qid;
 174 } __plt_cache_aligned;
 175
 176 struct cnxk_eth_txq_sp {
 177         struct cnxk_eth_dev *dev;
 178         struct cnxk_eth_qconf qconf;
 179         uint16_t qid;
 180 } __plt_cache_aligned;
 181
 182 static inline struct cnxk_eth_dev *
 183 cnxk_eth_pmd_priv(struct rte_eth_dev *eth_dev)
 184 {
 185         return eth_dev->data->dev_private;
 186 }
 187
 188 static inline struct cnxk_eth_rxq_sp *
 189 cnxk_eth_rxq_to_sp(void *__rxq)
 190 {
 191         return ((struct cnxk_eth_rxq_sp *)__rxq) - 1;
 192 }
 193
 194 static inline struct cnxk_eth_txq_sp *
 195 cnxk_eth_txq_to_sp(void *__txq)
 196 {
 197         return ((struct cnxk_eth_txq_sp *)__txq) - 1;
 198 }
 199
 200 /* Common ethdev ops */
 201 extern struct eth_dev_ops cnxk_eth_dev_ops;
 202
 203 /* Ops */
 204 int cnxk_nix_probe(struct rte_pci_driver *pci_drv,
 205                    struct rte_pci_device *pci_dev);
 206 int cnxk_nix_remove(struct rte_pci_device *pci_dev);
 207 int cnxk_nix_info_get(struct rte_eth_dev *eth_dev,
 208                       struct rte_eth_dev_info *dev_info);
 209 int cnxk_nix_configure(struct rte_eth_dev *eth_dev);
 210 int cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 211                             uint16_t nb_desc, uint16_t fp_tx_q_sz,
 212                             const struct rte_eth_txconf *tx_conf);
 213 int cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 214                             uint16_t nb_desc, uint16_t fp_rx_q_sz,
 215                             const struct rte_eth_rxconf *rx_conf,
 216                             struct rte_mempool *mp);
 217
 218 uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev);
 219
 220 /* RSS */
 221 uint32_t cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
 222                                 uint8_t rss_level);
 223
 224 /* Link */
 225 void cnxk_eth_dev_link_status_cb(struct roc_nix *nix,
 226                                  struct roc_nix_link_info *link);
 227 int cnxk_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
 228
 229 /* Lookup configuration */
 230 const uint32_t *cnxk_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev);
 231 void *cnxk_nix_fastpath_lookup_mem_get(void);
 232
 233 /* Devargs */
 234 int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs,
 235                               struct cnxk_eth_dev *dev);
 236
 237 #endif /* __CNXK_ETHDEV_H__ */