drivers/net/cnxk/cnxk_ethdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4 #ifndef __CNXK_ETHDEV_H__
   5 #define __CNXK_ETHDEV_H__
   6
   7 #include <math.h>
   8 #include <stdint.h>
   9
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_kvargs.h>
  13 #include <rte_mbuf.h>
  14 #include <rte_mbuf_pool_ops.h>
  15 #include <rte_mempool.h>
  16 #include <rte_mtr_driver.h>
  17 #include <rte_security.h>
  18 #include <rte_security_driver.h>
  19 #include <rte_tailq.h>
  20 #include <rte_time.h>
  21
  22 #include "roc_api.h"
  23
  24 #define CNXK_ETH_DEV_PMD_VERSION "1.0"
  25
  26 /* Used for struct cnxk_eth_dev::flags */
  27 #define CNXK_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
  28
  29 /* VLAN tag inserted by NIX_TX_VTAG_ACTION.
  30  * In Tx space is always reserved for this in FRS.
  31  */
  32 #define CNXK_NIX_MAX_VTAG_INS      2
  33 #define CNXK_NIX_MAX_VTAG_ACT_SIZE (4 * CNXK_NIX_MAX_VTAG_INS)
  34
  35 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
  36 #define CNXK_NIX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + \
  37                               RTE_ETHER_CRC_LEN + \
  38                               CNXK_NIX_MAX_VTAG_ACT_SIZE)
  39
  40 #define CNXK_NIX_RX_MIN_DESC        16
  41 #define CNXK_NIX_RX_MIN_DESC_ALIGN  16
  42 #define CNXK_NIX_RX_NB_SEG_MAX      6
  43 #define CNXK_NIX_RX_DEFAULT_RING_SZ 4096
  44 /* Max supported SQB count */
  45 #define CNXK_NIX_TX_MAX_SQB 512
  46
  47 /* If PTP is enabled additional SEND MEM DESC is required which
  48  * takes 2 words, hence max 7 iova address are possible
  49  */
  50 #if defined(RTE_LIBRTE_IEEE1588)
  51 #define CNXK_NIX_TX_NB_SEG_MAX 7
  52 #else
  53 #define CNXK_NIX_TX_NB_SEG_MAX 9
  54 #endif
  55
  56 #define CNXK_NIX_TX_MSEG_SG_DWORDS                                             \
  57         ((RTE_ALIGN_MUL_CEIL(CNXK_NIX_TX_NB_SEG_MAX, 3) / 3) +                 \
  58          CNXK_NIX_TX_NB_SEG_MAX)
  59
  60 #define CNXK_NIX_RSS_L3_L4_SRC_DST                                             \
  61         (RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY |                   \
  62          RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY)
  63
  64 #define CNXK_NIX_RSS_OFFLOAD                                                   \
  65         (RTE_ETH_RSS_PORT | RTE_ETH_RSS_IP | RTE_ETH_RSS_UDP |                 \
  66          RTE_ETH_RSS_TCP | RTE_ETH_RSS_SCTP | RTE_ETH_RSS_TUNNEL |             \
  67          RTE_ETH_RSS_L2_PAYLOAD | CNXK_NIX_RSS_L3_L4_SRC_DST |                 \
  68          RTE_ETH_RSS_LEVEL_MASK | RTE_ETH_RSS_C_VLAN)
  69
  70 #define CNXK_NIX_TX_OFFLOAD_CAPA                                               \
  71         (RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE | RTE_ETH_TX_OFFLOAD_MT_LOCKFREE |          \
  72          RTE_ETH_TX_OFFLOAD_VLAN_INSERT | RTE_ETH_TX_OFFLOAD_QINQ_INSERT |             \
  73          RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM |    \
  74          RTE_ETH_TX_OFFLOAD_TCP_CKSUM | RTE_ETH_TX_OFFLOAD_UDP_CKSUM |                 \
  75          RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | RTE_ETH_TX_OFFLOAD_TCP_TSO |                  \
  76          RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO | RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |        \
  77          RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO | RTE_ETH_TX_OFFLOAD_MULTI_SEGS |              \
  78          RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | RTE_ETH_TX_OFFLOAD_SECURITY)
  79
  80 #define CNXK_NIX_RX_OFFLOAD_CAPA                                               \
  81         (RTE_ETH_RX_OFFLOAD_CHECKSUM | RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |         \
  82          RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | RTE_ETH_RX_OFFLOAD_SCATTER |    \
  83          RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM | RTE_ETH_RX_OFFLOAD_RSS_HASH |    \
  84          RTE_ETH_RX_OFFLOAD_TIMESTAMP | RTE_ETH_RX_OFFLOAD_VLAN_STRIP |        \
  85          RTE_ETH_RX_OFFLOAD_SECURITY)
  86
  87 #define RSS_IPV4_ENABLE                                                        \
  88         (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 |                            \
  89          RTE_ETH_RSS_NONFRAG_IPV4_UDP | RTE_ETH_RSS_NONFRAG_IPV4_TCP |         \
  90          RTE_ETH_RSS_NONFRAG_IPV4_SCTP)
  91
  92 #define RSS_IPV6_ENABLE                                                        \
  93         (RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 |                            \
  94          RTE_ETH_RSS_NONFRAG_IPV6_UDP | RTE_ETH_RSS_NONFRAG_IPV6_TCP |         \
  95          RTE_ETH_RSS_NONFRAG_IPV6_SCTP)
  96
  97 #define RSS_IPV6_EX_ENABLE                                                     \
  98         (RTE_ETH_RSS_IPV6_EX | RTE_ETH_RSS_IPV6_TCP_EX | RTE_ETH_RSS_IPV6_UDP_EX)
  99
 100 #define RSS_MAX_LEVELS 3
 101
 102 #define RSS_IPV4_INDEX 0
 103 #define RSS_IPV6_INDEX 1
 104 #define RSS_TCP_INDEX  2
 105 #define RSS_UDP_INDEX  3
 106 #define RSS_SCTP_INDEX 4
 107 #define RSS_DMAC_INDEX 5
 108
 109 /* Default mark value used when none is provided. */
 110 #define CNXK_FLOW_ACTION_FLAG_DEFAULT 0xffff
 111
 112 /* Default cycle counter mask */
 113 #define CNXK_CYCLECOUNTER_MASK     0xffffffffffffffffULL
 114 #define CNXK_NIX_TIMESYNC_RX_OFFSET 8
 115
 116 #define PTYPE_NON_TUNNEL_WIDTH    16
 117 #define PTYPE_TUNNEL_WIDTH        12
 118 #define PTYPE_NON_TUNNEL_ARRAY_SZ BIT(PTYPE_NON_TUNNEL_WIDTH)
 119 #define PTYPE_TUNNEL_ARRAY_SZ     BIT(PTYPE_TUNNEL_WIDTH)
 120 #define PTYPE_ARRAY_SZ                                                         \
 121         ((PTYPE_NON_TUNNEL_ARRAY_SZ + PTYPE_TUNNEL_ARRAY_SZ) * sizeof(uint16_t))
 122
 123 /* NIX_RX_PARSE_S's ERRCODE + ERRLEV (12 bits) */
 124 #define ERRCODE_ERRLEN_WIDTH 12
 125 #define ERR_ARRAY_SZ         ((BIT(ERRCODE_ERRLEN_WIDTH)) * sizeof(uint32_t))
 126
 127 /* Fastpath lookup */
 128 #define CNXK_NIX_FASTPATH_LOOKUP_MEM "cnxk_nix_fastpath_lookup_mem"
 129
 130 #define CNXK_NIX_UDP_TUN_BITMASK                                               \
 131         ((1ull << (RTE_MBUF_F_TX_TUNNEL_VXLAN >> 45)) |                               \
 132          (1ull << (RTE_MBUF_F_TX_TUNNEL_GENEVE >> 45)))
 133
 134 /* Subtype from inline outbound error event */
 135 #define CNXK_ETHDEV_SEC_OUTB_EV_SUB 0xFFUL
 136
 137 /* SPI will be in 20 bits of tag */
 138 #define CNXK_ETHDEV_SPI_TAG_MASK 0xFFFFFUL
 139
 140 #define CNXK_NIX_PFC_CHAN_COUNT 16
 141
 142 struct cnxk_fc_cfg {
 143         enum rte_eth_fc_mode mode;
 144         uint8_t rx_pause;
 145         uint8_t tx_pause;
 146 };
 147
 148 struct cnxk_pfc_cfg {
 149         struct cnxk_fc_cfg fc_cfg;
 150         uint16_t class_en;
 151         uint16_t pause_time;
 152         uint8_t rx_tc;
 153         uint8_t rx_qid;
 154         uint8_t tx_tc;
 155         uint8_t tx_qid;
 156 };
 157
 158 struct cnxk_eth_qconf {
 159         union {
 160                 struct rte_eth_txconf tx;
 161                 struct rte_eth_rxconf rx;
 162         } conf;
 163         struct rte_mempool *mp;
 164         uint16_t nb_desc;
 165         uint8_t valid;
 166 };
 167
 168 struct cnxk_timesync_info {
 169         uint8_t rx_ready;
 170         uint64_t rx_tstamp;
 171         uint64_t rx_tstamp_dynflag;
 172         int tstamp_dynfield_offset;
 173         rte_iova_t tx_tstamp_iova;
 174         uint64_t *tx_tstamp;
 175 } __plt_cache_aligned;
 176
 177 struct cnxk_meter_node {
 178 #define MAX_PRV_MTR_NODES 10
 179         TAILQ_ENTRY(cnxk_meter_node) next;
 180         /**< Pointer to the next flow meter structure. */
 181         uint32_t id; /**< Usr mtr id. */
 182         struct cnxk_mtr_profile_node *profile;
 183         struct cnxk_mtr_policy_node *policy;
 184         uint32_t bpf_id; /**< Hw mtr id. */
 185         uint32_t rq_num;
 186         uint32_t *rq_id;
 187         uint16_t level;
 188         uint32_t prev_id[MAX_PRV_MTR_NODES]; /**< Prev mtr id for chaining */
 189         uint32_t prev_cnt;
 190         uint32_t next_id; /**< Next mtr id for chaining */
 191         bool is_prev;
 192         bool is_next;
 193         struct rte_mtr_params params;
 194         struct roc_nix_bpf_objs profs;
 195         bool is_used;
 196         uint32_t ref_cnt;
 197 };
 198
 199 struct action_rss {
 200         enum rte_eth_hash_function func;
 201         uint32_t level;
 202         uint64_t types;
 203         uint32_t key_len;
 204         uint32_t queue_num;
 205         uint8_t *key;
 206         uint16_t *queue;
 207 };
 208
 209 struct policy_actions {
 210         uint32_t action_fate;
 211         union {
 212                 uint16_t queue;
 213                 uint32_t mtr_id;
 214                 struct action_rss *rss_desc;
 215         };
 216 };
 217
 218 struct cnxk_mtr_policy_node {
 219         TAILQ_ENTRY(cnxk_mtr_policy_node) next;
 220         /**< Pointer to the next flow meter structure. */
 221         uint32_t id;     /**< Policy id */
 222         uint32_t mtr_id; /** Meter id */
 223         struct rte_mtr_meter_policy_params policy;
 224         struct policy_actions actions[RTE_COLORS];
 225         uint32_t ref_cnt;
 226 };
 227
 228 struct cnxk_mtr_profile_node {
 229         TAILQ_ENTRY(cnxk_mtr_profile_node) next;
 230         struct rte_mtr_meter_profile profile; /**< Profile detail. */
 231         uint32_t ref_cnt;                     /**< Use count. */
 232         uint32_t id;                          /**< Profile id. */
 233 };
 234
 235 TAILQ_HEAD(cnxk_mtr_profiles, cnxk_mtr_profile_node);
 236 TAILQ_HEAD(cnxk_mtr_policy, cnxk_mtr_policy_node);
 237 TAILQ_HEAD(cnxk_mtr, cnxk_meter_node);
 238
 239 /* Security session private data */
 240 struct cnxk_eth_sec_sess {
 241         /* List entry */
 242         TAILQ_ENTRY(cnxk_eth_sec_sess) entry;
 243
 244         /* Inbound SA is from NIX_RX_IPSEC_SA_BASE or
 245          * Outbound SA from roc_nix_inl_outb_sa_base_get()
 246          */
 247         void *sa;
 248
 249         /* SA index */
 250         uint32_t sa_idx;
 251
 252         /* SPI */
 253         uint32_t spi;
 254
 255         /* Back pointer to session */
 256         struct rte_security_session *sess;
 257
 258         /* Inbound */
 259         bool inb;
 260
 261         /* Inbound session on inl dev */
 262         bool inl_dev;
 263 };
 264
 265 TAILQ_HEAD(cnxk_eth_sec_sess_list, cnxk_eth_sec_sess);
 266
 267 /* Inbound security data */
 268 struct cnxk_eth_dev_sec_inb {
 269         /* IPSec inbound max SPI */
 270         uint16_t max_spi;
 271
 272         /* Using inbound with inline device */
 273         bool inl_dev;
 274
 275         /* Device argument to force inline device for inb */
 276         bool force_inl_dev;
 277
 278         /* Active sessions */
 279         uint16_t nb_sess;
 280
 281         /* List of sessions */
 282         struct cnxk_eth_sec_sess_list list;
 283
 284         /* DPTR for WRITE_SA microcode op */
 285         void *sa_dptr;
 286
 287         /* Lock to synchronize sa setup/release */
 288         rte_spinlock_t lock;
 289 };
 290
 291 /* Outbound security data */
 292 struct cnxk_eth_dev_sec_outb {
 293         /* IPSec outbound max SA */
 294         uint16_t max_sa;
 295
 296         /* Per CPT LF descriptor count */
 297         uint32_t nb_desc;
 298
 299         /* SA Bitmap */
 300         struct plt_bitmap *sa_bmap;
 301
 302         /* SA bitmap memory */
 303         void *sa_bmap_mem;
 304
 305         /* SA base */
 306         uint64_t sa_base;
 307
 308         /* CPT LF base */
 309         struct roc_cpt_lf *lf_base;
 310
 311         /* Crypto queues => CPT lf count */
 312         uint16_t nb_crypto_qs;
 313
 314         /* Active sessions */
 315         uint16_t nb_sess;
 316
 317         /* List of sessions */
 318         struct cnxk_eth_sec_sess_list list;
 319
 320         /* DPTR for WRITE_SA microcode op */
 321         void *sa_dptr;
 322
 323         /* Lock to synchronize sa setup/release */
 324         rte_spinlock_t lock;
 325 };
 326
 327 struct cnxk_eth_dev {
 328         /* ROC NIX */
 329         struct roc_nix nix;
 330
 331         /* ROC NPC */
 332         struct roc_npc npc;
 333
 334         /* ROC RQs, SQs and CQs */
 335         struct roc_nix_rq *rqs;
 336         struct roc_nix_sq *sqs;
 337         struct roc_nix_cq *cqs;
 338
 339         /* Configured queue count */
 340         uint16_t nb_rxq;
 341         uint16_t nb_txq;
 342         uint16_t nb_rxq_sso;
 343         uint8_t configured;
 344
 345         /* Max macfilter entries */
 346         uint8_t dmac_filter_count;
 347         uint8_t max_mac_entries;
 348         bool dmac_filter_enable;
 349
 350         uint16_t flags;
 351         uint8_t ptype_disable;
 352         bool scalar_ena;
 353         bool ptp_en;
 354         bool rx_mark_update; /* Enable/Disable mark update to mbuf */
 355
 356         /* Pointer back to rte */
 357         struct rte_eth_dev *eth_dev;
 358
 359         /* HW capabilities / Limitations */
 360         union {
 361                 struct {
 362                         uint64_t cq_min_4k : 1;
 363                         uint64_t ipsecd_drop_re_dis : 1;
 364                         uint64_t vec_drop_re_dis : 1;
 365                 };
 366                 uint64_t hwcap;
 367         };
 368
 369         /* Rx and Tx offload capabilities */
 370         uint64_t rx_offload_capa;
 371         uint64_t tx_offload_capa;
 372         uint32_t speed_capa;
 373         /* Configured Rx and Tx offloads */
 374         uint64_t rx_offloads;
 375         uint64_t tx_offloads;
 376         /* Platform specific offload flags */
 377         uint16_t rx_offload_flags;
 378         uint16_t tx_offload_flags;
 379
 380         /* ETHDEV RSS HF bitmask */
 381         uint64_t ethdev_rss_hf;
 382
 383         /* Saved qconf before lf realloc */
 384         struct cnxk_eth_qconf *tx_qconf;
 385         struct cnxk_eth_qconf *rx_qconf;
 386
 387         /* Flow control configuration */
 388         uint16_t pfc_tc_sq_map[CNXK_NIX_PFC_CHAN_COUNT];
 389         struct cnxk_pfc_cfg pfc_cfg;
 390         struct cnxk_fc_cfg fc_cfg;
 391
 392         /* PTP Counters */
 393         struct cnxk_timesync_info tstamp;
 394         struct rte_timecounter systime_tc;
 395         struct rte_timecounter rx_tstamp_tc;
 396         struct rte_timecounter tx_tstamp_tc;
 397         double clk_freq_mult;
 398         uint64_t clk_delta;
 399
 400         /* Ingress policer */
 401         enum roc_nix_bpf_color precolor_tbl[ROC_NIX_BPF_PRE_COLOR_MAX];
 402         struct cnxk_mtr_profiles mtr_profiles;
 403         struct cnxk_mtr_policy mtr_policy;
 404         struct cnxk_mtr mtr;
 405
 406         /* Rx burst for cleanup(Only Primary) */
 407         eth_rx_burst_t rx_pkt_burst_no_offload;
 408
 409         /* Default mac address */
 410         uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
 411
 412         /* LSO Tunnel format indices */
 413         uint64_t lso_tun_fmt;
 414
 415         /* Per queue statistics counters */
 416         uint32_t txq_stat_map[RTE_ETHDEV_QUEUE_STAT_CNTRS];
 417         uint32_t rxq_stat_map[RTE_ETHDEV_QUEUE_STAT_CNTRS];
 418
 419         /* Security data */
 420         struct cnxk_eth_dev_sec_inb inb;
 421         struct cnxk_eth_dev_sec_outb outb;
 422 };
 423
 424 struct cnxk_eth_rxq_sp {
 425         struct cnxk_eth_dev *dev;
 426         struct cnxk_eth_qconf qconf;
 427         uint16_t qid;
 428 } __plt_cache_aligned;
 429
 430 struct cnxk_eth_txq_sp {
 431         struct cnxk_eth_dev *dev;
 432         struct cnxk_eth_qconf qconf;
 433         uint16_t qid;
 434 } __plt_cache_aligned;
 435
 436 static inline struct cnxk_eth_dev *
 437 cnxk_eth_pmd_priv(const struct rte_eth_dev *eth_dev)
 438 {
 439         return eth_dev->data->dev_private;
 440 }
 441
 442 static inline struct cnxk_eth_rxq_sp *
 443 cnxk_eth_rxq_to_sp(void *__rxq)
 444 {
 445         return ((struct cnxk_eth_rxq_sp *)__rxq) - 1;
 446 }
 447
 448 static inline struct cnxk_eth_txq_sp *
 449 cnxk_eth_txq_to_sp(void *__txq)
 450 {
 451         return ((struct cnxk_eth_txq_sp *)__txq) - 1;
 452 }
 453
 454 /* Common ethdev ops */
 455 extern struct eth_dev_ops cnxk_eth_dev_ops;
 456
 457 /* Common flow ops */
 458 extern struct rte_flow_ops cnxk_flow_ops;
 459
 460 /* Common security ops */
 461 extern struct rte_security_ops cnxk_eth_sec_ops;
 462
 463 /* Ops */
 464 int cnxk_nix_probe(struct rte_pci_driver *pci_drv,
 465                    struct rte_pci_device *pci_dev);
 466 int cnxk_nix_remove(struct rte_pci_device *pci_dev);
 467 int cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
 468 int cnxk_nix_mc_addr_list_configure(struct rte_eth_dev *eth_dev,
 469                                     struct rte_ether_addr *mc_addr_set,
 470                                     uint32_t nb_mc_addr);
 471 int cnxk_nix_mac_addr_add(struct rte_eth_dev *eth_dev,
 472                           struct rte_ether_addr *addr, uint32_t index,
 473                           uint32_t pool);
 474 void cnxk_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index);
 475 int cnxk_nix_mac_addr_set(struct rte_eth_dev *eth_dev,
 476                           struct rte_ether_addr *addr);
 477 int cnxk_nix_promisc_enable(struct rte_eth_dev *eth_dev);
 478 int cnxk_nix_promisc_disable(struct rte_eth_dev *eth_dev);
 479 int cnxk_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);
 480 int cnxk_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);
 481 int cnxk_nix_info_get(struct rte_eth_dev *eth_dev,
 482                       struct rte_eth_dev_info *dev_info);
 483 int cnxk_nix_rx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
 484                                struct rte_eth_burst_mode *mode);
 485 int cnxk_nix_tx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
 486                                struct rte_eth_burst_mode *mode);
 487 int cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
 488                            struct rte_eth_fc_conf *fc_conf);
 489 int cnxk_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
 490                            struct rte_eth_fc_conf *fc_conf);
 491 int cnxk_nix_priority_flow_ctrl_queue_config(struct rte_eth_dev *eth_dev,
 492                                              struct rte_eth_pfc_queue_conf *pfc_conf);
 493 int cnxk_nix_priority_flow_ctrl_queue_info_get(struct rte_eth_dev *eth_dev,
 494                                                struct rte_eth_pfc_queue_info *pfc_info);
 495 int cnxk_nix_set_link_up(struct rte_eth_dev *eth_dev);
 496 int cnxk_nix_set_link_down(struct rte_eth_dev *eth_dev);
 497 int cnxk_nix_get_module_info(struct rte_eth_dev *eth_dev,
 498                              struct rte_eth_dev_module_info *modinfo);
 499 int cnxk_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
 500                                struct rte_dev_eeprom_info *info);
 501 int cnxk_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
 502                                   uint16_t rx_queue_id);
 503 int cnxk_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
 504                                    uint16_t rx_queue_id);
 505 int cnxk_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool);
 506 int cnxk_nix_tx_done_cleanup(void *txq, uint32_t free_cnt);
 507 int cnxk_nix_flow_ops_get(struct rte_eth_dev *eth_dev,
 508                           const struct rte_flow_ops **ops);
 509 int cnxk_nix_configure(struct rte_eth_dev *eth_dev);
 510 int cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 511                             uint16_t nb_desc, uint16_t fp_tx_q_sz,
 512                             const struct rte_eth_txconf *tx_conf);
 513 int cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 514                             uint16_t nb_desc, uint16_t fp_rx_q_sz,
 515                             const struct rte_eth_rxconf *rx_conf,
 516                             struct rte_mempool *mp);
 517 int cnxk_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid);
 518 int cnxk_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid);
 519 int cnxk_nix_dev_start(struct rte_eth_dev *eth_dev);
 520 int cnxk_nix_timesync_enable(struct rte_eth_dev *eth_dev);
 521 int cnxk_nix_timesync_disable(struct rte_eth_dev *eth_dev);
 522 int cnxk_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev,
 523                                         struct timespec *timestamp,
 524                                         uint32_t flags);
 525 int cnxk_nix_timesync_read_tx_timestamp(struct rte_eth_dev *eth_dev,
 526                                         struct timespec *timestamp);
 527 int cnxk_nix_timesync_read_time(struct rte_eth_dev *eth_dev,
 528                                 struct timespec *ts);
 529 int cnxk_nix_timesync_write_time(struct rte_eth_dev *eth_dev,
 530                                  const struct timespec *ts);
 531 int cnxk_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta);
 532 int cnxk_nix_tsc_convert(struct cnxk_eth_dev *dev);
 533 int cnxk_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *clock);
 534
 535 uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev);
 536 int cnxk_nix_tm_ops_get(struct rte_eth_dev *eth_dev, void *ops);
 537 int cnxk_nix_tm_set_queue_rate_limit(struct rte_eth_dev *eth_dev,
 538                                      uint16_t queue_idx, uint16_t tx_rate);
 539
 540 /* MTR */
 541 int cnxk_nix_mtr_ops_get(struct rte_eth_dev *dev, void *ops);
 542
 543 /* RSS */
 544 uint32_t cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
 545                                 uint8_t rss_level);
 546 int cnxk_nix_reta_update(struct rte_eth_dev *eth_dev,
 547                          struct rte_eth_rss_reta_entry64 *reta_conf,
 548                          uint16_t reta_size);
 549 int cnxk_nix_reta_query(struct rte_eth_dev *eth_dev,
 550                         struct rte_eth_rss_reta_entry64 *reta_conf,
 551                         uint16_t reta_size);
 552 int cnxk_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
 553                              struct rte_eth_rss_conf *rss_conf);
 554 int cnxk_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
 555                                struct rte_eth_rss_conf *rss_conf);
 556
 557 /* Link */
 558 void cnxk_nix_toggle_flag_link_cfg(struct cnxk_eth_dev *dev, bool set);
 559 void cnxk_eth_dev_link_status_cb(struct roc_nix *nix,
 560                                  struct roc_nix_link_info *link);
 561 void cnxk_eth_dev_link_status_get_cb(struct roc_nix *nix,
 562                                      struct roc_nix_link_info *link);
 563 int cnxk_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
 564 int cnxk_nix_queue_stats_mapping(struct rte_eth_dev *dev, uint16_t queue_id,
 565                                  uint8_t stat_idx, uint8_t is_rx);
 566 int cnxk_nix_stats_reset(struct rte_eth_dev *dev);
 567 int cnxk_nix_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 568 int cnxk_nix_xstats_get(struct rte_eth_dev *eth_dev,
 569                         struct rte_eth_xstat *xstats, unsigned int n);
 570 int cnxk_nix_xstats_get_names(struct rte_eth_dev *eth_dev,
 571                               struct rte_eth_xstat_name *xstats_names,
 572                               unsigned int limit);
 573 int cnxk_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,
 574                                     const uint64_t *ids,
 575                                     struct rte_eth_xstat_name *xstats_names,
 576                                     unsigned int limit);
 577 int cnxk_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids,
 578                               uint64_t *values, unsigned int n);
 579 int cnxk_nix_xstats_reset(struct rte_eth_dev *eth_dev);
 580 int cnxk_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
 581                             size_t fw_size);
 582 void cnxk_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid,
 583                            struct rte_eth_rxq_info *qinfo);
 584 void cnxk_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid,
 585                            struct rte_eth_txq_info *qinfo);
 586
 587 /* Queue status */
 588 int cnxk_nix_rx_descriptor_status(void *rxq, uint16_t offset);
 589 int cnxk_nix_tx_descriptor_status(void *txq, uint16_t offset);
 590 uint32_t cnxk_nix_rx_queue_count(void *rxq);
 591
 592 /* Lookup configuration */
 593 const uint32_t *cnxk_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev);
 594 void *cnxk_nix_fastpath_lookup_mem_get(void);
 595
 596 /* Devargs */
 597 int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs,
 598                               struct cnxk_eth_dev *dev);
 599
 600 /* Debug */
 601 int cnxk_nix_dev_get_reg(struct rte_eth_dev *eth_dev,
 602                          struct rte_dev_reg_info *regs);
 603 /* Security */
 604 int cnxk_eth_outb_sa_idx_get(struct cnxk_eth_dev *dev, uint32_t *idx_p);
 605 int cnxk_eth_outb_sa_idx_put(struct cnxk_eth_dev *dev, uint32_t idx);
 606 int cnxk_nix_lookup_mem_sa_base_set(struct cnxk_eth_dev *dev);
 607 int cnxk_nix_lookup_mem_sa_base_clear(struct cnxk_eth_dev *dev);
 608 __rte_internal
 609 int cnxk_nix_inb_mode_set(struct cnxk_eth_dev *dev, bool use_inl_dev);
 610 struct cnxk_eth_sec_sess *cnxk_eth_sec_sess_get_by_spi(struct cnxk_eth_dev *dev,
 611                                                        uint32_t spi, bool inb);
 612 struct cnxk_eth_sec_sess *
 613 cnxk_eth_sec_sess_get_by_sess(struct cnxk_eth_dev *dev,
 614                               struct rte_security_session *sess);
 615
 616 /* Other private functions */
 617 int nix_recalc_mtu(struct rte_eth_dev *eth_dev);
 618 int nix_mtr_validate(struct rte_eth_dev *dev, uint32_t id);
 619 int nix_mtr_policy_act_get(struct rte_eth_dev *eth_dev, uint32_t id,
 620                            struct cnxk_mtr_policy_node **policy);
 621 int nix_mtr_rq_update(struct rte_eth_dev *eth_dev, uint32_t id,
 622                       uint32_t queue_num, const uint16_t *queue);
 623 int nix_mtr_chain_update(struct rte_eth_dev *eth_dev, uint32_t cur_id,
 624                          uint32_t prev_id, uint32_t next_id);
 625 int nix_mtr_chain_reset(struct rte_eth_dev *eth_dev, uint32_t cur_id);
 626 struct cnxk_meter_node *nix_get_mtr(struct rte_eth_dev *eth_dev,
 627                                     uint32_t cur_id);
 628 int nix_mtr_level_update(struct rte_eth_dev *eth_dev, uint32_t id,
 629                          uint32_t level);
 630 int nix_mtr_capabilities_init(struct rte_eth_dev *eth_dev);
 631 int nix_mtr_configure(struct rte_eth_dev *eth_dev, uint32_t id);
 632 int nix_mtr_connect(struct rte_eth_dev *eth_dev, uint32_t id);
 633 int nix_mtr_destroy(struct rte_eth_dev *eth_dev, uint32_t id,
 634                     struct rte_mtr_error *error);
 635 int nix_mtr_color_action_validate(struct rte_eth_dev *eth_dev, uint32_t id,
 636                                   uint32_t *prev_id, uint32_t *next_id,
 637                                   struct cnxk_mtr_policy_node *policy,
 638                                   int *tree_level);
 639 int nix_priority_flow_ctrl_configure(struct rte_eth_dev *eth_dev,
 640                                      struct cnxk_pfc_cfg *conf);
 641
 642 /* Inlines */
 643 static __rte_always_inline uint64_t
 644 cnxk_pktmbuf_detach(struct rte_mbuf *m)
 645 {
 646         struct rte_mempool *mp = m->pool;
 647         uint32_t mbuf_size, buf_len;
 648         struct rte_mbuf *md;
 649         uint16_t priv_size;
 650         uint16_t refcount;
 651
 652         /* Update refcount of direct mbuf */
 653         md = rte_mbuf_from_indirect(m);
 654         refcount = rte_mbuf_refcnt_update(md, -1);
 655
 656         priv_size = rte_pktmbuf_priv_size(mp);
 657         mbuf_size = (uint32_t)(sizeof(struct rte_mbuf) + priv_size);
 658         buf_len = rte_pktmbuf_data_room_size(mp);
 659
 660         m->priv_size = priv_size;
 661         m->buf_addr = (char *)m + mbuf_size;
 662         m->buf_iova = rte_mempool_virt2iova(m) + mbuf_size;
 663         m->buf_len = (uint16_t)buf_len;
 664         rte_pktmbuf_reset_headroom(m);
 665         m->data_len = 0;
 666         m->ol_flags = 0;
 667         m->next = NULL;
 668         m->nb_segs = 1;
 669
 670         /* Now indirect mbuf is safe to free */
 671         rte_pktmbuf_free(m);
 672
 673         if (refcount == 0) {
 674                 rte_mbuf_refcnt_set(md, 1);
 675                 md->data_len = 0;
 676                 md->ol_flags = 0;
 677                 md->next = NULL;
 678                 md->nb_segs = 1;
 679                 return 0;
 680         } else {
 681                 return 1;
 682         }
 683 }
 684
 685 static __rte_always_inline uint64_t
 686 cnxk_nix_prefree_seg(struct rte_mbuf *m)
 687 {
 688         if (likely(rte_mbuf_refcnt_read(m) == 1)) {
 689                 if (!RTE_MBUF_DIRECT(m))
 690                         return cnxk_pktmbuf_detach(m);
 691
 692                 m->next = NULL;
 693                 m->nb_segs = 1;
 694                 return 0;
 695         } else if (rte_mbuf_refcnt_update(m, -1) == 0) {
 696                 if (!RTE_MBUF_DIRECT(m))
 697                         return cnxk_pktmbuf_detach(m);
 698
 699                 rte_mbuf_refcnt_set(m, 1);
 700                 m->next = NULL;
 701                 m->nb_segs = 1;
 702                 return 0;
 703         }
 704
 705         /* Mbuf is having refcount more than 1 so need not to be freed */
 706         return 1;
 707 }
 708
 709 static inline rte_mbuf_timestamp_t *
 710 cnxk_nix_timestamp_dynfield(struct rte_mbuf *mbuf,
 711                             struct cnxk_timesync_info *info)
 712 {
 713         return RTE_MBUF_DYNFIELD(mbuf, info->tstamp_dynfield_offset,
 714                                  rte_mbuf_timestamp_t *);
 715 }
 716
 717 static __rte_always_inline void
 718 cnxk_nix_mbuf_to_tstamp(struct rte_mbuf *mbuf,
 719                         struct cnxk_timesync_info *tstamp,
 720                         const uint8_t ts_enable, uint64_t *tstamp_ptr)
 721 {
 722         if (ts_enable) {
 723                 mbuf->pkt_len -= CNXK_NIX_TIMESYNC_RX_OFFSET;
 724                 mbuf->data_len -= CNXK_NIX_TIMESYNC_RX_OFFSET;
 725
 726                 /* Reading the rx timestamp inserted by CGX, viz at
 727                  * starting of the packet data.
 728                  */
 729                 *cnxk_nix_timestamp_dynfield(mbuf, tstamp) =
 730                         rte_be_to_cpu_64(*tstamp_ptr);
 731                 /* RTE_MBUF_F_RX_IEEE1588_TMST flag needs to be set only in case
 732                  * PTP packets are received.
 733                  */
 734                 if (mbuf->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC) {
 735                         tstamp->rx_tstamp =
 736                                 *cnxk_nix_timestamp_dynfield(mbuf, tstamp);
 737                         tstamp->rx_ready = 1;
 738                         mbuf->ol_flags |= RTE_MBUF_F_RX_IEEE1588_PTP |
 739                                           RTE_MBUF_F_RX_IEEE1588_TMST |
 740                                           tstamp->rx_tstamp_dynflag;
 741                 }
 742         }
 743 }
 744
 745 static __rte_always_inline uintptr_t
 746 cnxk_nix_sa_base_get(uint16_t port, const void *lookup_mem)
 747 {
 748         uintptr_t sa_base_tbl;
 749
 750         sa_base_tbl = (uintptr_t)lookup_mem;
 751         sa_base_tbl += PTYPE_ARRAY_SZ + ERR_ARRAY_SZ;
 752         return *((const uintptr_t *)sa_base_tbl + port);
 753 }
 754
 755 #endif /* __CNXK_ETHDEV_H__ */