drivers/net/cnxk/cnxk_ethdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4 #ifndef __CNXK_ETHDEV_H__
   5 #define __CNXK_ETHDEV_H__
   6
   7 #include <math.h>
   8 #include <stdint.h>
   9
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_kvargs.h>
  13 #include <rte_mbuf.h>
  14 #include <rte_mbuf_pool_ops.h>
  15 #include <rte_mempool.h>
  16 #include <rte_security.h>
  17 #include <rte_security_driver.h>
  18 #include <rte_tailq.h>
  19 #include <rte_time.h>
  20
  21 #include "roc_api.h"
  22
  23 #define CNXK_ETH_DEV_PMD_VERSION "1.0"
  24
  25 /* Used for struct cnxk_eth_dev::flags */
  26 #define CNXK_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
  27
  28 /* VLAN tag inserted by NIX_TX_VTAG_ACTION.
  29  * In Tx space is always reserved for this in FRS.
  30  */
  31 #define CNXK_NIX_MAX_VTAG_INS      2
  32 #define CNXK_NIX_MAX_VTAG_ACT_SIZE (4 * CNXK_NIX_MAX_VTAG_INS)
  33
  34 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
  35 #define CNXK_NIX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + \
  36                               RTE_ETHER_CRC_LEN + \
  37                               CNXK_NIX_MAX_VTAG_ACT_SIZE)
  38
  39 #define CNXK_NIX_RX_MIN_DESC        16
  40 #define CNXK_NIX_RX_MIN_DESC_ALIGN  16
  41 #define CNXK_NIX_RX_NB_SEG_MAX      6
  42 #define CNXK_NIX_RX_DEFAULT_RING_SZ 4096
  43 /* Max supported SQB count */
  44 #define CNXK_NIX_TX_MAX_SQB 512
  45
  46 /* If PTP is enabled additional SEND MEM DESC is required which
  47  * takes 2 words, hence max 7 iova address are possible
  48  */
  49 #if defined(RTE_LIBRTE_IEEE1588)
  50 #define CNXK_NIX_TX_NB_SEG_MAX 7
  51 #else
  52 #define CNXK_NIX_TX_NB_SEG_MAX 9
  53 #endif
  54
  55 #define CNXK_NIX_TX_MSEG_SG_DWORDS                                             \
  56         ((RTE_ALIGN_MUL_CEIL(CNXK_NIX_TX_NB_SEG_MAX, 3) / 3) +                 \
  57          CNXK_NIX_TX_NB_SEG_MAX)
  58
  59 #define CNXK_NIX_RSS_L3_L4_SRC_DST                                             \
  60         (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | ETH_RSS_L4_SRC_ONLY |     \
  61          ETH_RSS_L4_DST_ONLY)
  62
  63 #define CNXK_NIX_RSS_OFFLOAD                                                   \
  64         (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP |               \
  65          ETH_RSS_SCTP | ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD |                  \
  66          CNXK_NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | ETH_RSS_C_VLAN)
  67
  68 #define CNXK_NIX_TX_OFFLOAD_CAPA                                               \
  69         (DEV_TX_OFFLOAD_MBUF_FAST_FREE | DEV_TX_OFFLOAD_MT_LOCKFREE |          \
  70          DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT |             \
  71          DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_TX_OFFLOAD_OUTER_UDP_CKSUM |    \
  72          DEV_TX_OFFLOAD_TCP_CKSUM | DEV_TX_OFFLOAD_UDP_CKSUM |                 \
  73          DEV_TX_OFFLOAD_SCTP_CKSUM | DEV_TX_OFFLOAD_TCP_TSO |                  \
  74          DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GENEVE_TNL_TSO |        \
  75          DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_MULTI_SEGS |              \
  76          DEV_TX_OFFLOAD_IPV4_CKSUM | DEV_TX_OFFLOAD_SECURITY)
  77
  78 #define CNXK_NIX_RX_OFFLOAD_CAPA                                               \
  79         (DEV_RX_OFFLOAD_CHECKSUM | DEV_RX_OFFLOAD_SCTP_CKSUM |                 \
  80          DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_SCATTER |            \
  81          DEV_RX_OFFLOAD_JUMBO_FRAME | DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |         \
  82          DEV_RX_OFFLOAD_RSS_HASH | DEV_RX_OFFLOAD_TIMESTAMP |                  \
  83          DEV_RX_OFFLOAD_VLAN_STRIP | DEV_RX_OFFLOAD_SECURITY)
  84
  85 #define RSS_IPV4_ENABLE                                                        \
  86         (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_UDP |         \
  87          ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_SCTP)
  88
  89 #define RSS_IPV6_ENABLE                                                        \
  90         (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_UDP |         \
  91          ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_NONFRAG_IPV6_SCTP)
  92
  93 #define RSS_IPV6_EX_ENABLE                                                     \
  94         (ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | ETH_RSS_IPV6_UDP_EX)
  95
  96 #define RSS_MAX_LEVELS 3
  97
  98 #define RSS_IPV4_INDEX 0
  99 #define RSS_IPV6_INDEX 1
 100 #define RSS_TCP_INDEX  2
 101 #define RSS_UDP_INDEX  3
 102 #define RSS_SCTP_INDEX 4
 103 #define RSS_DMAC_INDEX 5
 104
 105 /* Default mark value used when none is provided. */
 106 #define CNXK_FLOW_ACTION_FLAG_DEFAULT 0xffff
 107
 108 /* Default cycle counter mask */
 109 #define CNXK_CYCLECOUNTER_MASK     0xffffffffffffffffULL
 110 #define CNXK_NIX_TIMESYNC_RX_OFFSET 8
 111
 112 #define PTYPE_NON_TUNNEL_WIDTH    16
 113 #define PTYPE_TUNNEL_WIDTH        12
 114 #define PTYPE_NON_TUNNEL_ARRAY_SZ BIT(PTYPE_NON_TUNNEL_WIDTH)
 115 #define PTYPE_TUNNEL_ARRAY_SZ     BIT(PTYPE_TUNNEL_WIDTH)
 116 #define PTYPE_ARRAY_SZ                                                         \
 117         ((PTYPE_NON_TUNNEL_ARRAY_SZ + PTYPE_TUNNEL_ARRAY_SZ) * sizeof(uint16_t))
 118
 119 /* NIX_RX_PARSE_S's ERRCODE + ERRLEV (12 bits) */
 120 #define ERRCODE_ERRLEN_WIDTH 12
 121 #define ERR_ARRAY_SZ         ((BIT(ERRCODE_ERRLEN_WIDTH)) * sizeof(uint32_t))
 122
 123 /* Fastpath lookup */
 124 #define CNXK_NIX_FASTPATH_LOOKUP_MEM "cnxk_nix_fastpath_lookup_mem"
 125
 126 #define CNXK_NIX_UDP_TUN_BITMASK                                               \
 127         ((1ull << (PKT_TX_TUNNEL_VXLAN >> 45)) |                               \
 128          (1ull << (PKT_TX_TUNNEL_GENEVE >> 45)))
 129
 130 /* Subtype from inline outbound error event */
 131 #define CNXK_ETHDEV_SEC_OUTB_EV_SUB 0xFFUL
 132
 133 /* SPI will be in 20 bits of tag */
 134 #define CNXK_ETHDEV_SPI_TAG_MASK 0xFFFFFUL
 135
 136 struct cnxk_fc_cfg {
 137         enum rte_eth_fc_mode mode;
 138         uint8_t rx_pause;
 139         uint8_t tx_pause;
 140 };
 141
 142 struct cnxk_eth_qconf {
 143         union {
 144                 struct rte_eth_txconf tx;
 145                 struct rte_eth_rxconf rx;
 146         } conf;
 147         struct rte_mempool *mp;
 148         uint16_t nb_desc;
 149         uint8_t valid;
 150 };
 151
 152 struct cnxk_timesync_info {
 153         uint8_t rx_ready;
 154         uint64_t rx_tstamp;
 155         uint64_t rx_tstamp_dynflag;
 156         int tstamp_dynfield_offset;
 157         rte_iova_t tx_tstamp_iova;
 158         uint64_t *tx_tstamp;
 159 } __plt_cache_aligned;
 160
 161 /* Security session private data */
 162 struct cnxk_eth_sec_sess {
 163         /* List entry */
 164         TAILQ_ENTRY(cnxk_eth_sec_sess) entry;
 165
 166         /* Inbound SA is from NIX_RX_IPSEC_SA_BASE or
 167          * Outbound SA from roc_nix_inl_outb_sa_base_get()
 168          */
 169         void *sa;
 170
 171         /* SA index */
 172         uint32_t sa_idx;
 173
 174         /* SPI */
 175         uint32_t spi;
 176
 177         /* Back pointer to session */
 178         struct rte_security_session *sess;
 179
 180         /* Inbound */
 181         bool inb;
 182
 183         /* Inbound session on inl dev */
 184         bool inl_dev;
 185 };
 186
 187 TAILQ_HEAD(cnxk_eth_sec_sess_list, cnxk_eth_sec_sess);
 188
 189 /* Inbound security data */
 190 struct cnxk_eth_dev_sec_inb {
 191         /* IPSec inbound max SPI */
 192         uint16_t max_spi;
 193
 194         /* Using inbound with inline device */
 195         bool inl_dev;
 196
 197         /* Device argument to force inline device for inb */
 198         bool force_inl_dev;
 199
 200         /* Active sessions */
 201         uint16_t nb_sess;
 202
 203         /* List of sessions */
 204         struct cnxk_eth_sec_sess_list list;
 205 };
 206
 207 /* Outbound security data */
 208 struct cnxk_eth_dev_sec_outb {
 209         /* IPSec outbound max SA */
 210         uint16_t max_sa;
 211
 212         /* Per CPT LF descriptor count */
 213         uint32_t nb_desc;
 214
 215         /* SA Bitmap */
 216         struct plt_bitmap *sa_bmap;
 217
 218         /* SA bitmap memory */
 219         void *sa_bmap_mem;
 220
 221         /* SA base */
 222         uint64_t sa_base;
 223
 224         /* CPT LF base */
 225         struct roc_cpt_lf *lf_base;
 226
 227         /* Crypto queues => CPT lf count */
 228         uint16_t nb_crypto_qs;
 229
 230         /* Active sessions */
 231         uint16_t nb_sess;
 232
 233         /* List of sessions */
 234         struct cnxk_eth_sec_sess_list list;
 235 };
 236
 237 struct cnxk_eth_dev {
 238         /* ROC NIX */
 239         struct roc_nix nix;
 240
 241         /* ROC NPC */
 242         struct roc_npc npc;
 243
 244         /* ROC RQs, SQs and CQs */
 245         struct roc_nix_rq *rqs;
 246         struct roc_nix_sq *sqs;
 247         struct roc_nix_cq *cqs;
 248
 249         /* Configured queue count */
 250         uint16_t nb_rxq;
 251         uint16_t nb_txq;
 252         uint16_t nb_rxq_sso;
 253         uint8_t configured;
 254
 255         /* Max macfilter entries */
 256         uint8_t dmac_filter_count;
 257         uint8_t max_mac_entries;
 258         bool dmac_filter_enable;
 259
 260         uint16_t flags;
 261         uint8_t ptype_disable;
 262         bool scalar_ena;
 263         bool ptp_en;
 264
 265         /* Pointer back to rte */
 266         struct rte_eth_dev *eth_dev;
 267
 268         /* HW capabilities / Limitations */
 269         union {
 270                 struct {
 271                         uint64_t cq_min_4k : 1;
 272                 };
 273                 uint64_t hwcap;
 274         };
 275
 276         /* Rx and Tx offload capabilities */
 277         uint64_t rx_offload_capa;
 278         uint64_t tx_offload_capa;
 279         uint32_t speed_capa;
 280         /* Configured Rx and Tx offloads */
 281         uint64_t rx_offloads;
 282         uint64_t tx_offloads;
 283         /* Platform specific offload flags */
 284         uint16_t rx_offload_flags;
 285         uint16_t tx_offload_flags;
 286
 287         /* ETHDEV RSS HF bitmask */
 288         uint64_t ethdev_rss_hf;
 289
 290         /* Saved qconf before lf realloc */
 291         struct cnxk_eth_qconf *tx_qconf;
 292         struct cnxk_eth_qconf *rx_qconf;
 293
 294         /* Flow control configuration */
 295         struct cnxk_fc_cfg fc_cfg;
 296
 297         /* PTP Counters */
 298         struct cnxk_timesync_info tstamp;
 299         struct rte_timecounter systime_tc;
 300         struct rte_timecounter rx_tstamp_tc;
 301         struct rte_timecounter tx_tstamp_tc;
 302         double clk_freq_mult;
 303         uint64_t clk_delta;
 304
 305         /* Rx burst for cleanup(Only Primary) */
 306         eth_rx_burst_t rx_pkt_burst_no_offload;
 307
 308         /* Default mac address */
 309         uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
 310
 311         /* LSO Tunnel format indices */
 312         uint64_t lso_tun_fmt;
 313
 314         /* Per queue statistics counters */
 315         uint32_t txq_stat_map[RTE_ETHDEV_QUEUE_STAT_CNTRS];
 316         uint32_t rxq_stat_map[RTE_ETHDEV_QUEUE_STAT_CNTRS];
 317
 318         /* Security data */
 319         struct cnxk_eth_dev_sec_inb inb;
 320         struct cnxk_eth_dev_sec_outb outb;
 321 };
 322
 323 struct cnxk_eth_rxq_sp {
 324         struct cnxk_eth_dev *dev;
 325         struct cnxk_eth_qconf qconf;
 326         uint16_t qid;
 327 } __plt_cache_aligned;
 328
 329 struct cnxk_eth_txq_sp {
 330         struct cnxk_eth_dev *dev;
 331         struct cnxk_eth_qconf qconf;
 332         uint16_t qid;
 333 } __plt_cache_aligned;
 334
 335 static inline struct cnxk_eth_dev *
 336 cnxk_eth_pmd_priv(const struct rte_eth_dev *eth_dev)
 337 {
 338         return eth_dev->data->dev_private;
 339 }
 340
 341 static inline struct cnxk_eth_rxq_sp *
 342 cnxk_eth_rxq_to_sp(void *__rxq)
 343 {
 344         return ((struct cnxk_eth_rxq_sp *)__rxq) - 1;
 345 }
 346
 347 static inline struct cnxk_eth_txq_sp *
 348 cnxk_eth_txq_to_sp(void *__txq)
 349 {
 350         return ((struct cnxk_eth_txq_sp *)__txq) - 1;
 351 }
 352
 353 /* Common ethdev ops */
 354 extern struct eth_dev_ops cnxk_eth_dev_ops;
 355
 356 /* Common flow ops */
 357 extern struct rte_flow_ops cnxk_flow_ops;
 358
 359 /* Common security ops */
 360 extern struct rte_security_ops cnxk_eth_sec_ops;
 361
 362 /* Ops */
 363 int cnxk_nix_probe(struct rte_pci_driver *pci_drv,
 364                    struct rte_pci_device *pci_dev);
 365 int cnxk_nix_remove(struct rte_pci_device *pci_dev);
 366 int cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
 367 int cnxk_nix_mc_addr_list_configure(struct rte_eth_dev *eth_dev,
 368                                     struct rte_ether_addr *mc_addr_set,
 369                                     uint32_t nb_mc_addr);
 370 int cnxk_nix_mac_addr_add(struct rte_eth_dev *eth_dev,
 371                           struct rte_ether_addr *addr, uint32_t index,
 372                           uint32_t pool);
 373 void cnxk_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index);
 374 int cnxk_nix_mac_addr_set(struct rte_eth_dev *eth_dev,
 375                           struct rte_ether_addr *addr);
 376 int cnxk_nix_promisc_enable(struct rte_eth_dev *eth_dev);
 377 int cnxk_nix_promisc_disable(struct rte_eth_dev *eth_dev);
 378 int cnxk_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);
 379 int cnxk_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);
 380 int cnxk_nix_info_get(struct rte_eth_dev *eth_dev,
 381                       struct rte_eth_dev_info *dev_info);
 382 int cnxk_nix_rx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
 383                                struct rte_eth_burst_mode *mode);
 384 int cnxk_nix_tx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
 385                                struct rte_eth_burst_mode *mode);
 386 int cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
 387                            struct rte_eth_fc_conf *fc_conf);
 388 int cnxk_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
 389                            struct rte_eth_fc_conf *fc_conf);
 390 int cnxk_nix_set_link_up(struct rte_eth_dev *eth_dev);
 391 int cnxk_nix_set_link_down(struct rte_eth_dev *eth_dev);
 392 int cnxk_nix_get_module_info(struct rte_eth_dev *eth_dev,
 393                              struct rte_eth_dev_module_info *modinfo);
 394 int cnxk_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
 395                                struct rte_dev_eeprom_info *info);
 396 int cnxk_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
 397                                   uint16_t rx_queue_id);
 398 int cnxk_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
 399                                    uint16_t rx_queue_id);
 400 int cnxk_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool);
 401 int cnxk_nix_tx_done_cleanup(void *txq, uint32_t free_cnt);
 402 int cnxk_nix_flow_ops_get(struct rte_eth_dev *eth_dev,
 403                           const struct rte_flow_ops **ops);
 404 int cnxk_nix_configure(struct rte_eth_dev *eth_dev);
 405 int cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 406                             uint16_t nb_desc, uint16_t fp_tx_q_sz,
 407                             const struct rte_eth_txconf *tx_conf);
 408 int cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 409                             uint16_t nb_desc, uint16_t fp_rx_q_sz,
 410                             const struct rte_eth_rxconf *rx_conf,
 411                             struct rte_mempool *mp);
 412 int cnxk_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid);
 413 int cnxk_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid);
 414 int cnxk_nix_dev_start(struct rte_eth_dev *eth_dev);
 415 int cnxk_nix_timesync_enable(struct rte_eth_dev *eth_dev);
 416 int cnxk_nix_timesync_disable(struct rte_eth_dev *eth_dev);
 417 int cnxk_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev,
 418                                         struct timespec *timestamp,
 419                                         uint32_t flags);
 420 int cnxk_nix_timesync_read_tx_timestamp(struct rte_eth_dev *eth_dev,
 421                                         struct timespec *timestamp);
 422 int cnxk_nix_timesync_read_time(struct rte_eth_dev *eth_dev,
 423                                 struct timespec *ts);
 424 int cnxk_nix_timesync_write_time(struct rte_eth_dev *eth_dev,
 425                                  const struct timespec *ts);
 426 int cnxk_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta);
 427 int cnxk_nix_tsc_convert(struct cnxk_eth_dev *dev);
 428 int cnxk_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *clock);
 429
 430 uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev);
 431 int cnxk_nix_tm_ops_get(struct rte_eth_dev *eth_dev, void *ops);
 432 int cnxk_nix_tm_set_queue_rate_limit(struct rte_eth_dev *eth_dev,
 433                                      uint16_t queue_idx, uint16_t tx_rate);
 434
 435 /* RSS */
 436 uint32_t cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
 437                                 uint8_t rss_level);
 438 int cnxk_nix_reta_update(struct rte_eth_dev *eth_dev,
 439                          struct rte_eth_rss_reta_entry64 *reta_conf,
 440                          uint16_t reta_size);
 441 int cnxk_nix_reta_query(struct rte_eth_dev *eth_dev,
 442                         struct rte_eth_rss_reta_entry64 *reta_conf,
 443                         uint16_t reta_size);
 444 int cnxk_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
 445                              struct rte_eth_rss_conf *rss_conf);
 446 int cnxk_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
 447                                struct rte_eth_rss_conf *rss_conf);
 448
 449 /* Link */
 450 void cnxk_nix_toggle_flag_link_cfg(struct cnxk_eth_dev *dev, bool set);
 451 void cnxk_eth_dev_link_status_cb(struct roc_nix *nix,
 452                                  struct roc_nix_link_info *link);
 453 void cnxk_eth_dev_link_status_get_cb(struct roc_nix *nix,
 454                                      struct roc_nix_link_info *link);
 455 int cnxk_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
 456 int cnxk_nix_queue_stats_mapping(struct rte_eth_dev *dev, uint16_t queue_id,
 457                                  uint8_t stat_idx, uint8_t is_rx);
 458 int cnxk_nix_stats_reset(struct rte_eth_dev *dev);
 459 int cnxk_nix_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 460 int cnxk_nix_xstats_get(struct rte_eth_dev *eth_dev,
 461                         struct rte_eth_xstat *xstats, unsigned int n);
 462 int cnxk_nix_xstats_get_names(struct rte_eth_dev *eth_dev,
 463                               struct rte_eth_xstat_name *xstats_names,
 464                               unsigned int limit);
 465 int cnxk_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,
 466                                     const uint64_t *ids,
 467                                     struct rte_eth_xstat_name *xstats_names,
 468                                     unsigned int limit);
 469 int cnxk_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids,
 470                               uint64_t *values, unsigned int n);
 471 int cnxk_nix_xstats_reset(struct rte_eth_dev *eth_dev);
 472 int cnxk_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
 473                             size_t fw_size);
 474 void cnxk_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid,
 475                            struct rte_eth_rxq_info *qinfo);
 476 void cnxk_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid,
 477                            struct rte_eth_txq_info *qinfo);
 478
 479 /* Lookup configuration */
 480 const uint32_t *cnxk_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev);
 481 void *cnxk_nix_fastpath_lookup_mem_get(void);
 482
 483 /* Devargs */
 484 int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs,
 485                               struct cnxk_eth_dev *dev);
 486
 487 /* Debug */
 488 int cnxk_nix_dev_get_reg(struct rte_eth_dev *eth_dev,
 489                          struct rte_dev_reg_info *regs);
 490 /* Security */
 491 int cnxk_eth_outb_sa_idx_get(struct cnxk_eth_dev *dev, uint32_t *idx_p);
 492 int cnxk_eth_outb_sa_idx_put(struct cnxk_eth_dev *dev, uint32_t idx);
 493 int cnxk_nix_lookup_mem_sa_base_set(struct cnxk_eth_dev *dev);
 494 int cnxk_nix_lookup_mem_sa_base_clear(struct cnxk_eth_dev *dev);
 495 __rte_internal
 496 int cnxk_nix_inb_mode_set(struct cnxk_eth_dev *dev, bool use_inl_dev);
 497 struct cnxk_eth_sec_sess *cnxk_eth_sec_sess_get_by_spi(struct cnxk_eth_dev *dev,
 498                                                        uint32_t spi, bool inb);
 499 struct cnxk_eth_sec_sess *
 500 cnxk_eth_sec_sess_get_by_sess(struct cnxk_eth_dev *dev,
 501                               struct rte_security_session *sess);
 502
 503 /* Other private functions */
 504 int nix_recalc_mtu(struct rte_eth_dev *eth_dev);
 505
 506 /* Inlines */
 507 static __rte_always_inline uint64_t
 508 cnxk_pktmbuf_detach(struct rte_mbuf *m)
 509 {
 510         struct rte_mempool *mp = m->pool;
 511         uint32_t mbuf_size, buf_len;
 512         struct rte_mbuf *md;
 513         uint16_t priv_size;
 514         uint16_t refcount;
 515
 516         /* Update refcount of direct mbuf */
 517         md = rte_mbuf_from_indirect(m);
 518         refcount = rte_mbuf_refcnt_update(md, -1);
 519
 520         priv_size = rte_pktmbuf_priv_size(mp);
 521         mbuf_size = (uint32_t)(sizeof(struct rte_mbuf) + priv_size);
 522         buf_len = rte_pktmbuf_data_room_size(mp);
 523
 524         m->priv_size = priv_size;
 525         m->buf_addr = (char *)m + mbuf_size;
 526         m->buf_iova = rte_mempool_virt2iova(m) + mbuf_size;
 527         m->buf_len = (uint16_t)buf_len;
 528         rte_pktmbuf_reset_headroom(m);
 529         m->data_len = 0;
 530         m->ol_flags = 0;
 531         m->next = NULL;
 532         m->nb_segs = 1;
 533
 534         /* Now indirect mbuf is safe to free */
 535         rte_pktmbuf_free(m);
 536
 537         if (refcount == 0) {
 538                 rte_mbuf_refcnt_set(md, 1);
 539                 md->data_len = 0;
 540                 md->ol_flags = 0;
 541                 md->next = NULL;
 542                 md->nb_segs = 1;
 543                 return 0;
 544         } else {
 545                 return 1;
 546         }
 547 }
 548
 549 static __rte_always_inline uint64_t
 550 cnxk_nix_prefree_seg(struct rte_mbuf *m)
 551 {
 552         if (likely(rte_mbuf_refcnt_read(m) == 1)) {
 553                 if (!RTE_MBUF_DIRECT(m))
 554                         return cnxk_pktmbuf_detach(m);
 555
 556                 m->next = NULL;
 557                 m->nb_segs = 1;
 558                 return 0;
 559         } else if (rte_mbuf_refcnt_update(m, -1) == 0) {
 560                 if (!RTE_MBUF_DIRECT(m))
 561                         return cnxk_pktmbuf_detach(m);
 562
 563                 rte_mbuf_refcnt_set(m, 1);
 564                 m->next = NULL;
 565                 m->nb_segs = 1;
 566                 return 0;
 567         }
 568
 569         /* Mbuf is having refcount more than 1 so need not to be freed */
 570         return 1;
 571 }
 572
 573 static inline rte_mbuf_timestamp_t *
 574 cnxk_nix_timestamp_dynfield(struct rte_mbuf *mbuf,
 575                             struct cnxk_timesync_info *info)
 576 {
 577         return RTE_MBUF_DYNFIELD(mbuf, info->tstamp_dynfield_offset,
 578                                  rte_mbuf_timestamp_t *);
 579 }
 580
 581 static __rte_always_inline void
 582 cnxk_nix_mbuf_to_tstamp(struct rte_mbuf *mbuf,
 583                         struct cnxk_timesync_info *tstamp,
 584                         const uint8_t ts_enable, const uint8_t mseg_enable,
 585                         uint64_t *tstamp_ptr)
 586 {
 587         if (ts_enable) {
 588                 if (!mseg_enable) {
 589                         mbuf->pkt_len -= CNXK_NIX_TIMESYNC_RX_OFFSET;
 590                         mbuf->data_len -= CNXK_NIX_TIMESYNC_RX_OFFSET;
 591                 }
 592
 593                 /* Reading the rx timestamp inserted by CGX, viz at
 594                  * starting of the packet data.
 595                  */
 596                 *cnxk_nix_timestamp_dynfield(mbuf, tstamp) =
 597                         rte_be_to_cpu_64(*tstamp_ptr);
 598                 /* PKT_RX_IEEE1588_TMST flag needs to be set only in case
 599                  * PTP packets are received.
 600                  */
 601                 if (mbuf->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC) {
 602                         tstamp->rx_tstamp =
 603                                 *cnxk_nix_timestamp_dynfield(mbuf, tstamp);
 604                         tstamp->rx_ready = 1;
 605                         mbuf->ol_flags |= PKT_RX_IEEE1588_PTP |
 606                                           PKT_RX_IEEE1588_TMST |
 607                                           tstamp->rx_tstamp_dynflag;
 608                 }
 609         }
 610 }
 611
 612 static __rte_always_inline uintptr_t
 613 cnxk_nix_sa_base_get(uint16_t port, const void *lookup_mem)
 614 {
 615         uintptr_t sa_base_tbl;
 616
 617         sa_base_tbl = (uintptr_t)lookup_mem;
 618         sa_base_tbl += PTYPE_ARRAY_SZ + ERR_ARRAY_SZ;
 619         return *((const uintptr_t *)sa_base_tbl + port);
 620 }
 621
 622 #endif /* __CNXK_ETHDEV_H__ */