drivers/net/cnxk/cnxk_ethdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4 #ifndef __CNXK_ETHDEV_H__
   5 #define __CNXK_ETHDEV_H__
   6
   7 #include <math.h>
   8 #include <stdint.h>
   9
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_kvargs.h>
  13 #include <rte_mbuf.h>
  14 #include <rte_mbuf_pool_ops.h>
  15 #include <rte_mempool.h>
  16 #include <rte_mtr_driver.h>
  17 #include <rte_security.h>
  18 #include <rte_security_driver.h>
  19 #include <rte_tailq.h>
  20 #include <rte_time.h>
  21
  22 #include "roc_api.h"
  23
  24 #define CNXK_ETH_DEV_PMD_VERSION "1.0"
  25
  26 /* Used for struct cnxk_eth_dev::flags */
  27 #define CNXK_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
  28
  29 /* VLAN tag inserted by NIX_TX_VTAG_ACTION.
  30  * In Tx space is always reserved for this in FRS.
  31  */
  32 #define CNXK_NIX_MAX_VTAG_INS      2
  33 #define CNXK_NIX_MAX_VTAG_ACT_SIZE (4 * CNXK_NIX_MAX_VTAG_INS)
  34
  35 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
  36 #define CNXK_NIX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + \
  37                               RTE_ETHER_CRC_LEN + \
  38                               CNXK_NIX_MAX_VTAG_ACT_SIZE)
  39
  40 #define CNXK_NIX_RX_MIN_DESC        16
  41 #define CNXK_NIX_RX_MIN_DESC_ALIGN  16
  42 #define CNXK_NIX_RX_NB_SEG_MAX      6
  43 #define CNXK_NIX_RX_DEFAULT_RING_SZ 4096
  44 /* Max supported SQB count */
  45 #define CNXK_NIX_TX_MAX_SQB 512
  46
  47 /* If PTP is enabled additional SEND MEM DESC is required which
  48  * takes 2 words, hence max 7 iova address are possible
  49  */
  50 #if defined(RTE_LIBRTE_IEEE1588)
  51 #define CNXK_NIX_TX_NB_SEG_MAX 7
  52 #else
  53 #define CNXK_NIX_TX_NB_SEG_MAX 9
  54 #endif
  55
  56 #define CNXK_NIX_TX_MSEG_SG_DWORDS                                             \
  57         ((RTE_ALIGN_MUL_CEIL(CNXK_NIX_TX_NB_SEG_MAX, 3) / 3) +                 \
  58          CNXK_NIX_TX_NB_SEG_MAX)
  59
  60 #define CNXK_NIX_RSS_L3_L4_SRC_DST                                             \
  61         (RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY |                   \
  62          RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY)
  63
  64 #define CNXK_NIX_RSS_OFFLOAD                                                   \
  65         (RTE_ETH_RSS_PORT | RTE_ETH_RSS_IP | RTE_ETH_RSS_UDP |                 \
  66          RTE_ETH_RSS_TCP | RTE_ETH_RSS_SCTP | RTE_ETH_RSS_TUNNEL |             \
  67          RTE_ETH_RSS_L2_PAYLOAD | CNXK_NIX_RSS_L3_L4_SRC_DST |                 \
  68          RTE_ETH_RSS_LEVEL_MASK | RTE_ETH_RSS_C_VLAN)
  69
  70 #define CNXK_NIX_TX_OFFLOAD_CAPA                                               \
  71         (RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE | RTE_ETH_TX_OFFLOAD_MT_LOCKFREE |          \
  72          RTE_ETH_TX_OFFLOAD_VLAN_INSERT | RTE_ETH_TX_OFFLOAD_QINQ_INSERT |             \
  73          RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM |    \
  74          RTE_ETH_TX_OFFLOAD_TCP_CKSUM | RTE_ETH_TX_OFFLOAD_UDP_CKSUM |                 \
  75          RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | RTE_ETH_TX_OFFLOAD_TCP_TSO |                  \
  76          RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO | RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |        \
  77          RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO | RTE_ETH_TX_OFFLOAD_MULTI_SEGS |              \
  78          RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | RTE_ETH_TX_OFFLOAD_SECURITY)
  79
  80 #define CNXK_NIX_RX_OFFLOAD_CAPA                                               \
  81         (RTE_ETH_RX_OFFLOAD_CHECKSUM | RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |         \
  82          RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | RTE_ETH_RX_OFFLOAD_SCATTER |    \
  83          RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM | RTE_ETH_RX_OFFLOAD_RSS_HASH |    \
  84          RTE_ETH_RX_OFFLOAD_TIMESTAMP | RTE_ETH_RX_OFFLOAD_VLAN_STRIP |        \
  85          RTE_ETH_RX_OFFLOAD_SECURITY)
  86
  87 #define RSS_IPV4_ENABLE                                                        \
  88         (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 |                            \
  89          RTE_ETH_RSS_NONFRAG_IPV4_UDP | RTE_ETH_RSS_NONFRAG_IPV4_TCP |         \
  90          RTE_ETH_RSS_NONFRAG_IPV4_SCTP)
  91
  92 #define RSS_IPV6_ENABLE                                                        \
  93         (RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 |                            \
  94          RTE_ETH_RSS_NONFRAG_IPV6_UDP | RTE_ETH_RSS_NONFRAG_IPV6_TCP |         \
  95          RTE_ETH_RSS_NONFRAG_IPV6_SCTP)
  96
  97 #define RSS_IPV6_EX_ENABLE                                                     \
  98         (RTE_ETH_RSS_IPV6_EX | RTE_ETH_RSS_IPV6_TCP_EX | RTE_ETH_RSS_IPV6_UDP_EX)
  99
 100 #define RSS_MAX_LEVELS 3
 101
 102 #define RSS_IPV4_INDEX 0
 103 #define RSS_IPV6_INDEX 1
 104 #define RSS_TCP_INDEX  2
 105 #define RSS_UDP_INDEX  3
 106 #define RSS_SCTP_INDEX 4
 107 #define RSS_DMAC_INDEX 5
 108
 109 /* Default mark value used when none is provided. */
 110 #define CNXK_FLOW_ACTION_FLAG_DEFAULT 0xffff
 111
 112 /* Default cycle counter mask */
 113 #define CNXK_CYCLECOUNTER_MASK     0xffffffffffffffffULL
 114 #define CNXK_NIX_TIMESYNC_RX_OFFSET 8
 115
 116 #define PTYPE_NON_TUNNEL_WIDTH    16
 117 #define PTYPE_TUNNEL_WIDTH        12
 118 #define PTYPE_NON_TUNNEL_ARRAY_SZ BIT(PTYPE_NON_TUNNEL_WIDTH)
 119 #define PTYPE_TUNNEL_ARRAY_SZ     BIT(PTYPE_TUNNEL_WIDTH)
 120 #define PTYPE_ARRAY_SZ                                                         \
 121         ((PTYPE_NON_TUNNEL_ARRAY_SZ + PTYPE_TUNNEL_ARRAY_SZ) * sizeof(uint16_t))
 122
 123 /* NIX_RX_PARSE_S's ERRCODE + ERRLEV (12 bits) */
 124 #define ERRCODE_ERRLEN_WIDTH 12
 125 #define ERR_ARRAY_SZ         ((BIT(ERRCODE_ERRLEN_WIDTH)) * sizeof(uint32_t))
 126
 127 /* Fastpath lookup */
 128 #define CNXK_NIX_FASTPATH_LOOKUP_MEM "cnxk_nix_fastpath_lookup_mem"
 129
 130 #define CNXK_NIX_UDP_TUN_BITMASK                                               \
 131         ((1ull << (RTE_MBUF_F_TX_TUNNEL_VXLAN >> 45)) |                               \
 132          (1ull << (RTE_MBUF_F_TX_TUNNEL_GENEVE >> 45)))
 133
 134 /* Subtype from inline outbound error event */
 135 #define CNXK_ETHDEV_SEC_OUTB_EV_SUB 0xFFUL
 136
 137 /* SPI will be in 20 bits of tag */
 138 #define CNXK_ETHDEV_SPI_TAG_MASK 0xFFFFFUL
 139
 140 struct cnxk_fc_cfg {
 141         enum rte_eth_fc_mode mode;
 142         uint8_t rx_pause;
 143         uint8_t tx_pause;
 144 };
 145
 146 struct cnxk_eth_qconf {
 147         union {
 148                 struct rte_eth_txconf tx;
 149                 struct rte_eth_rxconf rx;
 150         } conf;
 151         struct rte_mempool *mp;
 152         uint16_t nb_desc;
 153         uint8_t valid;
 154 };
 155
 156 struct cnxk_timesync_info {
 157         uint8_t rx_ready;
 158         uint64_t rx_tstamp;
 159         uint64_t rx_tstamp_dynflag;
 160         int tstamp_dynfield_offset;
 161         rte_iova_t tx_tstamp_iova;
 162         uint64_t *tx_tstamp;
 163 } __plt_cache_aligned;
 164
 165 struct cnxk_meter_node {
 166 #define MAX_PRV_MTR_NODES 10
 167         TAILQ_ENTRY(cnxk_meter_node) next;
 168         /**< Pointer to the next flow meter structure. */
 169         uint32_t id; /**< Usr mtr id. */
 170         struct cnxk_mtr_profile_node *profile;
 171         struct cnxk_mtr_policy_node *policy;
 172         uint32_t bpf_id; /**< Hw mtr id. */
 173         uint32_t rq_num;
 174         uint32_t *rq_id;
 175         uint16_t level;
 176         uint32_t prev_id[MAX_PRV_MTR_NODES]; /**< Prev mtr id for chaining */
 177         uint32_t prev_cnt;
 178         uint32_t next_id; /**< Next mtr id for chaining */
 179         bool is_prev;
 180         bool is_next;
 181         struct rte_mtr_params params;
 182         struct roc_nix_bpf_objs profs;
 183         bool is_used;
 184         uint32_t ref_cnt;
 185 };
 186
 187 struct action_rss {
 188         enum rte_eth_hash_function func;
 189         uint32_t level;
 190         uint64_t types;
 191         uint32_t key_len;
 192         uint32_t queue_num;
 193         uint8_t *key;
 194         uint16_t *queue;
 195 };
 196
 197 struct policy_actions {
 198         uint32_t action_fate;
 199         union {
 200                 uint16_t queue;
 201                 uint32_t mtr_id;
 202                 struct action_rss *rss_desc;
 203         };
 204 };
 205
 206 struct cnxk_mtr_policy_node {
 207         TAILQ_ENTRY(cnxk_mtr_policy_node) next;
 208         /**< Pointer to the next flow meter structure. */
 209         uint32_t id;     /**< Policy id */
 210         uint32_t mtr_id; /** Meter id */
 211         struct rte_mtr_meter_policy_params policy;
 212         struct policy_actions actions[RTE_COLORS];
 213         uint32_t ref_cnt;
 214 };
 215
 216 struct cnxk_mtr_profile_node {
 217         TAILQ_ENTRY(cnxk_mtr_profile_node) next;
 218         struct rte_mtr_meter_profile profile; /**< Profile detail. */
 219         uint32_t ref_cnt;                     /**< Use count. */
 220         uint32_t id;                          /**< Profile id. */
 221 };
 222
 223 TAILQ_HEAD(cnxk_mtr_profiles, cnxk_mtr_profile_node);
 224 TAILQ_HEAD(cnxk_mtr_policy, cnxk_mtr_policy_node);
 225 TAILQ_HEAD(cnxk_mtr, cnxk_meter_node);
 226
 227 /* Security session private data */
 228 struct cnxk_eth_sec_sess {
 229         /* List entry */
 230         TAILQ_ENTRY(cnxk_eth_sec_sess) entry;
 231
 232         /* Inbound SA is from NIX_RX_IPSEC_SA_BASE or
 233          * Outbound SA from roc_nix_inl_outb_sa_base_get()
 234          */
 235         void *sa;
 236
 237         /* SA index */
 238         uint32_t sa_idx;
 239
 240         /* SPI */
 241         uint32_t spi;
 242
 243         /* Back pointer to session */
 244         struct rte_security_session *sess;
 245
 246         /* Inbound */
 247         bool inb;
 248
 249         /* Inbound session on inl dev */
 250         bool inl_dev;
 251 };
 252
 253 TAILQ_HEAD(cnxk_eth_sec_sess_list, cnxk_eth_sec_sess);
 254
 255 /* Inbound security data */
 256 struct cnxk_eth_dev_sec_inb {
 257         /* IPSec inbound max SPI */
 258         uint16_t max_spi;
 259
 260         /* Using inbound with inline device */
 261         bool inl_dev;
 262
 263         /* Device argument to force inline device for inb */
 264         bool force_inl_dev;
 265
 266         /* Active sessions */
 267         uint16_t nb_sess;
 268
 269         /* List of sessions */
 270         struct cnxk_eth_sec_sess_list list;
 271
 272         /* DPTR for WRITE_SA microcode op */
 273         void *sa_dptr;
 274
 275         /* Lock to synchronize sa setup/release */
 276         rte_spinlock_t lock;
 277 };
 278
 279 /* Outbound security data */
 280 struct cnxk_eth_dev_sec_outb {
 281         /* IPSec outbound max SA */
 282         uint16_t max_sa;
 283
 284         /* Per CPT LF descriptor count */
 285         uint32_t nb_desc;
 286
 287         /* SA Bitmap */
 288         struct plt_bitmap *sa_bmap;
 289
 290         /* SA bitmap memory */
 291         void *sa_bmap_mem;
 292
 293         /* SA base */
 294         uint64_t sa_base;
 295
 296         /* CPT LF base */
 297         struct roc_cpt_lf *lf_base;
 298
 299         /* Crypto queues => CPT lf count */
 300         uint16_t nb_crypto_qs;
 301
 302         /* Active sessions */
 303         uint16_t nb_sess;
 304
 305         /* List of sessions */
 306         struct cnxk_eth_sec_sess_list list;
 307
 308         /* DPTR for WRITE_SA microcode op */
 309         void *sa_dptr;
 310
 311         /* Lock to synchronize sa setup/release */
 312         rte_spinlock_t lock;
 313 };
 314
 315 struct cnxk_eth_dev {
 316         /* ROC NIX */
 317         struct roc_nix nix;
 318
 319         /* ROC NPC */
 320         struct roc_npc npc;
 321
 322         /* ROC RQs, SQs and CQs */
 323         struct roc_nix_rq *rqs;
 324         struct roc_nix_sq *sqs;
 325         struct roc_nix_cq *cqs;
 326
 327         /* Configured queue count */
 328         uint16_t nb_rxq;
 329         uint16_t nb_txq;
 330         uint16_t nb_rxq_sso;
 331         uint8_t configured;
 332
 333         /* Max macfilter entries */
 334         uint8_t dmac_filter_count;
 335         uint8_t max_mac_entries;
 336         bool dmac_filter_enable;
 337
 338         uint16_t flags;
 339         uint8_t ptype_disable;
 340         bool scalar_ena;
 341         bool ptp_en;
 342
 343         /* Pointer back to rte */
 344         struct rte_eth_dev *eth_dev;
 345
 346         /* HW capabilities / Limitations */
 347         union {
 348                 struct {
 349                         uint64_t cq_min_4k : 1;
 350                         uint64_t ipsecd_drop_re_dis : 1;
 351                         uint64_t vec_drop_re_dis : 1;
 352                 };
 353                 uint64_t hwcap;
 354         };
 355
 356         /* Rx and Tx offload capabilities */
 357         uint64_t rx_offload_capa;
 358         uint64_t tx_offload_capa;
 359         uint32_t speed_capa;
 360         /* Configured Rx and Tx offloads */
 361         uint64_t rx_offloads;
 362         uint64_t tx_offloads;
 363         /* Platform specific offload flags */
 364         uint16_t rx_offload_flags;
 365         uint16_t tx_offload_flags;
 366
 367         /* ETHDEV RSS HF bitmask */
 368         uint64_t ethdev_rss_hf;
 369
 370         /* Saved qconf before lf realloc */
 371         struct cnxk_eth_qconf *tx_qconf;
 372         struct cnxk_eth_qconf *rx_qconf;
 373
 374         /* Flow control configuration */
 375         struct cnxk_fc_cfg fc_cfg;
 376
 377         /* PTP Counters */
 378         struct cnxk_timesync_info tstamp;
 379         struct rte_timecounter systime_tc;
 380         struct rte_timecounter rx_tstamp_tc;
 381         struct rte_timecounter tx_tstamp_tc;
 382         double clk_freq_mult;
 383         uint64_t clk_delta;
 384
 385         /* Ingress policer */
 386         enum roc_nix_bpf_color precolor_tbl[ROC_NIX_BPF_PRE_COLOR_MAX];
 387         struct cnxk_mtr_profiles mtr_profiles;
 388         struct cnxk_mtr_policy mtr_policy;
 389         struct cnxk_mtr mtr;
 390
 391         /* Rx burst for cleanup(Only Primary) */
 392         eth_rx_burst_t rx_pkt_burst_no_offload;
 393
 394         /* Default mac address */
 395         uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
 396
 397         /* LSO Tunnel format indices */
 398         uint64_t lso_tun_fmt;
 399
 400         /* Per queue statistics counters */
 401         uint32_t txq_stat_map[RTE_ETHDEV_QUEUE_STAT_CNTRS];
 402         uint32_t rxq_stat_map[RTE_ETHDEV_QUEUE_STAT_CNTRS];
 403
 404         /* Security data */
 405         struct cnxk_eth_dev_sec_inb inb;
 406         struct cnxk_eth_dev_sec_outb outb;
 407 };
 408
 409 struct cnxk_eth_rxq_sp {
 410         struct cnxk_eth_dev *dev;
 411         struct cnxk_eth_qconf qconf;
 412         uint16_t qid;
 413 } __plt_cache_aligned;
 414
 415 struct cnxk_eth_txq_sp {
 416         struct cnxk_eth_dev *dev;
 417         struct cnxk_eth_qconf qconf;
 418         uint16_t qid;
 419 } __plt_cache_aligned;
 420
 421 static inline struct cnxk_eth_dev *
 422 cnxk_eth_pmd_priv(const struct rte_eth_dev *eth_dev)
 423 {
 424         return eth_dev->data->dev_private;
 425 }
 426
 427 static inline struct cnxk_eth_rxq_sp *
 428 cnxk_eth_rxq_to_sp(void *__rxq)
 429 {
 430         return ((struct cnxk_eth_rxq_sp *)__rxq) - 1;
 431 }
 432
 433 static inline struct cnxk_eth_txq_sp *
 434 cnxk_eth_txq_to_sp(void *__txq)
 435 {
 436         return ((struct cnxk_eth_txq_sp *)__txq) - 1;
 437 }
 438
 439 /* Common ethdev ops */
 440 extern struct eth_dev_ops cnxk_eth_dev_ops;
 441
 442 /* Common flow ops */
 443 extern struct rte_flow_ops cnxk_flow_ops;
 444
 445 /* Common security ops */
 446 extern struct rte_security_ops cnxk_eth_sec_ops;
 447
 448 /* Ops */
 449 int cnxk_nix_probe(struct rte_pci_driver *pci_drv,
 450                    struct rte_pci_device *pci_dev);
 451 int cnxk_nix_remove(struct rte_pci_device *pci_dev);
 452 int cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
 453 int cnxk_nix_mc_addr_list_configure(struct rte_eth_dev *eth_dev,
 454                                     struct rte_ether_addr *mc_addr_set,
 455                                     uint32_t nb_mc_addr);
 456 int cnxk_nix_mac_addr_add(struct rte_eth_dev *eth_dev,
 457                           struct rte_ether_addr *addr, uint32_t index,
 458                           uint32_t pool);
 459 void cnxk_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index);
 460 int cnxk_nix_mac_addr_set(struct rte_eth_dev *eth_dev,
 461                           struct rte_ether_addr *addr);
 462 int cnxk_nix_promisc_enable(struct rte_eth_dev *eth_dev);
 463 int cnxk_nix_promisc_disable(struct rte_eth_dev *eth_dev);
 464 int cnxk_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);
 465 int cnxk_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);
 466 int cnxk_nix_info_get(struct rte_eth_dev *eth_dev,
 467                       struct rte_eth_dev_info *dev_info);
 468 int cnxk_nix_rx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
 469                                struct rte_eth_burst_mode *mode);
 470 int cnxk_nix_tx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
 471                                struct rte_eth_burst_mode *mode);
 472 int cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
 473                            struct rte_eth_fc_conf *fc_conf);
 474 int cnxk_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
 475                            struct rte_eth_fc_conf *fc_conf);
 476 int cnxk_nix_set_link_up(struct rte_eth_dev *eth_dev);
 477 int cnxk_nix_set_link_down(struct rte_eth_dev *eth_dev);
 478 int cnxk_nix_get_module_info(struct rte_eth_dev *eth_dev,
 479                              struct rte_eth_dev_module_info *modinfo);
 480 int cnxk_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
 481                                struct rte_dev_eeprom_info *info);
 482 int cnxk_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
 483                                   uint16_t rx_queue_id);
 484 int cnxk_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
 485                                    uint16_t rx_queue_id);
 486 int cnxk_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool);
 487 int cnxk_nix_tx_done_cleanup(void *txq, uint32_t free_cnt);
 488 int cnxk_nix_flow_ops_get(struct rte_eth_dev *eth_dev,
 489                           const struct rte_flow_ops **ops);
 490 int cnxk_nix_configure(struct rte_eth_dev *eth_dev);
 491 int cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 492                             uint16_t nb_desc, uint16_t fp_tx_q_sz,
 493                             const struct rte_eth_txconf *tx_conf);
 494 int cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 495                             uint16_t nb_desc, uint16_t fp_rx_q_sz,
 496                             const struct rte_eth_rxconf *rx_conf,
 497                             struct rte_mempool *mp);
 498 int cnxk_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid);
 499 int cnxk_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid);
 500 int cnxk_nix_dev_start(struct rte_eth_dev *eth_dev);
 501 int cnxk_nix_timesync_enable(struct rte_eth_dev *eth_dev);
 502 int cnxk_nix_timesync_disable(struct rte_eth_dev *eth_dev);
 503 int cnxk_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev,
 504                                         struct timespec *timestamp,
 505                                         uint32_t flags);
 506 int cnxk_nix_timesync_read_tx_timestamp(struct rte_eth_dev *eth_dev,
 507                                         struct timespec *timestamp);
 508 int cnxk_nix_timesync_read_time(struct rte_eth_dev *eth_dev,
 509                                 struct timespec *ts);
 510 int cnxk_nix_timesync_write_time(struct rte_eth_dev *eth_dev,
 511                                  const struct timespec *ts);
 512 int cnxk_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta);
 513 int cnxk_nix_tsc_convert(struct cnxk_eth_dev *dev);
 514 int cnxk_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *clock);
 515
 516 uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev);
 517 int cnxk_nix_tm_ops_get(struct rte_eth_dev *eth_dev, void *ops);
 518 int cnxk_nix_tm_set_queue_rate_limit(struct rte_eth_dev *eth_dev,
 519                                      uint16_t queue_idx, uint16_t tx_rate);
 520
 521 /* MTR */
 522 int cnxk_nix_mtr_ops_get(struct rte_eth_dev *dev, void *ops);
 523
 524 /* RSS */
 525 uint32_t cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
 526                                 uint8_t rss_level);
 527 int cnxk_nix_reta_update(struct rte_eth_dev *eth_dev,
 528                          struct rte_eth_rss_reta_entry64 *reta_conf,
 529                          uint16_t reta_size);
 530 int cnxk_nix_reta_query(struct rte_eth_dev *eth_dev,
 531                         struct rte_eth_rss_reta_entry64 *reta_conf,
 532                         uint16_t reta_size);
 533 int cnxk_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
 534                              struct rte_eth_rss_conf *rss_conf);
 535 int cnxk_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
 536                                struct rte_eth_rss_conf *rss_conf);
 537
 538 /* Link */
 539 void cnxk_nix_toggle_flag_link_cfg(struct cnxk_eth_dev *dev, bool set);
 540 void cnxk_eth_dev_link_status_cb(struct roc_nix *nix,
 541                                  struct roc_nix_link_info *link);
 542 void cnxk_eth_dev_link_status_get_cb(struct roc_nix *nix,
 543                                      struct roc_nix_link_info *link);
 544 int cnxk_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
 545 int cnxk_nix_queue_stats_mapping(struct rte_eth_dev *dev, uint16_t queue_id,
 546                                  uint8_t stat_idx, uint8_t is_rx);
 547 int cnxk_nix_stats_reset(struct rte_eth_dev *dev);
 548 int cnxk_nix_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 549 int cnxk_nix_xstats_get(struct rte_eth_dev *eth_dev,
 550                         struct rte_eth_xstat *xstats, unsigned int n);
 551 int cnxk_nix_xstats_get_names(struct rte_eth_dev *eth_dev,
 552                               struct rte_eth_xstat_name *xstats_names,
 553                               unsigned int limit);
 554 int cnxk_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,
 555                                     const uint64_t *ids,
 556                                     struct rte_eth_xstat_name *xstats_names,
 557                                     unsigned int limit);
 558 int cnxk_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids,
 559                               uint64_t *values, unsigned int n);
 560 int cnxk_nix_xstats_reset(struct rte_eth_dev *eth_dev);
 561 int cnxk_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
 562                             size_t fw_size);
 563 void cnxk_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid,
 564                            struct rte_eth_rxq_info *qinfo);
 565 void cnxk_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid,
 566                            struct rte_eth_txq_info *qinfo);
 567
 568 /* Queue status */
 569 int cnxk_nix_rx_descriptor_status(void *rxq, uint16_t offset);
 570 int cnxk_nix_tx_descriptor_status(void *txq, uint16_t offset);
 571 uint32_t cnxk_nix_rx_queue_count(void *rxq);
 572
 573 /* Lookup configuration */
 574 const uint32_t *cnxk_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev);
 575 void *cnxk_nix_fastpath_lookup_mem_get(void);
 576
 577 /* Devargs */
 578 int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs,
 579                               struct cnxk_eth_dev *dev);
 580
 581 /* Debug */
 582 int cnxk_nix_dev_get_reg(struct rte_eth_dev *eth_dev,
 583                          struct rte_dev_reg_info *regs);
 584 /* Security */
 585 int cnxk_eth_outb_sa_idx_get(struct cnxk_eth_dev *dev, uint32_t *idx_p);
 586 int cnxk_eth_outb_sa_idx_put(struct cnxk_eth_dev *dev, uint32_t idx);
 587 int cnxk_nix_lookup_mem_sa_base_set(struct cnxk_eth_dev *dev);
 588 int cnxk_nix_lookup_mem_sa_base_clear(struct cnxk_eth_dev *dev);
 589 __rte_internal
 590 int cnxk_nix_inb_mode_set(struct cnxk_eth_dev *dev, bool use_inl_dev);
 591 struct cnxk_eth_sec_sess *cnxk_eth_sec_sess_get_by_spi(struct cnxk_eth_dev *dev,
 592                                                        uint32_t spi, bool inb);
 593 struct cnxk_eth_sec_sess *
 594 cnxk_eth_sec_sess_get_by_sess(struct cnxk_eth_dev *dev,
 595                               struct rte_security_session *sess);
 596
 597 /* Other private functions */
 598 int nix_recalc_mtu(struct rte_eth_dev *eth_dev);
 599 int nix_mtr_validate(struct rte_eth_dev *dev, uint32_t id);
 600 int nix_mtr_policy_act_get(struct rte_eth_dev *eth_dev, uint32_t id,
 601                            struct cnxk_mtr_policy_node **policy);
 602 int nix_mtr_rq_update(struct rte_eth_dev *eth_dev, uint32_t id,
 603                       uint32_t queue_num, const uint16_t *queue);
 604 int nix_mtr_chain_update(struct rte_eth_dev *eth_dev, uint32_t cur_id,
 605                          uint32_t prev_id, uint32_t next_id);
 606 int nix_mtr_chain_reset(struct rte_eth_dev *eth_dev, uint32_t cur_id);
 607 struct cnxk_meter_node *nix_get_mtr(struct rte_eth_dev *eth_dev,
 608                                     uint32_t cur_id);
 609 int nix_mtr_level_update(struct rte_eth_dev *eth_dev, uint32_t id,
 610                          uint32_t level);
 611 int nix_mtr_capabilities_init(struct rte_eth_dev *eth_dev);
 612 int nix_mtr_configure(struct rte_eth_dev *eth_dev, uint32_t id);
 613 int nix_mtr_connect(struct rte_eth_dev *eth_dev, uint32_t id);
 614 int nix_mtr_destroy(struct rte_eth_dev *eth_dev, uint32_t id,
 615                     struct rte_mtr_error *error);
 616 int nix_mtr_color_action_validate(struct rte_eth_dev *eth_dev, uint32_t id,
 617                                   uint32_t *prev_id, uint32_t *next_id,
 618                                   struct cnxk_mtr_policy_node *policy,
 619                                   int *tree_level);
 620
 621 /* Inlines */
 622 static __rte_always_inline uint64_t
 623 cnxk_pktmbuf_detach(struct rte_mbuf *m)
 624 {
 625         struct rte_mempool *mp = m->pool;
 626         uint32_t mbuf_size, buf_len;
 627         struct rte_mbuf *md;
 628         uint16_t priv_size;
 629         uint16_t refcount;
 630
 631         /* Update refcount of direct mbuf */
 632         md = rte_mbuf_from_indirect(m);
 633         refcount = rte_mbuf_refcnt_update(md, -1);
 634
 635         priv_size = rte_pktmbuf_priv_size(mp);
 636         mbuf_size = (uint32_t)(sizeof(struct rte_mbuf) + priv_size);
 637         buf_len = rte_pktmbuf_data_room_size(mp);
 638
 639         m->priv_size = priv_size;
 640         m->buf_addr = (char *)m + mbuf_size;
 641         m->buf_iova = rte_mempool_virt2iova(m) + mbuf_size;
 642         m->buf_len = (uint16_t)buf_len;
 643         rte_pktmbuf_reset_headroom(m);
 644         m->data_len = 0;
 645         m->ol_flags = 0;
 646         m->next = NULL;
 647         m->nb_segs = 1;
 648
 649         /* Now indirect mbuf is safe to free */
 650         rte_pktmbuf_free(m);
 651
 652         if (refcount == 0) {
 653                 rte_mbuf_refcnt_set(md, 1);
 654                 md->data_len = 0;
 655                 md->ol_flags = 0;
 656                 md->next = NULL;
 657                 md->nb_segs = 1;
 658                 return 0;
 659         } else {
 660                 return 1;
 661         }
 662 }
 663
 664 static __rte_always_inline uint64_t
 665 cnxk_nix_prefree_seg(struct rte_mbuf *m)
 666 {
 667         if (likely(rte_mbuf_refcnt_read(m) == 1)) {
 668                 if (!RTE_MBUF_DIRECT(m))
 669                         return cnxk_pktmbuf_detach(m);
 670
 671                 m->next = NULL;
 672                 m->nb_segs = 1;
 673                 return 0;
 674         } else if (rte_mbuf_refcnt_update(m, -1) == 0) {
 675                 if (!RTE_MBUF_DIRECT(m))
 676                         return cnxk_pktmbuf_detach(m);
 677
 678                 rte_mbuf_refcnt_set(m, 1);
 679                 m->next = NULL;
 680                 m->nb_segs = 1;
 681                 return 0;
 682         }
 683
 684         /* Mbuf is having refcount more than 1 so need not to be freed */
 685         return 1;
 686 }
 687
 688 static inline rte_mbuf_timestamp_t *
 689 cnxk_nix_timestamp_dynfield(struct rte_mbuf *mbuf,
 690                             struct cnxk_timesync_info *info)
 691 {
 692         return RTE_MBUF_DYNFIELD(mbuf, info->tstamp_dynfield_offset,
 693                                  rte_mbuf_timestamp_t *);
 694 }
 695
 696 static __rte_always_inline void
 697 cnxk_nix_mbuf_to_tstamp(struct rte_mbuf *mbuf,
 698                         struct cnxk_timesync_info *tstamp,
 699                         const uint8_t ts_enable, const uint8_t mseg_enable,
 700                         uint64_t *tstamp_ptr)
 701 {
 702         if (ts_enable) {
 703                 if (!mseg_enable) {
 704                         mbuf->pkt_len -= CNXK_NIX_TIMESYNC_RX_OFFSET;
 705                         mbuf->data_len -= CNXK_NIX_TIMESYNC_RX_OFFSET;
 706                 }
 707
 708                 /* Reading the rx timestamp inserted by CGX, viz at
 709                  * starting of the packet data.
 710                  */
 711                 *cnxk_nix_timestamp_dynfield(mbuf, tstamp) =
 712                         rte_be_to_cpu_64(*tstamp_ptr);
 713                 /* RTE_MBUF_F_RX_IEEE1588_TMST flag needs to be set only in case
 714                  * PTP packets are received.
 715                  */
 716                 if (mbuf->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC) {
 717                         tstamp->rx_tstamp =
 718                                 *cnxk_nix_timestamp_dynfield(mbuf, tstamp);
 719                         tstamp->rx_ready = 1;
 720                         mbuf->ol_flags |= RTE_MBUF_F_RX_IEEE1588_PTP |
 721                                           RTE_MBUF_F_RX_IEEE1588_TMST |
 722                                           tstamp->rx_tstamp_dynflag;
 723                 }
 724         }
 725 }
 726
 727 static __rte_always_inline uintptr_t
 728 cnxk_nix_sa_base_get(uint16_t port, const void *lookup_mem)
 729 {
 730         uintptr_t sa_base_tbl;
 731
 732         sa_base_tbl = (uintptr_t)lookup_mem;
 733         sa_base_tbl += PTYPE_ARRAY_SZ + ERR_ARRAY_SZ;
 734         return *((const uintptr_t *)sa_base_tbl + port);
 735 }
 736
 737 #endif /* __CNXK_ETHDEV_H__ */