1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
4 #ifndef __CNXK_ETHDEV_H__
5 #define __CNXK_ETHDEV_H__
10 #include <ethdev_driver.h>
11 #include <ethdev_pci.h>
12 #include <rte_kvargs.h>
14 #include <rte_mbuf_pool_ops.h>
15 #include <rte_mempool.h>
16 #include <rte_security.h>
17 #include <rte_security_driver.h>
18 #include <rte_tailq.h>
23 #define CNXK_ETH_DEV_PMD_VERSION "1.0"
25 /* Used for struct cnxk_eth_dev::flags */
26 #define CNXK_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
28 /* VLAN tag inserted by NIX_TX_VTAG_ACTION.
29 * In Tx space is always reserved for this in FRS.
31 #define CNXK_NIX_MAX_VTAG_INS 2
32 #define CNXK_NIX_MAX_VTAG_ACT_SIZE (4 * CNXK_NIX_MAX_VTAG_INS)
34 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
35 #define CNXK_NIX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + \
37 CNXK_NIX_MAX_VTAG_ACT_SIZE)
39 #define CNXK_NIX_RX_MIN_DESC 16
40 #define CNXK_NIX_RX_MIN_DESC_ALIGN 16
41 #define CNXK_NIX_RX_NB_SEG_MAX 6
42 #define CNXK_NIX_RX_DEFAULT_RING_SZ 4096
43 /* Max supported SQB count */
44 #define CNXK_NIX_TX_MAX_SQB 512
46 /* If PTP is enabled additional SEND MEM DESC is required which
47 * takes 2 words, hence max 7 iova address are possible
49 #if defined(RTE_LIBRTE_IEEE1588)
50 #define CNXK_NIX_TX_NB_SEG_MAX 7
52 #define CNXK_NIX_TX_NB_SEG_MAX 9
55 #define CNXK_NIX_TX_MSEG_SG_DWORDS \
56 ((RTE_ALIGN_MUL_CEIL(CNXK_NIX_TX_NB_SEG_MAX, 3) / 3) + \
57 CNXK_NIX_TX_NB_SEG_MAX)
59 #define CNXK_NIX_RSS_L3_L4_SRC_DST \
60 (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | ETH_RSS_L4_SRC_ONLY | \
63 #define CNXK_NIX_RSS_OFFLOAD \
64 (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP | \
65 ETH_RSS_SCTP | ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD | \
66 CNXK_NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | ETH_RSS_C_VLAN)
68 #define CNXK_NIX_TX_OFFLOAD_CAPA \
69 (DEV_TX_OFFLOAD_MBUF_FAST_FREE | DEV_TX_OFFLOAD_MT_LOCKFREE | \
70 DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT | \
71 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \
72 DEV_TX_OFFLOAD_TCP_CKSUM | DEV_TX_OFFLOAD_UDP_CKSUM | \
73 DEV_TX_OFFLOAD_SCTP_CKSUM | DEV_TX_OFFLOAD_TCP_TSO | \
74 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
75 DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_MULTI_SEGS | \
76 DEV_TX_OFFLOAD_IPV4_CKSUM | DEV_TX_OFFLOAD_SECURITY)
78 #define CNXK_NIX_RX_OFFLOAD_CAPA \
79 (DEV_RX_OFFLOAD_CHECKSUM | DEV_RX_OFFLOAD_SCTP_CKSUM | \
80 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_SCATTER | \
81 DEV_RX_OFFLOAD_JUMBO_FRAME | DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \
82 DEV_RX_OFFLOAD_RSS_HASH | DEV_RX_OFFLOAD_TIMESTAMP | \
83 DEV_RX_OFFLOAD_VLAN_STRIP | DEV_RX_OFFLOAD_SECURITY)
85 #define RSS_IPV4_ENABLE \
86 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_UDP | \
87 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_SCTP)
89 #define RSS_IPV6_ENABLE \
90 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_UDP | \
91 ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_NONFRAG_IPV6_SCTP)
93 #define RSS_IPV6_EX_ENABLE \
94 (ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | ETH_RSS_IPV6_UDP_EX)
96 #define RSS_MAX_LEVELS 3
98 #define RSS_IPV4_INDEX 0
99 #define RSS_IPV6_INDEX 1
100 #define RSS_TCP_INDEX 2
101 #define RSS_UDP_INDEX 3
102 #define RSS_SCTP_INDEX 4
103 #define RSS_DMAC_INDEX 5
105 /* Default mark value used when none is provided. */
106 #define CNXK_FLOW_ACTION_FLAG_DEFAULT 0xffff
108 /* Default cycle counter mask */
109 #define CNXK_CYCLECOUNTER_MASK 0xffffffffffffffffULL
110 #define CNXK_NIX_TIMESYNC_RX_OFFSET 8
112 #define PTYPE_NON_TUNNEL_WIDTH 16
113 #define PTYPE_TUNNEL_WIDTH 12
114 #define PTYPE_NON_TUNNEL_ARRAY_SZ BIT(PTYPE_NON_TUNNEL_WIDTH)
115 #define PTYPE_TUNNEL_ARRAY_SZ BIT(PTYPE_TUNNEL_WIDTH)
116 #define PTYPE_ARRAY_SZ \
117 ((PTYPE_NON_TUNNEL_ARRAY_SZ + PTYPE_TUNNEL_ARRAY_SZ) * sizeof(uint16_t))
119 /* NIX_RX_PARSE_S's ERRCODE + ERRLEV (12 bits) */
120 #define ERRCODE_ERRLEN_WIDTH 12
121 #define ERR_ARRAY_SZ ((BIT(ERRCODE_ERRLEN_WIDTH)) * sizeof(uint32_t))
123 /* Fastpath lookup */
124 #define CNXK_NIX_FASTPATH_LOOKUP_MEM "cnxk_nix_fastpath_lookup_mem"
126 #define CNXK_NIX_UDP_TUN_BITMASK \
127 ((1ull << (PKT_TX_TUNNEL_VXLAN >> 45)) | \
128 (1ull << (PKT_TX_TUNNEL_GENEVE >> 45)))
130 /* Subtype from inline outbound error event */
131 #define CNXK_ETHDEV_SEC_OUTB_EV_SUB 0xFFUL
133 /* SPI will be in 20 bits of tag */
134 #define CNXK_ETHDEV_SPI_TAG_MASK 0xFFFFFUL
137 enum rte_eth_fc_mode mode;
142 struct cnxk_eth_qconf {
144 struct rte_eth_txconf tx;
145 struct rte_eth_rxconf rx;
147 struct rte_mempool *mp;
152 struct cnxk_timesync_info {
155 uint64_t rx_tstamp_dynflag;
156 int tstamp_dynfield_offset;
157 rte_iova_t tx_tstamp_iova;
159 } __plt_cache_aligned;
161 /* Security session private data */
162 struct cnxk_eth_sec_sess {
164 TAILQ_ENTRY(cnxk_eth_sec_sess) entry;
166 /* Inbound SA is from NIX_RX_IPSEC_SA_BASE or
167 * Outbound SA from roc_nix_inl_outb_sa_base_get()
177 /* Back pointer to session */
178 struct rte_security_session *sess;
183 /* Inbound session on inl dev */
187 TAILQ_HEAD(cnxk_eth_sec_sess_list, cnxk_eth_sec_sess);
189 /* Inbound security data */
190 struct cnxk_eth_dev_sec_inb {
191 /* IPSec inbound max SPI */
194 /* Using inbound with inline device */
197 /* Device argument to force inline device for inb */
200 /* Active sessions */
203 /* List of sessions */
204 struct cnxk_eth_sec_sess_list list;
207 /* Outbound security data */
208 struct cnxk_eth_dev_sec_outb {
209 /* IPSec outbound max SA */
212 /* Per CPT LF descriptor count */
216 struct plt_bitmap *sa_bmap;
218 /* SA bitmap memory */
225 struct roc_cpt_lf *lf_base;
227 /* Crypto queues => CPT lf count */
228 uint16_t nb_crypto_qs;
230 /* Active sessions */
233 /* List of sessions */
234 struct cnxk_eth_sec_sess_list list;
237 struct cnxk_eth_dev {
244 /* ROC RQs, SQs and CQs */
245 struct roc_nix_rq *rqs;
246 struct roc_nix_sq *sqs;
247 struct roc_nix_cq *cqs;
249 /* Configured queue count */
255 /* Max macfilter entries */
256 uint8_t dmac_filter_count;
257 uint8_t max_mac_entries;
258 bool dmac_filter_enable;
261 uint8_t ptype_disable;
265 /* Pointer back to rte */
266 struct rte_eth_dev *eth_dev;
268 /* HW capabilities / Limitations */
271 uint64_t cq_min_4k : 1;
272 uint64_t ipsecd_drop_re_dis : 1;
277 /* Rx and Tx offload capabilities */
278 uint64_t rx_offload_capa;
279 uint64_t tx_offload_capa;
281 /* Configured Rx and Tx offloads */
282 uint64_t rx_offloads;
283 uint64_t tx_offloads;
284 /* Platform specific offload flags */
285 uint16_t rx_offload_flags;
286 uint16_t tx_offload_flags;
288 /* ETHDEV RSS HF bitmask */
289 uint64_t ethdev_rss_hf;
291 /* Saved qconf before lf realloc */
292 struct cnxk_eth_qconf *tx_qconf;
293 struct cnxk_eth_qconf *rx_qconf;
295 /* Flow control configuration */
296 struct cnxk_fc_cfg fc_cfg;
299 struct cnxk_timesync_info tstamp;
300 struct rte_timecounter systime_tc;
301 struct rte_timecounter rx_tstamp_tc;
302 struct rte_timecounter tx_tstamp_tc;
303 double clk_freq_mult;
306 /* Rx burst for cleanup(Only Primary) */
307 eth_rx_burst_t rx_pkt_burst_no_offload;
309 /* Default mac address */
310 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
312 /* LSO Tunnel format indices */
313 uint64_t lso_tun_fmt;
315 /* Per queue statistics counters */
316 uint32_t txq_stat_map[RTE_ETHDEV_QUEUE_STAT_CNTRS];
317 uint32_t rxq_stat_map[RTE_ETHDEV_QUEUE_STAT_CNTRS];
320 struct cnxk_eth_dev_sec_inb inb;
321 struct cnxk_eth_dev_sec_outb outb;
324 struct cnxk_eth_rxq_sp {
325 struct cnxk_eth_dev *dev;
326 struct cnxk_eth_qconf qconf;
328 } __plt_cache_aligned;
330 struct cnxk_eth_txq_sp {
331 struct cnxk_eth_dev *dev;
332 struct cnxk_eth_qconf qconf;
334 } __plt_cache_aligned;
336 static inline struct cnxk_eth_dev *
337 cnxk_eth_pmd_priv(const struct rte_eth_dev *eth_dev)
339 return eth_dev->data->dev_private;
342 static inline struct cnxk_eth_rxq_sp *
343 cnxk_eth_rxq_to_sp(void *__rxq)
345 return ((struct cnxk_eth_rxq_sp *)__rxq) - 1;
348 static inline struct cnxk_eth_txq_sp *
349 cnxk_eth_txq_to_sp(void *__txq)
351 return ((struct cnxk_eth_txq_sp *)__txq) - 1;
354 /* Common ethdev ops */
355 extern struct eth_dev_ops cnxk_eth_dev_ops;
357 /* Common flow ops */
358 extern struct rte_flow_ops cnxk_flow_ops;
360 /* Common security ops */
361 extern struct rte_security_ops cnxk_eth_sec_ops;
364 int cnxk_nix_probe(struct rte_pci_driver *pci_drv,
365 struct rte_pci_device *pci_dev);
366 int cnxk_nix_remove(struct rte_pci_device *pci_dev);
367 int cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
368 int cnxk_nix_mc_addr_list_configure(struct rte_eth_dev *eth_dev,
369 struct rte_ether_addr *mc_addr_set,
370 uint32_t nb_mc_addr);
371 int cnxk_nix_mac_addr_add(struct rte_eth_dev *eth_dev,
372 struct rte_ether_addr *addr, uint32_t index,
374 void cnxk_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index);
375 int cnxk_nix_mac_addr_set(struct rte_eth_dev *eth_dev,
376 struct rte_ether_addr *addr);
377 int cnxk_nix_promisc_enable(struct rte_eth_dev *eth_dev);
378 int cnxk_nix_promisc_disable(struct rte_eth_dev *eth_dev);
379 int cnxk_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);
380 int cnxk_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);
381 int cnxk_nix_info_get(struct rte_eth_dev *eth_dev,
382 struct rte_eth_dev_info *dev_info);
383 int cnxk_nix_rx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
384 struct rte_eth_burst_mode *mode);
385 int cnxk_nix_tx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
386 struct rte_eth_burst_mode *mode);
387 int cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
388 struct rte_eth_fc_conf *fc_conf);
389 int cnxk_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
390 struct rte_eth_fc_conf *fc_conf);
391 int cnxk_nix_set_link_up(struct rte_eth_dev *eth_dev);
392 int cnxk_nix_set_link_down(struct rte_eth_dev *eth_dev);
393 int cnxk_nix_get_module_info(struct rte_eth_dev *eth_dev,
394 struct rte_eth_dev_module_info *modinfo);
395 int cnxk_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
396 struct rte_dev_eeprom_info *info);
397 int cnxk_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
398 uint16_t rx_queue_id);
399 int cnxk_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
400 uint16_t rx_queue_id);
401 int cnxk_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool);
402 int cnxk_nix_tx_done_cleanup(void *txq, uint32_t free_cnt);
403 int cnxk_nix_flow_ops_get(struct rte_eth_dev *eth_dev,
404 const struct rte_flow_ops **ops);
405 int cnxk_nix_configure(struct rte_eth_dev *eth_dev);
406 int cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
407 uint16_t nb_desc, uint16_t fp_tx_q_sz,
408 const struct rte_eth_txconf *tx_conf);
409 int cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
410 uint16_t nb_desc, uint16_t fp_rx_q_sz,
411 const struct rte_eth_rxconf *rx_conf,
412 struct rte_mempool *mp);
413 int cnxk_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid);
414 int cnxk_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid);
415 int cnxk_nix_dev_start(struct rte_eth_dev *eth_dev);
416 int cnxk_nix_timesync_enable(struct rte_eth_dev *eth_dev);
417 int cnxk_nix_timesync_disable(struct rte_eth_dev *eth_dev);
418 int cnxk_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev,
419 struct timespec *timestamp,
421 int cnxk_nix_timesync_read_tx_timestamp(struct rte_eth_dev *eth_dev,
422 struct timespec *timestamp);
423 int cnxk_nix_timesync_read_time(struct rte_eth_dev *eth_dev,
424 struct timespec *ts);
425 int cnxk_nix_timesync_write_time(struct rte_eth_dev *eth_dev,
426 const struct timespec *ts);
427 int cnxk_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta);
428 int cnxk_nix_tsc_convert(struct cnxk_eth_dev *dev);
429 int cnxk_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *clock);
431 uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev);
432 int cnxk_nix_tm_ops_get(struct rte_eth_dev *eth_dev, void *ops);
433 int cnxk_nix_tm_set_queue_rate_limit(struct rte_eth_dev *eth_dev,
434 uint16_t queue_idx, uint16_t tx_rate);
437 uint32_t cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
439 int cnxk_nix_reta_update(struct rte_eth_dev *eth_dev,
440 struct rte_eth_rss_reta_entry64 *reta_conf,
442 int cnxk_nix_reta_query(struct rte_eth_dev *eth_dev,
443 struct rte_eth_rss_reta_entry64 *reta_conf,
445 int cnxk_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
446 struct rte_eth_rss_conf *rss_conf);
447 int cnxk_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
448 struct rte_eth_rss_conf *rss_conf);
451 void cnxk_nix_toggle_flag_link_cfg(struct cnxk_eth_dev *dev, bool set);
452 void cnxk_eth_dev_link_status_cb(struct roc_nix *nix,
453 struct roc_nix_link_info *link);
454 void cnxk_eth_dev_link_status_get_cb(struct roc_nix *nix,
455 struct roc_nix_link_info *link);
456 int cnxk_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
457 int cnxk_nix_queue_stats_mapping(struct rte_eth_dev *dev, uint16_t queue_id,
458 uint8_t stat_idx, uint8_t is_rx);
459 int cnxk_nix_stats_reset(struct rte_eth_dev *dev);
460 int cnxk_nix_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
461 int cnxk_nix_xstats_get(struct rte_eth_dev *eth_dev,
462 struct rte_eth_xstat *xstats, unsigned int n);
463 int cnxk_nix_xstats_get_names(struct rte_eth_dev *eth_dev,
464 struct rte_eth_xstat_name *xstats_names,
466 int cnxk_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,
468 struct rte_eth_xstat_name *xstats_names,
470 int cnxk_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids,
471 uint64_t *values, unsigned int n);
472 int cnxk_nix_xstats_reset(struct rte_eth_dev *eth_dev);
473 int cnxk_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
475 void cnxk_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid,
476 struct rte_eth_rxq_info *qinfo);
477 void cnxk_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid,
478 struct rte_eth_txq_info *qinfo);
480 /* Lookup configuration */
481 const uint32_t *cnxk_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev);
482 void *cnxk_nix_fastpath_lookup_mem_get(void);
485 int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs,
486 struct cnxk_eth_dev *dev);
489 int cnxk_nix_dev_get_reg(struct rte_eth_dev *eth_dev,
490 struct rte_dev_reg_info *regs);
492 int cnxk_eth_outb_sa_idx_get(struct cnxk_eth_dev *dev, uint32_t *idx_p);
493 int cnxk_eth_outb_sa_idx_put(struct cnxk_eth_dev *dev, uint32_t idx);
494 int cnxk_nix_lookup_mem_sa_base_set(struct cnxk_eth_dev *dev);
495 int cnxk_nix_lookup_mem_sa_base_clear(struct cnxk_eth_dev *dev);
497 int cnxk_nix_inb_mode_set(struct cnxk_eth_dev *dev, bool use_inl_dev);
498 struct cnxk_eth_sec_sess *cnxk_eth_sec_sess_get_by_spi(struct cnxk_eth_dev *dev,
499 uint32_t spi, bool inb);
500 struct cnxk_eth_sec_sess *
501 cnxk_eth_sec_sess_get_by_sess(struct cnxk_eth_dev *dev,
502 struct rte_security_session *sess);
504 /* Other private functions */
505 int nix_recalc_mtu(struct rte_eth_dev *eth_dev);
508 static __rte_always_inline uint64_t
509 cnxk_pktmbuf_detach(struct rte_mbuf *m)
511 struct rte_mempool *mp = m->pool;
512 uint32_t mbuf_size, buf_len;
517 /* Update refcount of direct mbuf */
518 md = rte_mbuf_from_indirect(m);
519 refcount = rte_mbuf_refcnt_update(md, -1);
521 priv_size = rte_pktmbuf_priv_size(mp);
522 mbuf_size = (uint32_t)(sizeof(struct rte_mbuf) + priv_size);
523 buf_len = rte_pktmbuf_data_room_size(mp);
525 m->priv_size = priv_size;
526 m->buf_addr = (char *)m + mbuf_size;
527 m->buf_iova = rte_mempool_virt2iova(m) + mbuf_size;
528 m->buf_len = (uint16_t)buf_len;
529 rte_pktmbuf_reset_headroom(m);
535 /* Now indirect mbuf is safe to free */
539 rte_mbuf_refcnt_set(md, 1);
550 static __rte_always_inline uint64_t
551 cnxk_nix_prefree_seg(struct rte_mbuf *m)
553 if (likely(rte_mbuf_refcnt_read(m) == 1)) {
554 if (!RTE_MBUF_DIRECT(m))
555 return cnxk_pktmbuf_detach(m);
560 } else if (rte_mbuf_refcnt_update(m, -1) == 0) {
561 if (!RTE_MBUF_DIRECT(m))
562 return cnxk_pktmbuf_detach(m);
564 rte_mbuf_refcnt_set(m, 1);
570 /* Mbuf is having refcount more than 1 so need not to be freed */
574 static inline rte_mbuf_timestamp_t *
575 cnxk_nix_timestamp_dynfield(struct rte_mbuf *mbuf,
576 struct cnxk_timesync_info *info)
578 return RTE_MBUF_DYNFIELD(mbuf, info->tstamp_dynfield_offset,
579 rte_mbuf_timestamp_t *);
582 static __rte_always_inline void
583 cnxk_nix_mbuf_to_tstamp(struct rte_mbuf *mbuf,
584 struct cnxk_timesync_info *tstamp,
585 const uint8_t ts_enable, const uint8_t mseg_enable,
586 uint64_t *tstamp_ptr)
590 mbuf->pkt_len -= CNXK_NIX_TIMESYNC_RX_OFFSET;
591 mbuf->data_len -= CNXK_NIX_TIMESYNC_RX_OFFSET;
594 /* Reading the rx timestamp inserted by CGX, viz at
595 * starting of the packet data.
597 *cnxk_nix_timestamp_dynfield(mbuf, tstamp) =
598 rte_be_to_cpu_64(*tstamp_ptr);
599 /* PKT_RX_IEEE1588_TMST flag needs to be set only in case
600 * PTP packets are received.
602 if (mbuf->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC) {
604 *cnxk_nix_timestamp_dynfield(mbuf, tstamp);
605 tstamp->rx_ready = 1;
606 mbuf->ol_flags |= PKT_RX_IEEE1588_PTP |
607 PKT_RX_IEEE1588_TMST |
608 tstamp->rx_tstamp_dynflag;
613 static __rte_always_inline uintptr_t
614 cnxk_nix_sa_base_get(uint16_t port, const void *lookup_mem)
616 uintptr_t sa_base_tbl;
618 sa_base_tbl = (uintptr_t)lookup_mem;
619 sa_base_tbl += PTYPE_ARRAY_SZ + ERR_ARRAY_SZ;
620 return *((const uintptr_t *)sa_base_tbl + port);
623 #endif /* __CNXK_ETHDEV_H__ */