1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
4 #ifndef __CNXK_ETHDEV_H__
5 #define __CNXK_ETHDEV_H__
10 #include <ethdev_driver.h>
11 #include <ethdev_pci.h>
12 #include <rte_kvargs.h>
14 #include <rte_mbuf_pool_ops.h>
15 #include <rte_mempool.h>
19 #define CNXK_ETH_DEV_PMD_VERSION "1.0"
21 /* Used for struct cnxk_eth_dev::flags */
22 #define CNXK_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
24 /* VLAN tag inserted by NIX_TX_VTAG_ACTION.
25 * In Tx space is always reserved for this in FRS.
27 #define CNXK_NIX_MAX_VTAG_INS 2
28 #define CNXK_NIX_MAX_VTAG_ACT_SIZE (4 * CNXK_NIX_MAX_VTAG_INS)
30 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
31 #define CNXK_NIX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + \
33 CNXK_NIX_MAX_VTAG_ACT_SIZE)
35 #define CNXK_NIX_RX_MIN_DESC 16
36 #define CNXK_NIX_RX_MIN_DESC_ALIGN 16
37 #define CNXK_NIX_RX_NB_SEG_MAX 6
38 #define CNXK_NIX_RX_DEFAULT_RING_SZ 4096
39 /* Max supported SQB count */
40 #define CNXK_NIX_TX_MAX_SQB 512
42 /* If PTP is enabled additional SEND MEM DESC is required which
43 * takes 2 words, hence max 7 iova address are possible
45 #if defined(RTE_LIBRTE_IEEE1588)
46 #define CNXK_NIX_TX_NB_SEG_MAX 7
48 #define CNXK_NIX_TX_NB_SEG_MAX 9
51 #define CNXK_NIX_TX_MSEG_SG_DWORDS \
52 ((RTE_ALIGN_MUL_CEIL(CNXK_NIX_TX_NB_SEG_MAX, 3) / 3) + \
53 CNXK_NIX_TX_NB_SEG_MAX)
55 #define CNXK_NIX_RSS_L3_L4_SRC_DST \
56 (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | ETH_RSS_L4_SRC_ONLY | \
59 #define CNXK_NIX_RSS_OFFLOAD \
60 (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP | \
61 ETH_RSS_SCTP | ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD | \
62 CNXK_NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | ETH_RSS_C_VLAN)
64 #define CNXK_NIX_TX_OFFLOAD_CAPA \
65 (DEV_TX_OFFLOAD_MBUF_FAST_FREE | DEV_TX_OFFLOAD_MT_LOCKFREE | \
66 DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT | \
67 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \
68 DEV_TX_OFFLOAD_TCP_CKSUM | DEV_TX_OFFLOAD_UDP_CKSUM | \
69 DEV_TX_OFFLOAD_SCTP_CKSUM | DEV_TX_OFFLOAD_TCP_TSO | \
70 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
71 DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_MULTI_SEGS | \
72 DEV_TX_OFFLOAD_IPV4_CKSUM)
74 #define CNXK_NIX_RX_OFFLOAD_CAPA \
75 (DEV_RX_OFFLOAD_CHECKSUM | DEV_RX_OFFLOAD_SCTP_CKSUM | \
76 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_SCATTER | \
77 DEV_RX_OFFLOAD_JUMBO_FRAME | DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \
78 DEV_RX_OFFLOAD_RSS_HASH)
80 #define RSS_IPV4_ENABLE \
81 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_UDP | \
82 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_SCTP)
84 #define RSS_IPV6_ENABLE \
85 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_UDP | \
86 ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_NONFRAG_IPV6_SCTP)
88 #define RSS_IPV6_EX_ENABLE \
89 (ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | ETH_RSS_IPV6_UDP_EX)
91 #define RSS_MAX_LEVELS 3
93 #define RSS_IPV4_INDEX 0
94 #define RSS_IPV6_INDEX 1
95 #define RSS_TCP_INDEX 2
96 #define RSS_UDP_INDEX 3
97 #define RSS_SCTP_INDEX 4
98 #define RSS_DMAC_INDEX 5
100 /* Default mark value used when none is provided. */
101 #define CNXK_FLOW_ACTION_FLAG_DEFAULT 0xffff
103 #define PTYPE_NON_TUNNEL_WIDTH 16
104 #define PTYPE_TUNNEL_WIDTH 12
105 #define PTYPE_NON_TUNNEL_ARRAY_SZ BIT(PTYPE_NON_TUNNEL_WIDTH)
106 #define PTYPE_TUNNEL_ARRAY_SZ BIT(PTYPE_TUNNEL_WIDTH)
107 #define PTYPE_ARRAY_SZ \
108 ((PTYPE_NON_TUNNEL_ARRAY_SZ + PTYPE_TUNNEL_ARRAY_SZ) * sizeof(uint16_t))
109 /* Fastpath lookup */
110 #define CNXK_NIX_FASTPATH_LOOKUP_MEM "cnxk_nix_fastpath_lookup_mem"
112 #define CNXK_NIX_UDP_TUN_BITMASK \
113 ((1ull << (PKT_TX_TUNNEL_VXLAN >> 45)) | \
114 (1ull << (PKT_TX_TUNNEL_GENEVE >> 45)))
116 struct cnxk_eth_qconf {
118 struct rte_eth_txconf tx;
119 struct rte_eth_rxconf rx;
121 struct rte_mempool *mp;
126 struct cnxk_eth_dev {
130 /* ROC RQs, SQs and CQs */
131 struct roc_nix_rq *rqs;
132 struct roc_nix_sq *sqs;
133 struct roc_nix_cq *cqs;
135 /* Configured queue count */
140 /* Max macfilter entries */
141 uint8_t max_mac_entries;
142 bool dmac_filter_enable;
145 uint8_t ptype_disable;
148 /* Pointer back to rte */
149 struct rte_eth_dev *eth_dev;
151 /* HW capabilities / Limitations */
154 uint64_t cq_min_4k : 1;
159 /* Rx and Tx offload capabilities */
160 uint64_t rx_offload_capa;
161 uint64_t tx_offload_capa;
163 /* Configured Rx and Tx offloads */
164 uint64_t rx_offloads;
165 uint64_t tx_offloads;
166 /* Platform specific offload flags */
167 uint16_t rx_offload_flags;
168 uint16_t tx_offload_flags;
170 /* ETHDEV RSS HF bitmask */
171 uint64_t ethdev_rss_hf;
173 /* Saved qconf before lf realloc */
174 struct cnxk_eth_qconf *tx_qconf;
175 struct cnxk_eth_qconf *rx_qconf;
177 /* Rx burst for cleanup(Only Primary) */
178 eth_rx_burst_t rx_pkt_burst_no_offload;
180 /* Default mac address */
181 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
183 /* LSO Tunnel format indices */
184 uint64_t lso_tun_fmt;
187 struct cnxk_eth_rxq_sp {
188 struct cnxk_eth_dev *dev;
189 struct cnxk_eth_qconf qconf;
191 } __plt_cache_aligned;
193 struct cnxk_eth_txq_sp {
194 struct cnxk_eth_dev *dev;
195 struct cnxk_eth_qconf qconf;
197 } __plt_cache_aligned;
199 static inline struct cnxk_eth_dev *
200 cnxk_eth_pmd_priv(struct rte_eth_dev *eth_dev)
202 return eth_dev->data->dev_private;
205 static inline struct cnxk_eth_rxq_sp *
206 cnxk_eth_rxq_to_sp(void *__rxq)
208 return ((struct cnxk_eth_rxq_sp *)__rxq) - 1;
211 static inline struct cnxk_eth_txq_sp *
212 cnxk_eth_txq_to_sp(void *__txq)
214 return ((struct cnxk_eth_txq_sp *)__txq) - 1;
217 /* Common ethdev ops */
218 extern struct eth_dev_ops cnxk_eth_dev_ops;
221 int cnxk_nix_probe(struct rte_pci_driver *pci_drv,
222 struct rte_pci_device *pci_dev);
223 int cnxk_nix_remove(struct rte_pci_device *pci_dev);
224 int cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
225 int cnxk_nix_mac_addr_add(struct rte_eth_dev *eth_dev,
226 struct rte_ether_addr *addr, uint32_t index,
228 void cnxk_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index);
229 int cnxk_nix_mac_addr_set(struct rte_eth_dev *eth_dev,
230 struct rte_ether_addr *addr);
231 int cnxk_nix_promisc_enable(struct rte_eth_dev *eth_dev);
232 int cnxk_nix_promisc_disable(struct rte_eth_dev *eth_dev);
233 int cnxk_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);
234 int cnxk_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);
235 int cnxk_nix_info_get(struct rte_eth_dev *eth_dev,
236 struct rte_eth_dev_info *dev_info);
237 int cnxk_nix_configure(struct rte_eth_dev *eth_dev);
238 int cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
239 uint16_t nb_desc, uint16_t fp_tx_q_sz,
240 const struct rte_eth_txconf *tx_conf);
241 int cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
242 uint16_t nb_desc, uint16_t fp_rx_q_sz,
243 const struct rte_eth_rxconf *rx_conf,
244 struct rte_mempool *mp);
245 int cnxk_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid);
246 int cnxk_nix_dev_start(struct rte_eth_dev *eth_dev);
248 uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev);
251 uint32_t cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
255 void cnxk_nix_toggle_flag_link_cfg(struct cnxk_eth_dev *dev, bool set);
256 void cnxk_eth_dev_link_status_cb(struct roc_nix *nix,
257 struct roc_nix_link_info *link);
258 int cnxk_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
260 /* Lookup configuration */
261 const uint32_t *cnxk_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev);
262 void *cnxk_nix_fastpath_lookup_mem_get(void);
265 int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs,
266 struct cnxk_eth_dev *dev);
269 static __rte_always_inline uint64_t
270 cnxk_pktmbuf_detach(struct rte_mbuf *m)
272 struct rte_mempool *mp = m->pool;
273 uint32_t mbuf_size, buf_len;
278 /* Update refcount of direct mbuf */
279 md = rte_mbuf_from_indirect(m);
280 refcount = rte_mbuf_refcnt_update(md, -1);
282 priv_size = rte_pktmbuf_priv_size(mp);
283 mbuf_size = (uint32_t)(sizeof(struct rte_mbuf) + priv_size);
284 buf_len = rte_pktmbuf_data_room_size(mp);
286 m->priv_size = priv_size;
287 m->buf_addr = (char *)m + mbuf_size;
288 m->buf_iova = rte_mempool_virt2iova(m) + mbuf_size;
289 m->buf_len = (uint16_t)buf_len;
290 rte_pktmbuf_reset_headroom(m);
296 /* Now indirect mbuf is safe to free */
300 rte_mbuf_refcnt_set(md, 1);
311 static __rte_always_inline uint64_t
312 cnxk_nix_prefree_seg(struct rte_mbuf *m)
314 if (likely(rte_mbuf_refcnt_read(m) == 1)) {
315 if (!RTE_MBUF_DIRECT(m))
316 return cnxk_pktmbuf_detach(m);
321 } else if (rte_mbuf_refcnt_update(m, -1) == 0) {
322 if (!RTE_MBUF_DIRECT(m))
323 return cnxk_pktmbuf_detach(m);
325 rte_mbuf_refcnt_set(m, 1);
331 /* Mbuf is having refcount more than 1 so need not to be freed */
335 #endif /* __CNXK_ETHDEV_H__ */