1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
4 #ifndef __CNXK_ETHDEV_H__
5 #define __CNXK_ETHDEV_H__
10 #include <ethdev_driver.h>
11 #include <ethdev_pci.h>
12 #include <rte_kvargs.h>
14 #include <rte_mbuf_pool_ops.h>
15 #include <rte_mempool.h>
19 #define CNXK_ETH_DEV_PMD_VERSION "1.0"
21 /* Used for struct cnxk_eth_dev::flags */
22 #define CNXK_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
24 /* VLAN tag inserted by NIX_TX_VTAG_ACTION.
25 * In Tx space is always reserved for this in FRS.
27 #define CNXK_NIX_MAX_VTAG_INS 2
28 #define CNXK_NIX_MAX_VTAG_ACT_SIZE (4 * CNXK_NIX_MAX_VTAG_INS)
30 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
31 #define CNXK_NIX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + \
33 CNXK_NIX_MAX_VTAG_ACT_SIZE)
35 #define CNXK_NIX_RX_MIN_DESC 16
36 #define CNXK_NIX_RX_MIN_DESC_ALIGN 16
37 #define CNXK_NIX_RX_NB_SEG_MAX 6
38 #define CNXK_NIX_RX_DEFAULT_RING_SZ 4096
39 /* Max supported SQB count */
40 #define CNXK_NIX_TX_MAX_SQB 512
42 /* If PTP is enabled additional SEND MEM DESC is required which
43 * takes 2 words, hence max 7 iova address are possible
45 #if defined(RTE_LIBRTE_IEEE1588)
46 #define CNXK_NIX_TX_NB_SEG_MAX 7
48 #define CNXK_NIX_TX_NB_SEG_MAX 9
51 #define CNXK_NIX_TX_MSEG_SG_DWORDS \
52 ((RTE_ALIGN_MUL_CEIL(CNXK_NIX_TX_NB_SEG_MAX, 3) / 3) + \
53 CNXK_NIX_TX_NB_SEG_MAX)
55 #define CNXK_NIX_RSS_L3_L4_SRC_DST \
56 (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | ETH_RSS_L4_SRC_ONLY | \
59 #define CNXK_NIX_RSS_OFFLOAD \
60 (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP | \
61 ETH_RSS_SCTP | ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD | \
62 CNXK_NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | ETH_RSS_C_VLAN)
64 #define CNXK_NIX_TX_OFFLOAD_CAPA \
65 (DEV_TX_OFFLOAD_MBUF_FAST_FREE | DEV_TX_OFFLOAD_MT_LOCKFREE | \
66 DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT | \
67 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \
68 DEV_TX_OFFLOAD_TCP_CKSUM | DEV_TX_OFFLOAD_UDP_CKSUM | \
69 DEV_TX_OFFLOAD_SCTP_CKSUM | DEV_TX_OFFLOAD_TCP_TSO | \
70 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
71 DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_MULTI_SEGS | \
72 DEV_TX_OFFLOAD_IPV4_CKSUM)
74 #define CNXK_NIX_RX_OFFLOAD_CAPA \
75 (DEV_RX_OFFLOAD_CHECKSUM | DEV_RX_OFFLOAD_SCTP_CKSUM | \
76 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_SCATTER | \
77 DEV_RX_OFFLOAD_JUMBO_FRAME | DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \
78 DEV_RX_OFFLOAD_RSS_HASH)
80 #define RSS_IPV4_ENABLE \
81 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_UDP | \
82 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_SCTP)
84 #define RSS_IPV6_ENABLE \
85 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_UDP | \
86 ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_NONFRAG_IPV6_SCTP)
88 #define RSS_IPV6_EX_ENABLE \
89 (ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | ETH_RSS_IPV6_UDP_EX)
91 #define RSS_MAX_LEVELS 3
93 #define RSS_IPV4_INDEX 0
94 #define RSS_IPV6_INDEX 1
95 #define RSS_TCP_INDEX 2
96 #define RSS_UDP_INDEX 3
97 #define RSS_SCTP_INDEX 4
98 #define RSS_DMAC_INDEX 5
100 /* Default mark value used when none is provided. */
101 #define CNXK_FLOW_ACTION_FLAG_DEFAULT 0xffff
103 #define PTYPE_NON_TUNNEL_WIDTH 16
104 #define PTYPE_TUNNEL_WIDTH 12
105 #define PTYPE_NON_TUNNEL_ARRAY_SZ BIT(PTYPE_NON_TUNNEL_WIDTH)
106 #define PTYPE_TUNNEL_ARRAY_SZ BIT(PTYPE_TUNNEL_WIDTH)
107 #define PTYPE_ARRAY_SZ \
108 ((PTYPE_NON_TUNNEL_ARRAY_SZ + PTYPE_TUNNEL_ARRAY_SZ) * sizeof(uint16_t))
109 /* Fastpath lookup */
110 #define CNXK_NIX_FASTPATH_LOOKUP_MEM "cnxk_nix_fastpath_lookup_mem"
112 #define CNXK_NIX_UDP_TUN_BITMASK \
113 ((1ull << (PKT_TX_TUNNEL_VXLAN >> 45)) | \
114 (1ull << (PKT_TX_TUNNEL_GENEVE >> 45)))
117 enum rte_eth_fc_mode mode;
122 struct cnxk_eth_qconf {
124 struct rte_eth_txconf tx;
125 struct rte_eth_rxconf rx;
127 struct rte_mempool *mp;
132 struct cnxk_eth_dev {
136 /* ROC RQs, SQs and CQs */
137 struct roc_nix_rq *rqs;
138 struct roc_nix_sq *sqs;
139 struct roc_nix_cq *cqs;
141 /* Configured queue count */
146 /* Max macfilter entries */
147 uint8_t max_mac_entries;
148 bool dmac_filter_enable;
151 uint8_t ptype_disable;
154 /* Pointer back to rte */
155 struct rte_eth_dev *eth_dev;
157 /* HW capabilities / Limitations */
160 uint64_t cq_min_4k : 1;
165 /* Rx and Tx offload capabilities */
166 uint64_t rx_offload_capa;
167 uint64_t tx_offload_capa;
169 /* Configured Rx and Tx offloads */
170 uint64_t rx_offloads;
171 uint64_t tx_offloads;
172 /* Platform specific offload flags */
173 uint16_t rx_offload_flags;
174 uint16_t tx_offload_flags;
176 /* ETHDEV RSS HF bitmask */
177 uint64_t ethdev_rss_hf;
179 /* Saved qconf before lf realloc */
180 struct cnxk_eth_qconf *tx_qconf;
181 struct cnxk_eth_qconf *rx_qconf;
183 /* Flow control configuration */
184 struct cnxk_fc_cfg fc_cfg;
186 /* Rx burst for cleanup(Only Primary) */
187 eth_rx_burst_t rx_pkt_burst_no_offload;
189 /* Default mac address */
190 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
192 /* LSO Tunnel format indices */
193 uint64_t lso_tun_fmt;
196 struct cnxk_eth_rxq_sp {
197 struct cnxk_eth_dev *dev;
198 struct cnxk_eth_qconf qconf;
200 } __plt_cache_aligned;
202 struct cnxk_eth_txq_sp {
203 struct cnxk_eth_dev *dev;
204 struct cnxk_eth_qconf qconf;
206 } __plt_cache_aligned;
208 static inline struct cnxk_eth_dev *
209 cnxk_eth_pmd_priv(struct rte_eth_dev *eth_dev)
211 return eth_dev->data->dev_private;
214 static inline struct cnxk_eth_rxq_sp *
215 cnxk_eth_rxq_to_sp(void *__rxq)
217 return ((struct cnxk_eth_rxq_sp *)__rxq) - 1;
220 static inline struct cnxk_eth_txq_sp *
221 cnxk_eth_txq_to_sp(void *__txq)
223 return ((struct cnxk_eth_txq_sp *)__txq) - 1;
226 /* Common ethdev ops */
227 extern struct eth_dev_ops cnxk_eth_dev_ops;
230 int cnxk_nix_probe(struct rte_pci_driver *pci_drv,
231 struct rte_pci_device *pci_dev);
232 int cnxk_nix_remove(struct rte_pci_device *pci_dev);
233 int cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
234 int cnxk_nix_mac_addr_add(struct rte_eth_dev *eth_dev,
235 struct rte_ether_addr *addr, uint32_t index,
237 void cnxk_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index);
238 int cnxk_nix_mac_addr_set(struct rte_eth_dev *eth_dev,
239 struct rte_ether_addr *addr);
240 int cnxk_nix_promisc_enable(struct rte_eth_dev *eth_dev);
241 int cnxk_nix_promisc_disable(struct rte_eth_dev *eth_dev);
242 int cnxk_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);
243 int cnxk_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);
244 int cnxk_nix_info_get(struct rte_eth_dev *eth_dev,
245 struct rte_eth_dev_info *dev_info);
246 int cnxk_nix_rx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
247 struct rte_eth_burst_mode *mode);
248 int cnxk_nix_tx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
249 struct rte_eth_burst_mode *mode);
250 int cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
251 struct rte_eth_fc_conf *fc_conf);
252 int cnxk_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
253 struct rte_eth_fc_conf *fc_conf);
254 int cnxk_nix_set_link_up(struct rte_eth_dev *eth_dev);
255 int cnxk_nix_set_link_down(struct rte_eth_dev *eth_dev);
256 int cnxk_nix_get_module_info(struct rte_eth_dev *eth_dev,
257 struct rte_eth_dev_module_info *modinfo);
258 int cnxk_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
259 struct rte_dev_eeprom_info *info);
260 int cnxk_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
261 uint16_t rx_queue_id);
262 int cnxk_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
263 uint16_t rx_queue_id);
265 int cnxk_nix_configure(struct rte_eth_dev *eth_dev);
266 int cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
267 uint16_t nb_desc, uint16_t fp_tx_q_sz,
268 const struct rte_eth_txconf *tx_conf);
269 int cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
270 uint16_t nb_desc, uint16_t fp_rx_q_sz,
271 const struct rte_eth_rxconf *rx_conf,
272 struct rte_mempool *mp);
273 int cnxk_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid);
274 int cnxk_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid);
275 int cnxk_nix_dev_start(struct rte_eth_dev *eth_dev);
277 uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev);
280 uint32_t cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
284 void cnxk_nix_toggle_flag_link_cfg(struct cnxk_eth_dev *dev, bool set);
285 void cnxk_eth_dev_link_status_cb(struct roc_nix *nix,
286 struct roc_nix_link_info *link);
287 int cnxk_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
289 /* Lookup configuration */
290 const uint32_t *cnxk_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev);
291 void *cnxk_nix_fastpath_lookup_mem_get(void);
294 int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs,
295 struct cnxk_eth_dev *dev);
298 static __rte_always_inline uint64_t
299 cnxk_pktmbuf_detach(struct rte_mbuf *m)
301 struct rte_mempool *mp = m->pool;
302 uint32_t mbuf_size, buf_len;
307 /* Update refcount of direct mbuf */
308 md = rte_mbuf_from_indirect(m);
309 refcount = rte_mbuf_refcnt_update(md, -1);
311 priv_size = rte_pktmbuf_priv_size(mp);
312 mbuf_size = (uint32_t)(sizeof(struct rte_mbuf) + priv_size);
313 buf_len = rte_pktmbuf_data_room_size(mp);
315 m->priv_size = priv_size;
316 m->buf_addr = (char *)m + mbuf_size;
317 m->buf_iova = rte_mempool_virt2iova(m) + mbuf_size;
318 m->buf_len = (uint16_t)buf_len;
319 rte_pktmbuf_reset_headroom(m);
325 /* Now indirect mbuf is safe to free */
329 rte_mbuf_refcnt_set(md, 1);
340 static __rte_always_inline uint64_t
341 cnxk_nix_prefree_seg(struct rte_mbuf *m)
343 if (likely(rte_mbuf_refcnt_read(m) == 1)) {
344 if (!RTE_MBUF_DIRECT(m))
345 return cnxk_pktmbuf_detach(m);
350 } else if (rte_mbuf_refcnt_update(m, -1) == 0) {
351 if (!RTE_MBUF_DIRECT(m))
352 return cnxk_pktmbuf_detach(m);
354 rte_mbuf_refcnt_set(m, 1);
360 /* Mbuf is having refcount more than 1 so need not to be freed */
364 #endif /* __CNXK_ETHDEV_H__ */