1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
8 #include "cnxk_ethdev.h"
11 parse_flow_max_priority(const char *key, const char *value, void *extra_args)
18 /* Limit the max priority to 32 */
19 if (val < 1 || val > 32)
22 *(uint16_t *)extra_args = val;
28 parse_flow_prealloc_size(const char *key, const char *value, void *extra_args)
35 /* Limit the prealloc size to 32 */
36 if (val < 1 || val > 32)
39 *(uint16_t *)extra_args = val;
45 parse_reta_size(const char *key, const char *value, void *extra_args)
52 if (val <= ETH_RSS_RETA_SIZE_64)
53 val = ROC_NIX_RSS_RETA_SZ_64;
54 else if (val > ETH_RSS_RETA_SIZE_64 && val <= ETH_RSS_RETA_SIZE_128)
55 val = ROC_NIX_RSS_RETA_SZ_128;
56 else if (val > ETH_RSS_RETA_SIZE_128 && val <= ETH_RSS_RETA_SIZE_256)
57 val = ROC_NIX_RSS_RETA_SZ_256;
59 val = ROC_NIX_RSS_RETA_SZ_64;
61 *(uint16_t *)extra_args = val;
67 parse_flag(const char *key, const char *value, void *extra_args)
71 *(uint16_t *)extra_args = atoi(value);
77 parse_sqb_count(const char *key, const char *value, void *extra_args)
84 *(uint16_t *)extra_args = val;
90 parse_switch_header_type(const char *key, const char *value, void *extra_args)
94 if (strcmp(value, "higig2") == 0)
95 *(uint16_t *)extra_args = ROC_PRIV_FLAGS_HIGIG;
97 if (strcmp(value, "dsa") == 0)
98 *(uint16_t *)extra_args = ROC_PRIV_FLAGS_EDSA;
100 if (strcmp(value, "chlen90b") == 0)
101 *(uint16_t *)extra_args = ROC_PRIV_FLAGS_LEN_90B;
103 if (strcmp(value, "exdsa") == 0)
104 *(uint16_t *)extra_args = ROC_PRIV_FLAGS_EXDSA;
106 if (strcmp(value, "vlan_exdsa") == 0)
107 *(uint16_t *)extra_args = ROC_PRIV_FLAGS_VLAN_EXDSA;
112 #define CNXK_RSS_RETA_SIZE "reta_size"
113 #define CNXK_SCL_ENABLE "scalar_enable"
114 #define CNXK_MAX_SQB_COUNT "max_sqb_count"
115 #define CNXK_FLOW_PREALLOC_SIZE "flow_prealloc_size"
116 #define CNXK_FLOW_MAX_PRIORITY "flow_max_priority"
117 #define CNXK_SWITCH_HEADER_TYPE "switch_header"
118 #define CNXK_RSS_TAG_AS_XOR "tag_as_xor"
119 #define CNXK_LOCK_RX_CTX "lock_rx_ctx"
122 cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
124 uint16_t reta_sz = ROC_NIX_RSS_RETA_SZ_64;
125 uint16_t sqb_count = CNXK_NIX_TX_MAX_SQB;
126 uint16_t flow_prealloc_size = 1;
127 uint16_t switch_header_type = 0;
128 uint16_t flow_max_priority = 3;
129 uint16_t rss_tag_as_xor = 0;
130 uint16_t scalar_enable = 0;
131 uint8_t lock_rx_ctx = 0;
132 struct rte_kvargs *kvlist;
137 kvlist = rte_kvargs_parse(devargs->args, NULL);
141 rte_kvargs_process(kvlist, CNXK_RSS_RETA_SIZE, &parse_reta_size,
143 rte_kvargs_process(kvlist, CNXK_SCL_ENABLE, &parse_flag,
145 rte_kvargs_process(kvlist, CNXK_MAX_SQB_COUNT, &parse_sqb_count,
147 rte_kvargs_process(kvlist, CNXK_FLOW_PREALLOC_SIZE,
148 &parse_flow_prealloc_size, &flow_prealloc_size);
149 rte_kvargs_process(kvlist, CNXK_FLOW_MAX_PRIORITY,
150 &parse_flow_max_priority, &flow_max_priority);
151 rte_kvargs_process(kvlist, CNXK_SWITCH_HEADER_TYPE,
152 &parse_switch_header_type, &switch_header_type);
153 rte_kvargs_process(kvlist, CNXK_RSS_TAG_AS_XOR, &parse_flag,
155 rte_kvargs_process(kvlist, CNXK_LOCK_RX_CTX, &parse_flag, &lock_rx_ctx);
156 rte_kvargs_free(kvlist);
159 dev->scalar_ena = !!scalar_enable;
160 dev->nix.rss_tag_as_xor = !!rss_tag_as_xor;
161 dev->nix.max_sqb_count = sqb_count;
162 dev->nix.reta_sz = reta_sz;
163 dev->nix.lock_rx_ctx = lock_rx_ctx;
164 dev->npc.flow_prealloc_size = flow_prealloc_size;
165 dev->npc.flow_max_priority = flow_max_priority;
166 dev->npc.switch_header_type = switch_header_type;
173 RTE_PMD_REGISTER_PARAM_STRING(net_cnxk,
174 CNXK_RSS_RETA_SIZE "=<64|128|256>"
176 CNXK_MAX_SQB_COUNT "=<8-512>"
177 CNXK_FLOW_PREALLOC_SIZE "=<1-32>"
178 CNXK_FLOW_MAX_PRIORITY "=<1-32>"
179 CNXK_SWITCH_HEADER_TYPE "=<higig2|dsa|chlen90b>"
180 CNXK_RSS_TAG_AS_XOR "=1");