1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
8 #include "cnxk_ethdev.h"
11 parse_outb_nb_desc(const char *key, const char *value, void *extra_args)
18 *(uint16_t *)extra_args = val;
24 parse_outb_nb_crypto_qs(const char *key, const char *value, void *extra_args)
31 if (val < 1 || val > 64)
34 *(uint16_t *)extra_args = val;
40 parse_ipsec_in_max_spi(const char *key, const char *value, void *extra_args)
47 *(uint16_t *)extra_args = val;
53 parse_ipsec_out_max_sa(const char *key, const char *value, void *extra_args)
60 *(uint16_t *)extra_args = val;
66 parse_flow_max_priority(const char *key, const char *value, void *extra_args)
73 /* Limit the max priority to 32 */
74 if (val < 1 || val > 32)
77 *(uint16_t *)extra_args = val;
83 parse_flow_prealloc_size(const char *key, const char *value, void *extra_args)
90 /* Limit the prealloc size to 32 */
91 if (val < 1 || val > 32)
94 *(uint16_t *)extra_args = val;
100 parse_reta_size(const char *key, const char *value, void *extra_args)
107 if (val <= RTE_ETH_RSS_RETA_SIZE_64)
108 val = ROC_NIX_RSS_RETA_SZ_64;
109 else if (val > RTE_ETH_RSS_RETA_SIZE_64 && val <= RTE_ETH_RSS_RETA_SIZE_128)
110 val = ROC_NIX_RSS_RETA_SZ_128;
111 else if (val > RTE_ETH_RSS_RETA_SIZE_128 && val <= RTE_ETH_RSS_RETA_SIZE_256)
112 val = ROC_NIX_RSS_RETA_SZ_256;
114 val = ROC_NIX_RSS_RETA_SZ_64;
116 *(uint16_t *)extra_args = val;
122 parse_flag(const char *key, const char *value, void *extra_args)
126 *(uint16_t *)extra_args = atoi(value);
132 parse_sqb_count(const char *key, const char *value, void *extra_args)
139 *(uint16_t *)extra_args = val;
145 parse_switch_header_type(const char *key, const char *value, void *extra_args)
149 if (strcmp(value, "higig2") == 0)
150 *(uint16_t *)extra_args = ROC_PRIV_FLAGS_HIGIG;
152 if (strcmp(value, "dsa") == 0)
153 *(uint16_t *)extra_args = ROC_PRIV_FLAGS_EDSA;
155 if (strcmp(value, "chlen90b") == 0)
156 *(uint16_t *)extra_args = ROC_PRIV_FLAGS_LEN_90B;
158 if (strcmp(value, "exdsa") == 0)
159 *(uint16_t *)extra_args = ROC_PRIV_FLAGS_EXDSA;
161 if (strcmp(value, "vlan_exdsa") == 0)
162 *(uint16_t *)extra_args = ROC_PRIV_FLAGS_VLAN_EXDSA;
167 #define CNXK_RSS_RETA_SIZE "reta_size"
168 #define CNXK_SCL_ENABLE "scalar_enable"
169 #define CNXK_MAX_SQB_COUNT "max_sqb_count"
170 #define CNXK_FLOW_PREALLOC_SIZE "flow_prealloc_size"
171 #define CNXK_FLOW_MAX_PRIORITY "flow_max_priority"
172 #define CNXK_SWITCH_HEADER_TYPE "switch_header"
173 #define CNXK_RSS_TAG_AS_XOR "tag_as_xor"
174 #define CNXK_LOCK_RX_CTX "lock_rx_ctx"
175 #define CNXK_IPSEC_IN_MAX_SPI "ipsec_in_max_spi"
176 #define CNXK_IPSEC_OUT_MAX_SA "ipsec_out_max_sa"
177 #define CNXK_OUTB_NB_DESC "outb_nb_desc"
178 #define CNXK_FORCE_INB_INL_DEV "force_inb_inl_dev"
179 #define CNXK_OUTB_NB_CRYPTO_QS "outb_nb_crypto_qs"
182 cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
184 uint16_t reta_sz = ROC_NIX_RSS_RETA_SZ_64;
185 uint16_t sqb_count = CNXK_NIX_TX_MAX_SQB;
186 uint16_t ipsec_in_max_spi = BIT(8) - 1;
187 uint16_t ipsec_out_max_sa = BIT(12);
188 uint16_t flow_prealloc_size = 1;
189 uint16_t switch_header_type = 0;
190 uint16_t flow_max_priority = 3;
191 uint16_t force_inb_inl_dev = 0;
192 uint16_t outb_nb_crypto_qs = 1;
193 uint16_t outb_nb_desc = 8200;
194 uint16_t rss_tag_as_xor = 0;
195 uint16_t scalar_enable = 0;
196 uint8_t lock_rx_ctx = 0;
197 struct rte_kvargs *kvlist;
202 kvlist = rte_kvargs_parse(devargs->args, NULL);
206 rte_kvargs_process(kvlist, CNXK_RSS_RETA_SIZE, &parse_reta_size,
208 rte_kvargs_process(kvlist, CNXK_SCL_ENABLE, &parse_flag,
210 rte_kvargs_process(kvlist, CNXK_MAX_SQB_COUNT, &parse_sqb_count,
212 rte_kvargs_process(kvlist, CNXK_FLOW_PREALLOC_SIZE,
213 &parse_flow_prealloc_size, &flow_prealloc_size);
214 rte_kvargs_process(kvlist, CNXK_FLOW_MAX_PRIORITY,
215 &parse_flow_max_priority, &flow_max_priority);
216 rte_kvargs_process(kvlist, CNXK_SWITCH_HEADER_TYPE,
217 &parse_switch_header_type, &switch_header_type);
218 rte_kvargs_process(kvlist, CNXK_RSS_TAG_AS_XOR, &parse_flag,
220 rte_kvargs_process(kvlist, CNXK_LOCK_RX_CTX, &parse_flag, &lock_rx_ctx);
221 rte_kvargs_process(kvlist, CNXK_IPSEC_IN_MAX_SPI,
222 &parse_ipsec_in_max_spi, &ipsec_in_max_spi);
223 rte_kvargs_process(kvlist, CNXK_IPSEC_OUT_MAX_SA,
224 &parse_ipsec_out_max_sa, &ipsec_out_max_sa);
225 rte_kvargs_process(kvlist, CNXK_OUTB_NB_DESC, &parse_outb_nb_desc,
227 rte_kvargs_process(kvlist, CNXK_OUTB_NB_CRYPTO_QS,
228 &parse_outb_nb_crypto_qs, &outb_nb_crypto_qs);
229 rte_kvargs_process(kvlist, CNXK_FORCE_INB_INL_DEV, &parse_flag,
231 rte_kvargs_free(kvlist);
234 dev->scalar_ena = !!scalar_enable;
235 dev->inb.force_inl_dev = !!force_inb_inl_dev;
236 dev->inb.max_spi = ipsec_in_max_spi;
237 dev->outb.max_sa = ipsec_out_max_sa;
238 dev->outb.nb_desc = outb_nb_desc;
239 dev->outb.nb_crypto_qs = outb_nb_crypto_qs;
240 dev->nix.ipsec_in_max_spi = ipsec_in_max_spi;
241 dev->nix.ipsec_out_max_sa = ipsec_out_max_sa;
242 dev->nix.rss_tag_as_xor = !!rss_tag_as_xor;
243 dev->nix.max_sqb_count = sqb_count;
244 dev->nix.reta_sz = reta_sz;
245 dev->nix.lock_rx_ctx = lock_rx_ctx;
246 dev->npc.flow_prealloc_size = flow_prealloc_size;
247 dev->npc.flow_max_priority = flow_max_priority;
248 dev->npc.switch_header_type = switch_header_type;
255 RTE_PMD_REGISTER_PARAM_STRING(net_cnxk,
256 CNXK_RSS_RETA_SIZE "=<64|128|256>"
258 CNXK_MAX_SQB_COUNT "=<8-512>"
259 CNXK_FLOW_PREALLOC_SIZE "=<1-32>"
260 CNXK_FLOW_MAX_PRIORITY "=<1-32>"
261 CNXK_SWITCH_HEADER_TYPE "=<higig2|dsa|chlen90b>"
262 CNXK_RSS_TAG_AS_XOR "=1"
263 CNXK_IPSEC_IN_MAX_SPI "=<1-65535>"
264 CNXK_OUTB_NB_DESC "=<1-65535>"
265 CNXK_OUTB_NB_CRYPTO_QS "=<1-64>"
266 CNXK_FORCE_INB_INL_DEV "=1");