drivers/net/cnxk/cnxk_ethdev_ops.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #include <cnxk_ethdev.h>
   6
   7 int
   8 cnxk_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo)
   9 {
  10         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
  11         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
  12         int max_rx_pktlen;
  13
  14         max_rx_pktlen = (roc_nix_max_pkt_len(&dev->nix) + RTE_ETHER_CRC_LEN -
  15                          CNXK_NIX_MAX_VTAG_ACT_SIZE);
  16
  17         devinfo->min_rx_bufsize = NIX_MIN_HW_FRS + RTE_ETHER_CRC_LEN;
  18         devinfo->max_rx_pktlen = max_rx_pktlen;
  19         devinfo->max_rx_queues = RTE_MAX_QUEUES_PER_PORT;
  20         devinfo->max_tx_queues = RTE_MAX_QUEUES_PER_PORT;
  21         devinfo->max_mac_addrs = dev->max_mac_entries;
  22         devinfo->max_vfs = pci_dev->max_vfs;
  23         devinfo->max_mtu = devinfo->max_rx_pktlen - CNXK_NIX_L2_OVERHEAD;
  24         devinfo->min_mtu = devinfo->min_rx_bufsize - CNXK_NIX_L2_OVERHEAD;
  25
  26         devinfo->rx_offload_capa = dev->rx_offload_capa;
  27         devinfo->tx_offload_capa = dev->tx_offload_capa;
  28         devinfo->rx_queue_offload_capa = 0;
  29         devinfo->tx_queue_offload_capa = 0;
  30
  31         devinfo->reta_size = dev->nix.reta_sz;
  32         devinfo->hash_key_size = ROC_NIX_RSS_KEY_LEN;
  33         devinfo->flow_type_rss_offloads = CNXK_NIX_RSS_OFFLOAD;
  34
  35         devinfo->default_rxconf = (struct rte_eth_rxconf){
  36                 .rx_drop_en = 0,
  37                 .offloads = 0,
  38         };
  39
  40         devinfo->default_txconf = (struct rte_eth_txconf){
  41                 .offloads = 0,
  42         };
  43
  44         devinfo->default_rxportconf = (struct rte_eth_dev_portconf){
  45                 .ring_size = CNXK_NIX_RX_DEFAULT_RING_SZ,
  46         };
  47
  48         devinfo->rx_desc_lim = (struct rte_eth_desc_lim){
  49                 .nb_max = UINT16_MAX,
  50                 .nb_min = CNXK_NIX_RX_MIN_DESC,
  51                 .nb_align = CNXK_NIX_RX_MIN_DESC_ALIGN,
  52                 .nb_seg_max = CNXK_NIX_RX_NB_SEG_MAX,
  53                 .nb_mtu_seg_max = CNXK_NIX_RX_NB_SEG_MAX,
  54         };
  55         devinfo->rx_desc_lim.nb_max =
  56                 RTE_ALIGN_MUL_FLOOR(devinfo->rx_desc_lim.nb_max,
  57                                     CNXK_NIX_RX_MIN_DESC_ALIGN);
  58
  59         devinfo->tx_desc_lim = (struct rte_eth_desc_lim){
  60                 .nb_max = UINT16_MAX,
  61                 .nb_min = 1,
  62                 .nb_align = 1,
  63                 .nb_seg_max = CNXK_NIX_TX_NB_SEG_MAX,
  64                 .nb_mtu_seg_max = CNXK_NIX_TX_NB_SEG_MAX,
  65         };
  66
  67         devinfo->speed_capa = dev->speed_capa;
  68         devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
  69                             RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
  70         return 0;
  71 }