1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #include <cnxk_ethdev.h>
8 cnxk_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo)
10 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
11 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
14 max_rx_pktlen = (roc_nix_max_pkt_len(&dev->nix) + RTE_ETHER_CRC_LEN -
15 CNXK_NIX_MAX_VTAG_ACT_SIZE);
17 devinfo->min_rx_bufsize = NIX_MIN_HW_FRS + RTE_ETHER_CRC_LEN;
18 devinfo->max_rx_pktlen = max_rx_pktlen;
19 devinfo->max_rx_queues = RTE_MAX_QUEUES_PER_PORT;
20 devinfo->max_tx_queues = RTE_MAX_QUEUES_PER_PORT;
21 devinfo->max_mac_addrs = dev->max_mac_entries;
22 devinfo->max_vfs = pci_dev->max_vfs;
23 devinfo->max_mtu = devinfo->max_rx_pktlen -
24 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN);
25 devinfo->min_mtu = devinfo->min_rx_bufsize - CNXK_NIX_L2_OVERHEAD;
27 devinfo->rx_offload_capa = dev->rx_offload_capa;
28 devinfo->tx_offload_capa = dev->tx_offload_capa;
29 devinfo->rx_queue_offload_capa = 0;
30 devinfo->tx_queue_offload_capa = 0;
32 devinfo->reta_size = dev->nix.reta_sz;
33 devinfo->hash_key_size = ROC_NIX_RSS_KEY_LEN;
34 devinfo->flow_type_rss_offloads = CNXK_NIX_RSS_OFFLOAD;
36 devinfo->default_rxconf = (struct rte_eth_rxconf){
41 devinfo->default_txconf = (struct rte_eth_txconf){
45 devinfo->default_rxportconf = (struct rte_eth_dev_portconf){
46 .ring_size = CNXK_NIX_RX_DEFAULT_RING_SZ,
49 devinfo->rx_desc_lim = (struct rte_eth_desc_lim){
51 .nb_min = CNXK_NIX_RX_MIN_DESC,
52 .nb_align = CNXK_NIX_RX_MIN_DESC_ALIGN,
53 .nb_seg_max = CNXK_NIX_RX_NB_SEG_MAX,
54 .nb_mtu_seg_max = CNXK_NIX_RX_NB_SEG_MAX,
56 devinfo->rx_desc_lim.nb_max =
57 RTE_ALIGN_MUL_FLOOR(devinfo->rx_desc_lim.nb_max,
58 CNXK_NIX_RX_MIN_DESC_ALIGN);
60 devinfo->tx_desc_lim = (struct rte_eth_desc_lim){
64 .nb_seg_max = CNXK_NIX_TX_NB_SEG_MAX,
65 .nb_mtu_seg_max = CNXK_NIX_TX_NB_SEG_MAX,
68 devinfo->speed_capa = dev->speed_capa;
69 devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
70 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
75 cnxk_nix_rx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
76 struct rte_eth_burst_mode *mode)
78 ssize_t bytes = 0, str_size = RTE_ETH_BURST_MODE_INFO_SIZE, rc;
79 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
80 const struct burst_info {
83 } rx_offload_map[] = {
84 {RTE_ETH_RX_OFFLOAD_VLAN_STRIP, " VLAN Strip,"},
85 {RTE_ETH_RX_OFFLOAD_IPV4_CKSUM, " Inner IPv4 Checksum,"},
86 {RTE_ETH_RX_OFFLOAD_UDP_CKSUM, " UDP Checksum,"},
87 {RTE_ETH_RX_OFFLOAD_TCP_CKSUM, " TCP Checksum,"},
88 {RTE_ETH_RX_OFFLOAD_TCP_LRO, " TCP LRO,"},
89 {RTE_ETH_RX_OFFLOAD_QINQ_STRIP, " QinQ VLAN Strip,"},
90 {RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPv4 Checksum,"},
91 {RTE_ETH_RX_OFFLOAD_MACSEC_STRIP, " MACsec Strip,"},
92 {RTE_ETH_RX_OFFLOAD_HEADER_SPLIT, " Header Split,"},
93 {RTE_ETH_RX_OFFLOAD_VLAN_FILTER, " VLAN Filter,"},
94 {RTE_ETH_RX_OFFLOAD_VLAN_EXTEND, " VLAN Extend,"},
95 {RTE_ETH_RX_OFFLOAD_SCATTER, " Scattered,"},
96 {RTE_ETH_RX_OFFLOAD_TIMESTAMP, " Timestamp,"},
97 {RTE_ETH_RX_OFFLOAD_SECURITY, " Security,"},
98 {RTE_ETH_RX_OFFLOAD_KEEP_CRC, " Keep CRC,"},
99 {RTE_ETH_RX_OFFLOAD_SCTP_CKSUM, " SCTP,"},
100 {RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP Checksum,"},
101 {RTE_ETH_RX_OFFLOAD_RSS_HASH, " RSS,"}
103 static const char *const burst_mode[] = {"Vector Neon, Rx Offloads:",
104 "Scalar, Rx Offloads:"
108 PLT_SET_USED(queue_id);
110 /* Update burst mode info */
111 rc = rte_strscpy(mode->info + bytes, burst_mode[dev->scalar_ena],
118 /* Update Rx offload info */
119 for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
120 if (dev->rx_offloads & rx_offload_map[i].flags) {
121 rc = rte_strscpy(mode->info + bytes,
122 rx_offload_map[i].output,
136 cnxk_nix_tx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
137 struct rte_eth_burst_mode *mode)
139 ssize_t bytes = 0, str_size = RTE_ETH_BURST_MODE_INFO_SIZE, rc;
140 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
141 const struct burst_info {
144 } tx_offload_map[] = {
145 {RTE_ETH_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"},
146 {RTE_ETH_TX_OFFLOAD_IPV4_CKSUM, " Inner IPv4 Checksum,"},
147 {RTE_ETH_TX_OFFLOAD_UDP_CKSUM, " UDP Checksum,"},
148 {RTE_ETH_TX_OFFLOAD_TCP_CKSUM, " TCP Checksum,"},
149 {RTE_ETH_TX_OFFLOAD_SCTP_CKSUM, " SCTP Checksum,"},
150 {RTE_ETH_TX_OFFLOAD_TCP_TSO, " TCP TSO,"},
151 {RTE_ETH_TX_OFFLOAD_UDP_TSO, " UDP TSO,"},
152 {RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPv4 Checksum,"},
153 {RTE_ETH_TX_OFFLOAD_QINQ_INSERT, " QinQ VLAN Insert,"},
154 {RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO, " VXLAN Tunnel TSO,"},
155 {RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO, " GRE Tunnel TSO,"},
156 {RTE_ETH_TX_OFFLOAD_IPIP_TNL_TSO, " IP-in-IP Tunnel TSO,"},
157 {RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO, " Geneve Tunnel TSO,"},
158 {RTE_ETH_TX_OFFLOAD_MACSEC_INSERT, " MACsec Insert,"},
159 {RTE_ETH_TX_OFFLOAD_MT_LOCKFREE, " Multi Thread Lockless Tx,"},
160 {RTE_ETH_TX_OFFLOAD_MULTI_SEGS, " Scattered,"},
161 {RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE, " H/W MBUF Free,"},
162 {RTE_ETH_TX_OFFLOAD_SECURITY, " Security,"},
163 {RTE_ETH_TX_OFFLOAD_UDP_TNL_TSO, " UDP Tunnel TSO,"},
164 {RTE_ETH_TX_OFFLOAD_IP_TNL_TSO, " IP Tunnel TSO,"},
165 {RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP Checksum,"},
166 {RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP, " Timestamp,"}
168 static const char *const burst_mode[] = {"Vector Neon, Tx Offloads:",
169 "Scalar, Tx Offloads:"
173 PLT_SET_USED(queue_id);
175 /* Update burst mode info */
176 rc = rte_strscpy(mode->info + bytes, burst_mode[dev->scalar_ena],
183 /* Update Tx offload info */
184 for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
185 if (dev->tx_offloads & tx_offload_map[i].flags) {
186 rc = rte_strscpy(mode->info + bytes,
187 tx_offload_map[i].output,
201 cnxk_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
202 struct rte_eth_fc_conf *fc_conf)
204 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
205 enum rte_eth_fc_mode mode_map[] = {
206 RTE_ETH_FC_NONE, RTE_ETH_FC_RX_PAUSE,
207 RTE_ETH_FC_TX_PAUSE, RTE_ETH_FC_FULL
209 struct roc_nix *nix = &dev->nix;
212 mode = roc_nix_fc_mode_get(nix);
216 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
217 fc_conf->mode = mode_map[mode];
222 nix_fc_cq_config_set(struct cnxk_eth_dev *dev, uint16_t qid, bool enable)
224 struct roc_nix *nix = &dev->nix;
225 struct roc_nix_fc_cfg fc_cfg;
226 struct roc_nix_cq *cq;
228 memset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg));
230 fc_cfg.cq_cfg_valid = true;
231 fc_cfg.cq_cfg.enable = enable;
232 fc_cfg.cq_cfg.rq = qid;
233 fc_cfg.cq_cfg.cq_drop = cq->drop_thresh;
235 return roc_nix_fc_config_set(nix, &fc_cfg);
239 cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
240 struct rte_eth_fc_conf *fc_conf)
242 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
243 enum roc_nix_fc_mode mode_map[] = {
244 ROC_NIX_FC_NONE, ROC_NIX_FC_RX,
245 ROC_NIX_FC_TX, ROC_NIX_FC_FULL
247 struct rte_eth_dev_data *data = eth_dev->data;
248 struct cnxk_fc_cfg *fc = &dev->fc_cfg;
249 struct roc_nix *nix = &dev->nix;
250 uint8_t rx_pause, tx_pause;
253 if (roc_nix_is_vf_or_sdp(nix)) {
254 plt_err("Flow control configuration is not allowed on VFs");
258 if (fc_conf->high_water || fc_conf->low_water || fc_conf->pause_time ||
259 fc_conf->mac_ctrl_frame_fwd || fc_conf->autoneg) {
260 plt_info("Only MODE configuration is supported");
264 if (fc_conf->mode == fc->mode)
267 rx_pause = (fc_conf->mode == RTE_ETH_FC_FULL) ||
268 (fc_conf->mode == RTE_ETH_FC_RX_PAUSE);
269 tx_pause = (fc_conf->mode == RTE_ETH_FC_FULL) ||
270 (fc_conf->mode == RTE_ETH_FC_TX_PAUSE);
272 /* Check if TX pause frame is already enabled or not */
273 if (fc->tx_pause ^ tx_pause) {
274 if (roc_model_is_cn96_ax() && data->dev_started) {
275 /* On Ax, CQ should be in disabled state
276 * while setting flow control configuration.
278 plt_info("Stop the port=%d for setting flow control",
283 for (i = 0; i < data->nb_rx_queues; i++) {
284 rc = nix_fc_cq_config_set(dev, i, tx_pause);
290 rc = roc_nix_fc_mode_set(nix, mode_map[fc_conf->mode]);
294 fc->rx_pause = rx_pause;
295 fc->tx_pause = tx_pause;
296 fc->mode = fc_conf->mode;
302 cnxk_nix_flow_ops_get(struct rte_eth_dev *eth_dev,
303 const struct rte_flow_ops **ops)
305 RTE_SET_USED(eth_dev);
307 *ops = &cnxk_flow_ops;
312 cnxk_nix_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *addr)
314 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
315 struct roc_nix *nix = &dev->nix;
318 /* Update mac address at NPC */
319 rc = roc_nix_npc_mac_addr_set(nix, addr->addr_bytes);
323 /* Update mac address at CGX for PFs only */
324 if (!roc_nix_is_vf_or_sdp(nix)) {
325 rc = roc_nix_mac_addr_set(nix, addr->addr_bytes);
327 /* Rollback to previous mac address */
328 roc_nix_npc_mac_addr_set(nix, dev->mac_addr);
333 /* Update mac address to cnxk ethernet device */
334 rte_memcpy(dev->mac_addr, addr->addr_bytes, RTE_ETHER_ADDR_LEN);
341 cnxk_nix_mac_addr_add(struct rte_eth_dev *eth_dev, struct rte_ether_addr *addr,
342 uint32_t index, uint32_t pool)
344 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
345 struct roc_nix *nix = &dev->nix;
351 rc = roc_nix_mac_addr_add(nix, addr->addr_bytes);
353 plt_err("Failed to add mac address, rc=%d", rc);
357 /* Enable promiscuous mode at NIX level */
358 roc_nix_npc_promisc_ena_dis(nix, true);
359 dev->dmac_filter_enable = true;
360 eth_dev->data->promiscuous = false;
361 dev->dmac_filter_count++;
367 cnxk_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index)
369 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
370 struct roc_nix *nix = &dev->nix;
373 rc = roc_nix_mac_addr_del(nix, index);
375 plt_err("Failed to delete mac address, rc=%d", rc);
377 dev->dmac_filter_count--;
381 cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
383 uint32_t old_frame_size, frame_size = mtu + CNXK_NIX_L2_OVERHEAD;
384 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
385 struct rte_eth_dev_data *data = eth_dev->data;
386 struct roc_nix *nix = &dev->nix;
390 frame_size += CNXK_NIX_TIMESYNC_RX_OFFSET * dev->ptp_en;
392 /* Check if MTU is within the allowed range */
393 if ((frame_size - RTE_ETHER_CRC_LEN) < NIX_MIN_HW_FRS) {
394 plt_err("MTU is lesser than minimum");
398 if ((frame_size - RTE_ETHER_CRC_LEN) >
399 ((uint32_t)roc_nix_max_pkt_len(nix))) {
400 plt_err("MTU is greater than maximum");
404 buffsz = data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
405 old_frame_size = data->mtu + CNXK_NIX_L2_OVERHEAD;
407 /* Refuse MTU that requires the support of scattered packets
408 * when this feature has not been enabled before.
410 if (data->dev_started && frame_size > buffsz &&
411 !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER)) {
412 plt_err("Scatter offload is not enabled for mtu");
416 /* Check <seg size> * <max_seg> >= max_frame */
417 if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER) &&
418 frame_size > (buffsz * CNXK_NIX_RX_NB_SEG_MAX)) {
419 plt_err("Greater than maximum supported packet length");
423 frame_size -= RTE_ETHER_CRC_LEN;
425 /* Update mtu on Tx */
426 rc = roc_nix_mac_mtu_set(nix, frame_size);
428 plt_err("Failed to set MTU, rc=%d", rc);
432 /* Sync same frame size on Rx */
433 rc = roc_nix_mac_max_rx_len_set(nix, frame_size);
435 /* Rollback to older mtu */
436 roc_nix_mac_mtu_set(nix,
437 old_frame_size - RTE_ETHER_CRC_LEN);
438 plt_err("Failed to max Rx frame length, rc=%d", rc);
446 cnxk_nix_promisc_enable(struct rte_eth_dev *eth_dev)
448 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
449 struct roc_nix *nix = &dev->nix;
452 if (roc_nix_is_vf_or_sdp(nix))
455 rc = roc_nix_npc_promisc_ena_dis(nix, true);
457 plt_err("Failed to setup promisc mode in npc, rc=%d(%s)", rc,
458 roc_error_msg_get(rc));
462 rc = roc_nix_mac_promisc_mode_enable(nix, true);
464 plt_err("Failed to setup promisc mode in mac, rc=%d(%s)", rc,
465 roc_error_msg_get(rc));
466 roc_nix_npc_promisc_ena_dis(nix, false);
474 cnxk_nix_promisc_disable(struct rte_eth_dev *eth_dev)
476 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
477 struct roc_nix *nix = &dev->nix;
480 if (roc_nix_is_vf_or_sdp(nix))
483 rc = roc_nix_npc_promisc_ena_dis(nix, dev->dmac_filter_enable);
485 plt_err("Failed to setup promisc mode in npc, rc=%d(%s)", rc,
486 roc_error_msg_get(rc));
490 rc = roc_nix_mac_promisc_mode_enable(nix, false);
492 plt_err("Failed to setup promisc mode in mac, rc=%d(%s)", rc,
493 roc_error_msg_get(rc));
494 roc_nix_npc_promisc_ena_dis(nix, !dev->dmac_filter_enable);
498 dev->dmac_filter_enable = false;
503 cnxk_nix_allmulticast_enable(struct rte_eth_dev *eth_dev)
505 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
507 return roc_nix_npc_mcast_config(&dev->nix, true, false);
511 cnxk_nix_allmulticast_disable(struct rte_eth_dev *eth_dev)
513 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
515 return roc_nix_npc_mcast_config(&dev->nix, false,
516 eth_dev->data->promiscuous);
520 cnxk_nix_set_link_up(struct rte_eth_dev *eth_dev)
522 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
523 struct roc_nix *nix = &dev->nix;
526 if (roc_nix_is_vf_or_sdp(nix))
529 rc = roc_nix_mac_link_state_set(nix, true);
533 /* Start tx queues */
534 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
535 rc = cnxk_nix_tx_queue_start(eth_dev, i);
545 cnxk_nix_set_link_down(struct rte_eth_dev *eth_dev)
547 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
548 struct roc_nix *nix = &dev->nix;
551 if (roc_nix_is_vf_or_sdp(nix))
555 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
556 rc = cnxk_nix_tx_queue_stop(eth_dev, i);
561 rc = roc_nix_mac_link_state_set(nix, false);
567 cnxk_nix_get_module_info(struct rte_eth_dev *eth_dev,
568 struct rte_eth_dev_module_info *modinfo)
570 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
571 struct roc_nix_eeprom_info eeprom_info = {0};
572 struct roc_nix *nix = &dev->nix;
575 rc = roc_nix_eeprom_info_get(nix, &eeprom_info);
579 modinfo->type = eeprom_info.sff_id;
580 modinfo->eeprom_len = ROC_NIX_EEPROM_SIZE;
585 cnxk_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
586 struct rte_dev_eeprom_info *info)
588 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
589 struct roc_nix_eeprom_info eeprom_info = {0};
590 struct roc_nix *nix = &dev->nix;
593 if (!info->data || !info->length ||
594 (info->offset + info->length > ROC_NIX_EEPROM_SIZE))
597 rc = roc_nix_eeprom_info_get(nix, &eeprom_info);
601 rte_memcpy(info->data, eeprom_info.buf + info->offset, info->length);
606 cnxk_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
608 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
610 roc_nix_rx_queue_intr_enable(&dev->nix, rx_queue_id);
615 cnxk_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
616 uint16_t rx_queue_id)
618 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
620 roc_nix_rx_queue_intr_disable(&dev->nix, rx_queue_id);
625 cnxk_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool)
627 RTE_SET_USED(eth_dev);
629 if (!strcmp(pool, rte_mbuf_platform_mempool_ops()))
636 cnxk_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
639 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
640 const char *str = roc_npc_profile_name_get(&dev->npc);
641 uint32_t size = strlen(str) + 1;
646 rte_strlcpy(fw_version, str, fw_size);
655 cnxk_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid,
656 struct rte_eth_rxq_info *qinfo)
658 void *rxq = eth_dev->data->rx_queues[qid];
659 struct cnxk_eth_rxq_sp *rxq_sp = cnxk_eth_rxq_to_sp(rxq);
661 memset(qinfo, 0, sizeof(*qinfo));
663 qinfo->mp = rxq_sp->qconf.mp;
664 qinfo->scattered_rx = eth_dev->data->scattered_rx;
665 qinfo->nb_desc = rxq_sp->qconf.nb_desc;
667 memcpy(&qinfo->conf, &rxq_sp->qconf.conf.rx, sizeof(qinfo->conf));
671 cnxk_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid,
672 struct rte_eth_txq_info *qinfo)
674 void *txq = eth_dev->data->tx_queues[qid];
675 struct cnxk_eth_txq_sp *txq_sp = cnxk_eth_txq_to_sp(txq);
677 memset(qinfo, 0, sizeof(*qinfo));
679 qinfo->nb_desc = txq_sp->qconf.nb_desc;
681 memcpy(&qinfo->conf, &txq_sp->qconf.conf.tx, sizeof(qinfo->conf));
684 /* It is a NOP for cnxk as HW frees the buffer on xmit */
686 cnxk_nix_tx_done_cleanup(void *txq, uint32_t free_cnt)
689 RTE_SET_USED(free_cnt);
695 cnxk_nix_dev_get_reg(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)
697 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
698 struct roc_nix *nix = &dev->nix;
699 uint64_t *data = regs->data;
703 rc = roc_nix_lf_get_reg_count(nix);
713 regs->length == (uint32_t)roc_nix_lf_get_reg_count(nix))
714 return roc_nix_lf_reg_dump(nix, data);
720 cnxk_nix_reta_update(struct rte_eth_dev *eth_dev,
721 struct rte_eth_rss_reta_entry64 *reta_conf,
724 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
725 uint16_t reta[ROC_NIX_RSS_RETA_MAX];
726 struct roc_nix *nix = &dev->nix;
727 int i, j, rc = -EINVAL, idx = 0;
729 if (reta_size != dev->nix.reta_sz) {
730 plt_err("Size of hash lookup table configured (%d) does not "
731 "match the number hardware can supported (%d)",
732 reta_size, dev->nix.reta_sz);
736 /* Copy RETA table */
737 for (i = 0; i < (int)(dev->nix.reta_sz / RTE_ETH_RETA_GROUP_SIZE); i++) {
738 for (j = 0; j < RTE_ETH_RETA_GROUP_SIZE; j++) {
739 if ((reta_conf[i].mask >> j) & 0x01)
740 reta[idx] = reta_conf[i].reta[j];
745 return roc_nix_rss_reta_set(nix, 0, reta);
752 cnxk_nix_reta_query(struct rte_eth_dev *eth_dev,
753 struct rte_eth_rss_reta_entry64 *reta_conf,
756 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
757 uint16_t reta[ROC_NIX_RSS_RETA_MAX];
758 struct roc_nix *nix = &dev->nix;
759 int rc = -EINVAL, i, j, idx = 0;
761 if (reta_size != dev->nix.reta_sz) {
762 plt_err("Size of hash lookup table configured (%d) does not "
763 "match the number hardware can supported (%d)",
764 reta_size, dev->nix.reta_sz);
768 rc = roc_nix_rss_reta_get(nix, 0, reta);
772 /* Copy RETA table */
773 for (i = 0; i < (int)(dev->nix.reta_sz / RTE_ETH_RETA_GROUP_SIZE); i++) {
774 for (j = 0; j < RTE_ETH_RETA_GROUP_SIZE; j++) {
775 if ((reta_conf[i].mask >> j) & 0x01)
776 reta_conf[i].reta[j] = reta[idx];
788 cnxk_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
789 struct rte_eth_rss_conf *rss_conf)
791 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
792 struct roc_nix *nix = &dev->nix;
793 uint8_t rss_hash_level;
794 uint32_t flowkey_cfg;
798 if (rss_conf->rss_key && rss_conf->rss_key_len != ROC_NIX_RSS_KEY_LEN) {
799 plt_err("Hash key size mismatch %d vs %d",
800 rss_conf->rss_key_len, ROC_NIX_RSS_KEY_LEN);
804 if (rss_conf->rss_key)
805 roc_nix_rss_key_set(nix, rss_conf->rss_key);
807 rss_hash_level = RTE_ETH_RSS_LEVEL(rss_conf->rss_hf);
811 cnxk_rss_ethdev_to_nix(dev, rss_conf->rss_hf, rss_hash_level);
813 rc = roc_nix_rss_flowkey_set(nix, &alg_idx, flowkey_cfg,
814 ROC_NIX_RSS_GROUP_DEFAULT,
815 ROC_NIX_RSS_MCAM_IDX_DEFAULT);
817 plt_err("Failed to set RSS hash function rc=%d", rc);
826 cnxk_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
827 struct rte_eth_rss_conf *rss_conf)
829 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
831 if (rss_conf->rss_key)
832 roc_nix_rss_key_get(&dev->nix, rss_conf->rss_key);
834 rss_conf->rss_key_len = ROC_NIX_RSS_KEY_LEN;
835 rss_conf->rss_hf = dev->ethdev_rss_hf;
841 cnxk_nix_mc_addr_list_configure(struct rte_eth_dev *eth_dev,
842 struct rte_ether_addr *mc_addr_set,
845 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
846 struct rte_eth_dev_data *data = eth_dev->data;
847 struct rte_ether_addr null_mac_addr;
848 struct roc_nix *nix = &dev->nix;
852 memset(&null_mac_addr, 0, sizeof(null_mac_addr));
854 /* All configured multicast filters should be flushed first */
855 for (i = 0; i < dev->max_mac_entries; i++) {
856 if (rte_is_multicast_ether_addr(&data->mac_addrs[i])) {
857 rc = roc_nix_mac_addr_del(nix, i);
859 plt_err("Failed to flush mcast address, rc=%d",
864 dev->dmac_filter_count--;
865 /* Update address in NIC data structure */
866 rte_ether_addr_copy(&null_mac_addr,
867 &data->mac_addrs[i]);
871 if (!mc_addr_set || !nb_mc_addr)
874 /* Check for available space */
876 ((uint32_t)(dev->max_mac_entries - dev->dmac_filter_count))) {
877 plt_err("No space is available to add multicast filters");
881 /* Multicast addresses are to be installed */
882 for (i = 0; i < nb_mc_addr; i++) {
883 index = roc_nix_mac_addr_add(nix, mc_addr_set[i].addr_bytes);
885 plt_err("Failed to add mcast mac address, rc=%d",
890 dev->dmac_filter_count++;
891 /* Update address in NIC data structure */
892 rte_ether_addr_copy(&mc_addr_set[i], &data->mac_addrs[index]);
895 roc_nix_npc_promisc_ena_dis(nix, true);
896 dev->dmac_filter_enable = true;
897 eth_dev->data->promiscuous = false;