1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #include <cnxk_ethdev.h>
8 cnxk_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo)
10 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
11 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
14 max_rx_pktlen = (roc_nix_max_pkt_len(&dev->nix) + RTE_ETHER_CRC_LEN -
15 CNXK_NIX_MAX_VTAG_ACT_SIZE);
17 devinfo->min_rx_bufsize = NIX_MIN_HW_FRS + RTE_ETHER_CRC_LEN;
18 devinfo->max_rx_pktlen = max_rx_pktlen;
19 devinfo->max_rx_queues = RTE_MAX_QUEUES_PER_PORT;
20 devinfo->max_tx_queues = RTE_MAX_QUEUES_PER_PORT;
21 devinfo->max_mac_addrs = dev->max_mac_entries;
22 devinfo->max_vfs = pci_dev->max_vfs;
23 devinfo->max_mtu = devinfo->max_rx_pktlen -
24 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN);
25 devinfo->min_mtu = devinfo->min_rx_bufsize - CNXK_NIX_L2_OVERHEAD;
27 devinfo->rx_offload_capa = dev->rx_offload_capa;
28 devinfo->tx_offload_capa = dev->tx_offload_capa;
29 devinfo->rx_queue_offload_capa = 0;
30 devinfo->tx_queue_offload_capa = 0;
32 devinfo->reta_size = dev->nix.reta_sz;
33 devinfo->hash_key_size = ROC_NIX_RSS_KEY_LEN;
34 devinfo->flow_type_rss_offloads = CNXK_NIX_RSS_OFFLOAD;
36 devinfo->default_rxconf = (struct rte_eth_rxconf){
41 devinfo->default_txconf = (struct rte_eth_txconf){
45 devinfo->default_rxportconf = (struct rte_eth_dev_portconf){
46 .ring_size = CNXK_NIX_RX_DEFAULT_RING_SZ,
49 devinfo->rx_desc_lim = (struct rte_eth_desc_lim){
51 .nb_min = CNXK_NIX_RX_MIN_DESC,
52 .nb_align = CNXK_NIX_RX_MIN_DESC_ALIGN,
53 .nb_seg_max = CNXK_NIX_RX_NB_SEG_MAX,
54 .nb_mtu_seg_max = CNXK_NIX_RX_NB_SEG_MAX,
56 devinfo->rx_desc_lim.nb_max =
57 RTE_ALIGN_MUL_FLOOR(devinfo->rx_desc_lim.nb_max,
58 CNXK_NIX_RX_MIN_DESC_ALIGN);
60 devinfo->tx_desc_lim = (struct rte_eth_desc_lim){
64 .nb_seg_max = CNXK_NIX_TX_NB_SEG_MAX,
65 .nb_mtu_seg_max = CNXK_NIX_TX_NB_SEG_MAX,
68 devinfo->speed_capa = dev->speed_capa;
69 devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
70 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
71 devinfo->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
76 cnxk_nix_rx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
77 struct rte_eth_burst_mode *mode)
79 ssize_t bytes = 0, str_size = RTE_ETH_BURST_MODE_INFO_SIZE, rc;
80 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
81 const struct burst_info {
84 } rx_offload_map[] = {
85 {RTE_ETH_RX_OFFLOAD_VLAN_STRIP, " VLAN Strip,"},
86 {RTE_ETH_RX_OFFLOAD_IPV4_CKSUM, " Inner IPv4 Checksum,"},
87 {RTE_ETH_RX_OFFLOAD_UDP_CKSUM, " UDP Checksum,"},
88 {RTE_ETH_RX_OFFLOAD_TCP_CKSUM, " TCP Checksum,"},
89 {RTE_ETH_RX_OFFLOAD_TCP_LRO, " TCP LRO,"},
90 {RTE_ETH_RX_OFFLOAD_QINQ_STRIP, " QinQ VLAN Strip,"},
91 {RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPv4 Checksum,"},
92 {RTE_ETH_RX_OFFLOAD_MACSEC_STRIP, " MACsec Strip,"},
93 {RTE_ETH_RX_OFFLOAD_HEADER_SPLIT, " Header Split,"},
94 {RTE_ETH_RX_OFFLOAD_VLAN_FILTER, " VLAN Filter,"},
95 {RTE_ETH_RX_OFFLOAD_VLAN_EXTEND, " VLAN Extend,"},
96 {RTE_ETH_RX_OFFLOAD_SCATTER, " Scattered,"},
97 {RTE_ETH_RX_OFFLOAD_TIMESTAMP, " Timestamp,"},
98 {RTE_ETH_RX_OFFLOAD_SECURITY, " Security,"},
99 {RTE_ETH_RX_OFFLOAD_KEEP_CRC, " Keep CRC,"},
100 {RTE_ETH_RX_OFFLOAD_SCTP_CKSUM, " SCTP,"},
101 {RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP Checksum,"},
102 {RTE_ETH_RX_OFFLOAD_RSS_HASH, " RSS,"}
104 static const char *const burst_mode[] = {"Vector Neon, Rx Offloads:",
105 "Scalar, Rx Offloads:"
109 PLT_SET_USED(queue_id);
111 /* Update burst mode info */
112 rc = rte_strscpy(mode->info + bytes, burst_mode[dev->scalar_ena],
119 /* Update Rx offload info */
120 for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
121 if (dev->rx_offloads & rx_offload_map[i].flags) {
122 rc = rte_strscpy(mode->info + bytes,
123 rx_offload_map[i].output,
137 cnxk_nix_tx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
138 struct rte_eth_burst_mode *mode)
140 ssize_t bytes = 0, str_size = RTE_ETH_BURST_MODE_INFO_SIZE, rc;
141 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
142 const struct burst_info {
145 } tx_offload_map[] = {
146 {RTE_ETH_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"},
147 {RTE_ETH_TX_OFFLOAD_IPV4_CKSUM, " Inner IPv4 Checksum,"},
148 {RTE_ETH_TX_OFFLOAD_UDP_CKSUM, " UDP Checksum,"},
149 {RTE_ETH_TX_OFFLOAD_TCP_CKSUM, " TCP Checksum,"},
150 {RTE_ETH_TX_OFFLOAD_SCTP_CKSUM, " SCTP Checksum,"},
151 {RTE_ETH_TX_OFFLOAD_TCP_TSO, " TCP TSO,"},
152 {RTE_ETH_TX_OFFLOAD_UDP_TSO, " UDP TSO,"},
153 {RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPv4 Checksum,"},
154 {RTE_ETH_TX_OFFLOAD_QINQ_INSERT, " QinQ VLAN Insert,"},
155 {RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO, " VXLAN Tunnel TSO,"},
156 {RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO, " GRE Tunnel TSO,"},
157 {RTE_ETH_TX_OFFLOAD_IPIP_TNL_TSO, " IP-in-IP Tunnel TSO,"},
158 {RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO, " Geneve Tunnel TSO,"},
159 {RTE_ETH_TX_OFFLOAD_MACSEC_INSERT, " MACsec Insert,"},
160 {RTE_ETH_TX_OFFLOAD_MT_LOCKFREE, " Multi Thread Lockless Tx,"},
161 {RTE_ETH_TX_OFFLOAD_MULTI_SEGS, " Scattered,"},
162 {RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE, " H/W MBUF Free,"},
163 {RTE_ETH_TX_OFFLOAD_SECURITY, " Security,"},
164 {RTE_ETH_TX_OFFLOAD_UDP_TNL_TSO, " UDP Tunnel TSO,"},
165 {RTE_ETH_TX_OFFLOAD_IP_TNL_TSO, " IP Tunnel TSO,"},
166 {RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP Checksum,"},
167 {RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP, " Timestamp,"}
169 static const char *const burst_mode[] = {"Vector Neon, Tx Offloads:",
170 "Scalar, Tx Offloads:"
174 PLT_SET_USED(queue_id);
176 /* Update burst mode info */
177 rc = rte_strscpy(mode->info + bytes, burst_mode[dev->scalar_ena],
184 /* Update Tx offload info */
185 for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
186 if (dev->tx_offloads & tx_offload_map[i].flags) {
187 rc = rte_strscpy(mode->info + bytes,
188 tx_offload_map[i].output,
202 cnxk_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
203 struct rte_eth_fc_conf *fc_conf)
205 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
206 enum rte_eth_fc_mode mode_map[] = {
207 RTE_ETH_FC_NONE, RTE_ETH_FC_RX_PAUSE,
208 RTE_ETH_FC_TX_PAUSE, RTE_ETH_FC_FULL
210 struct roc_nix *nix = &dev->nix;
213 mode = roc_nix_fc_mode_get(nix);
217 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
218 fc_conf->mode = mode_map[mode];
223 nix_fc_cq_config_set(struct cnxk_eth_dev *dev, uint16_t qid, bool enable)
225 struct roc_nix *nix = &dev->nix;
226 struct roc_nix_fc_cfg fc_cfg;
227 struct roc_nix_cq *cq;
229 memset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg));
231 fc_cfg.type = ROC_NIX_FC_CQ_CFG;
232 fc_cfg.cq_cfg.enable = enable;
233 fc_cfg.cq_cfg.rq = qid;
234 fc_cfg.cq_cfg.cq_drop = cq->drop_thresh;
236 return roc_nix_fc_config_set(nix, &fc_cfg);
240 cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
241 struct rte_eth_fc_conf *fc_conf)
243 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
244 enum roc_nix_fc_mode mode_map[] = {
245 ROC_NIX_FC_NONE, ROC_NIX_FC_RX,
246 ROC_NIX_FC_TX, ROC_NIX_FC_FULL
248 struct rte_eth_dev_data *data = eth_dev->data;
249 struct cnxk_fc_cfg *fc = &dev->fc_cfg;
250 struct roc_nix *nix = &dev->nix;
251 uint8_t rx_pause, tx_pause;
254 if (roc_nix_is_vf_or_sdp(nix) && !roc_nix_is_lbk(nix)) {
255 plt_err("Flow control configuration is not allowed on VFs");
259 if (fc_conf->high_water || fc_conf->low_water || fc_conf->pause_time ||
260 fc_conf->mac_ctrl_frame_fwd || fc_conf->autoneg) {
261 plt_info("Only MODE configuration is supported");
265 if (fc_conf->mode == fc->mode)
268 rx_pause = (fc_conf->mode == RTE_ETH_FC_FULL) ||
269 (fc_conf->mode == RTE_ETH_FC_RX_PAUSE);
270 tx_pause = (fc_conf->mode == RTE_ETH_FC_FULL) ||
271 (fc_conf->mode == RTE_ETH_FC_TX_PAUSE);
273 /* Check if TX pause frame is already enabled or not */
274 if (fc->tx_pause ^ tx_pause) {
275 if (roc_model_is_cn96_ax() && data->dev_started) {
276 /* On Ax, CQ should be in disabled state
277 * while setting flow control configuration.
279 plt_info("Stop the port=%d for setting flow control",
284 for (i = 0; i < data->nb_rx_queues; i++) {
285 rc = nix_fc_cq_config_set(dev, i, tx_pause);
291 /* Check if RX pause frame is enabled or not */
292 if (fc->rx_pause ^ rx_pause) {
293 struct roc_nix_fc_cfg fc_cfg;
295 memset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg));
296 fc_cfg.type = ROC_NIX_FC_TM_CFG;
297 fc_cfg.tm_cfg.enable = !!rx_pause;
298 rc = roc_nix_fc_config_set(nix, &fc_cfg);
303 rc = roc_nix_fc_mode_set(nix, mode_map[fc_conf->mode]);
307 fc->rx_pause = rx_pause;
308 fc->tx_pause = tx_pause;
309 fc->mode = fc_conf->mode;
315 cnxk_nix_flow_ops_get(struct rte_eth_dev *eth_dev,
316 const struct rte_flow_ops **ops)
318 RTE_SET_USED(eth_dev);
320 *ops = &cnxk_flow_ops;
325 cnxk_nix_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *addr)
327 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
328 struct roc_nix *nix = &dev->nix;
331 /* Update mac address at NPC */
332 rc = roc_nix_npc_mac_addr_set(nix, addr->addr_bytes);
336 /* Update mac address at CGX for PFs only */
337 if (!roc_nix_is_vf_or_sdp(nix)) {
338 rc = roc_nix_mac_addr_set(nix, addr->addr_bytes);
340 /* Rollback to previous mac address */
341 roc_nix_npc_mac_addr_set(nix, dev->mac_addr);
346 /* Update mac address to cnxk ethernet device */
347 rte_memcpy(dev->mac_addr, addr->addr_bytes, RTE_ETHER_ADDR_LEN);
354 cnxk_nix_mac_addr_add(struct rte_eth_dev *eth_dev, struct rte_ether_addr *addr,
355 uint32_t index, uint32_t pool)
357 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
358 struct roc_nix *nix = &dev->nix;
364 rc = roc_nix_mac_addr_add(nix, addr->addr_bytes);
366 plt_err("Failed to add mac address, rc=%d", rc);
370 /* Enable promiscuous mode at NIX level */
371 roc_nix_npc_promisc_ena_dis(nix, true);
372 dev->dmac_filter_enable = true;
373 eth_dev->data->promiscuous = false;
374 dev->dmac_filter_count++;
380 cnxk_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index)
382 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
383 struct roc_nix *nix = &dev->nix;
386 rc = roc_nix_mac_addr_del(nix, index);
388 plt_err("Failed to delete mac address, rc=%d", rc);
390 dev->dmac_filter_count--;
394 cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
396 uint32_t old_frame_size, frame_size = mtu + CNXK_NIX_L2_OVERHEAD;
397 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
398 struct rte_eth_dev_data *data = eth_dev->data;
399 struct roc_nix *nix = &dev->nix;
403 frame_size += CNXK_NIX_TIMESYNC_RX_OFFSET * dev->ptp_en;
405 /* Check if MTU is within the allowed range */
406 if ((frame_size - RTE_ETHER_CRC_LEN) < NIX_MIN_HW_FRS) {
407 plt_err("MTU is lesser than minimum");
411 if ((frame_size - RTE_ETHER_CRC_LEN) >
412 ((uint32_t)roc_nix_max_pkt_len(nix))) {
413 plt_err("MTU is greater than maximum");
417 buffsz = data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
418 old_frame_size = data->mtu + CNXK_NIX_L2_OVERHEAD;
420 /* Refuse MTU that requires the support of scattered packets
421 * when this feature has not been enabled before.
423 if (data->dev_started && frame_size > buffsz &&
424 !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER)) {
425 plt_err("Scatter offload is not enabled for mtu");
429 /* Check <seg size> * <max_seg> >= max_frame */
430 if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER) &&
431 frame_size > (buffsz * CNXK_NIX_RX_NB_SEG_MAX)) {
432 plt_err("Greater than maximum supported packet length");
436 frame_size -= RTE_ETHER_CRC_LEN;
438 /* Update mtu on Tx */
439 rc = roc_nix_mac_mtu_set(nix, frame_size);
441 plt_err("Failed to set MTU, rc=%d", rc);
445 /* Sync same frame size on Rx */
446 rc = roc_nix_mac_max_rx_len_set(nix, frame_size);
448 /* Rollback to older mtu */
449 roc_nix_mac_mtu_set(nix,
450 old_frame_size - RTE_ETHER_CRC_LEN);
451 plt_err("Failed to max Rx frame length, rc=%d", rc);
459 cnxk_nix_promisc_enable(struct rte_eth_dev *eth_dev)
461 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
462 struct roc_nix *nix = &dev->nix;
465 if (roc_nix_is_vf_or_sdp(nix))
468 rc = roc_nix_npc_promisc_ena_dis(nix, true);
470 plt_err("Failed to setup promisc mode in npc, rc=%d(%s)", rc,
471 roc_error_msg_get(rc));
475 rc = roc_nix_mac_promisc_mode_enable(nix, true);
477 plt_err("Failed to setup promisc mode in mac, rc=%d(%s)", rc,
478 roc_error_msg_get(rc));
479 roc_nix_npc_promisc_ena_dis(nix, false);
487 cnxk_nix_promisc_disable(struct rte_eth_dev *eth_dev)
489 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
490 struct roc_nix *nix = &dev->nix;
493 if (roc_nix_is_vf_or_sdp(nix))
496 rc = roc_nix_npc_promisc_ena_dis(nix, dev->dmac_filter_enable);
498 plt_err("Failed to setup promisc mode in npc, rc=%d(%s)", rc,
499 roc_error_msg_get(rc));
503 rc = roc_nix_mac_promisc_mode_enable(nix, false);
505 plt_err("Failed to setup promisc mode in mac, rc=%d(%s)", rc,
506 roc_error_msg_get(rc));
507 roc_nix_npc_promisc_ena_dis(nix, !dev->dmac_filter_enable);
511 dev->dmac_filter_enable = false;
516 cnxk_nix_allmulticast_enable(struct rte_eth_dev *eth_dev)
518 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
520 return roc_nix_npc_mcast_config(&dev->nix, true,
521 eth_dev->data->promiscuous);
525 cnxk_nix_allmulticast_disable(struct rte_eth_dev *eth_dev)
527 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
529 return roc_nix_npc_mcast_config(&dev->nix, false,
530 eth_dev->data->promiscuous);
534 cnxk_nix_set_link_up(struct rte_eth_dev *eth_dev)
536 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
537 struct roc_nix *nix = &dev->nix;
540 if (roc_nix_is_vf_or_sdp(nix))
543 rc = roc_nix_mac_link_state_set(nix, true);
547 /* Start tx queues */
548 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
549 rc = cnxk_nix_tx_queue_start(eth_dev, i);
559 cnxk_nix_set_link_down(struct rte_eth_dev *eth_dev)
561 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
562 struct roc_nix *nix = &dev->nix;
565 if (roc_nix_is_vf_or_sdp(nix))
569 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
570 rc = cnxk_nix_tx_queue_stop(eth_dev, i);
575 rc = roc_nix_mac_link_state_set(nix, false);
581 cnxk_nix_get_module_info(struct rte_eth_dev *eth_dev,
582 struct rte_eth_dev_module_info *modinfo)
584 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
585 struct roc_nix_eeprom_info eeprom_info = {0};
586 struct roc_nix *nix = &dev->nix;
589 rc = roc_nix_eeprom_info_get(nix, &eeprom_info);
593 modinfo->type = eeprom_info.sff_id;
594 modinfo->eeprom_len = ROC_NIX_EEPROM_SIZE;
599 cnxk_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
600 struct rte_dev_eeprom_info *info)
602 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
603 struct roc_nix_eeprom_info eeprom_info = {0};
604 struct roc_nix *nix = &dev->nix;
607 if (!info->data || !info->length ||
608 (info->offset + info->length > ROC_NIX_EEPROM_SIZE))
611 rc = roc_nix_eeprom_info_get(nix, &eeprom_info);
615 rte_memcpy(info->data, eeprom_info.buf + info->offset, info->length);
620 cnxk_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
622 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
624 roc_nix_rx_queue_intr_enable(&dev->nix, rx_queue_id);
629 cnxk_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
630 uint16_t rx_queue_id)
632 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
634 roc_nix_rx_queue_intr_disable(&dev->nix, rx_queue_id);
639 cnxk_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool)
641 RTE_SET_USED(eth_dev);
643 if (!strcmp(pool, rte_mbuf_platform_mempool_ops()))
650 cnxk_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
653 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
654 const char *str = roc_npc_profile_name_get(&dev->npc);
655 uint32_t size = strlen(str) + 1;
660 rte_strlcpy(fw_version, str, fw_size);
669 cnxk_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid,
670 struct rte_eth_rxq_info *qinfo)
672 void *rxq = eth_dev->data->rx_queues[qid];
673 struct cnxk_eth_rxq_sp *rxq_sp = cnxk_eth_rxq_to_sp(rxq);
675 memset(qinfo, 0, sizeof(*qinfo));
677 qinfo->mp = rxq_sp->qconf.mp;
678 qinfo->scattered_rx = eth_dev->data->scattered_rx;
679 qinfo->nb_desc = rxq_sp->qconf.nb_desc;
681 memcpy(&qinfo->conf, &rxq_sp->qconf.conf.rx, sizeof(qinfo->conf));
685 cnxk_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid,
686 struct rte_eth_txq_info *qinfo)
688 void *txq = eth_dev->data->tx_queues[qid];
689 struct cnxk_eth_txq_sp *txq_sp = cnxk_eth_txq_to_sp(txq);
691 memset(qinfo, 0, sizeof(*qinfo));
693 qinfo->nb_desc = txq_sp->qconf.nb_desc;
695 memcpy(&qinfo->conf, &txq_sp->qconf.conf.tx, sizeof(qinfo->conf));
699 cnxk_nix_rx_queue_count(void *rxq)
701 struct cnxk_eth_rxq_sp *rxq_sp = cnxk_eth_rxq_to_sp(rxq);
702 struct roc_nix *nix = &rxq_sp->dev->nix;
705 roc_nix_cq_head_tail_get(nix, rxq_sp->qid, &head, &tail);
706 return (tail - head) % (rxq_sp->qconf.nb_desc);
710 nix_offset_has_packet(uint32_t head, uint32_t tail, uint16_t offset, bool is_rx)
712 /* Check given offset(queue index) has packet filled/xmit by HW
713 * in case of Rx or Tx.
714 * Also, checks for wrap around case.
716 return ((tail > head && offset <= tail && offset >= head) ||
717 (head > tail && (offset >= head || offset <= tail))) ?
723 cnxk_nix_rx_descriptor_status(void *rxq, uint16_t offset)
725 struct cnxk_eth_rxq_sp *rxq_sp = cnxk_eth_rxq_to_sp(rxq);
726 struct roc_nix *nix = &rxq_sp->dev->nix;
729 if (rxq_sp->qconf.nb_desc <= offset)
732 roc_nix_cq_head_tail_get(nix, rxq_sp->qid, &head, &tail);
734 if (nix_offset_has_packet(head, tail, offset, 1))
735 return RTE_ETH_RX_DESC_DONE;
737 return RTE_ETH_RX_DESC_AVAIL;
741 cnxk_nix_tx_descriptor_status(void *txq, uint16_t offset)
743 struct cnxk_eth_txq_sp *txq_sp = cnxk_eth_txq_to_sp(txq);
744 struct roc_nix *nix = &txq_sp->dev->nix;
745 uint32_t head = 0, tail = 0;
747 if (txq_sp->qconf.nb_desc <= offset)
750 roc_nix_sq_head_tail_get(nix, txq_sp->qid, &head, &tail);
752 if (nix_offset_has_packet(head, tail, offset, 0))
753 return RTE_ETH_TX_DESC_DONE;
755 return RTE_ETH_TX_DESC_FULL;
758 /* It is a NOP for cnxk as HW frees the buffer on xmit */
760 cnxk_nix_tx_done_cleanup(void *txq, uint32_t free_cnt)
763 RTE_SET_USED(free_cnt);
769 cnxk_nix_dev_get_reg(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)
771 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
772 struct roc_nix *nix = &dev->nix;
773 uint64_t *data = regs->data;
777 rc = roc_nix_lf_get_reg_count(nix);
787 regs->length == (uint32_t)roc_nix_lf_get_reg_count(nix))
788 return roc_nix_lf_reg_dump(nix, data);
794 cnxk_nix_reta_update(struct rte_eth_dev *eth_dev,
795 struct rte_eth_rss_reta_entry64 *reta_conf,
798 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
799 uint16_t reta[ROC_NIX_RSS_RETA_MAX];
800 struct roc_nix *nix = &dev->nix;
801 int i, j, rc = -EINVAL, idx = 0;
803 if (reta_size != dev->nix.reta_sz) {
804 plt_err("Size of hash lookup table configured (%d) does not "
805 "match the number hardware can supported (%d)",
806 reta_size, dev->nix.reta_sz);
810 /* Copy RETA table */
811 for (i = 0; i < (int)(dev->nix.reta_sz / RTE_ETH_RETA_GROUP_SIZE); i++) {
812 for (j = 0; j < RTE_ETH_RETA_GROUP_SIZE; j++) {
813 if ((reta_conf[i].mask >> j) & 0x01)
814 reta[idx] = reta_conf[i].reta[j];
819 return roc_nix_rss_reta_set(nix, 0, reta);
826 cnxk_nix_reta_query(struct rte_eth_dev *eth_dev,
827 struct rte_eth_rss_reta_entry64 *reta_conf,
830 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
831 uint16_t reta[ROC_NIX_RSS_RETA_MAX];
832 struct roc_nix *nix = &dev->nix;
833 int rc = -EINVAL, i, j, idx = 0;
835 if (reta_size != dev->nix.reta_sz) {
836 plt_err("Size of hash lookup table configured (%d) does not "
837 "match the number hardware can supported (%d)",
838 reta_size, dev->nix.reta_sz);
842 rc = roc_nix_rss_reta_get(nix, 0, reta);
846 /* Copy RETA table */
847 for (i = 0; i < (int)(dev->nix.reta_sz / RTE_ETH_RETA_GROUP_SIZE); i++) {
848 for (j = 0; j < RTE_ETH_RETA_GROUP_SIZE; j++) {
849 if ((reta_conf[i].mask >> j) & 0x01)
850 reta_conf[i].reta[j] = reta[idx];
862 cnxk_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
863 struct rte_eth_rss_conf *rss_conf)
865 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
866 struct roc_nix *nix = &dev->nix;
867 uint8_t rss_hash_level;
868 uint32_t flowkey_cfg;
872 if (rss_conf->rss_key && rss_conf->rss_key_len != ROC_NIX_RSS_KEY_LEN) {
873 plt_err("Hash key size mismatch %d vs %d",
874 rss_conf->rss_key_len, ROC_NIX_RSS_KEY_LEN);
878 if (rss_conf->rss_key)
879 roc_nix_rss_key_set(nix, rss_conf->rss_key);
881 rss_hash_level = RTE_ETH_RSS_LEVEL(rss_conf->rss_hf);
885 cnxk_rss_ethdev_to_nix(dev, rss_conf->rss_hf, rss_hash_level);
887 rc = roc_nix_rss_flowkey_set(nix, &alg_idx, flowkey_cfg,
888 ROC_NIX_RSS_GROUP_DEFAULT,
889 ROC_NIX_RSS_MCAM_IDX_DEFAULT);
891 plt_err("Failed to set RSS hash function rc=%d", rc);
900 cnxk_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
901 struct rte_eth_rss_conf *rss_conf)
903 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
905 if (rss_conf->rss_key)
906 roc_nix_rss_key_get(&dev->nix, rss_conf->rss_key);
908 rss_conf->rss_key_len = ROC_NIX_RSS_KEY_LEN;
909 rss_conf->rss_hf = dev->ethdev_rss_hf;
915 cnxk_nix_mc_addr_list_configure(struct rte_eth_dev *eth_dev,
916 struct rte_ether_addr *mc_addr_set,
919 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
920 struct rte_eth_dev_data *data = eth_dev->data;
921 struct rte_ether_addr null_mac_addr;
922 struct roc_nix *nix = &dev->nix;
926 memset(&null_mac_addr, 0, sizeof(null_mac_addr));
928 /* All configured multicast filters should be flushed first */
929 for (i = 0; i < dev->max_mac_entries; i++) {
930 if (rte_is_multicast_ether_addr(&data->mac_addrs[i])) {
931 rc = roc_nix_mac_addr_del(nix, i);
933 plt_err("Failed to flush mcast address, rc=%d",
938 dev->dmac_filter_count--;
939 /* Update address in NIC data structure */
940 rte_ether_addr_copy(&null_mac_addr,
941 &data->mac_addrs[i]);
945 if (!mc_addr_set || !nb_mc_addr)
948 /* Check for available space */
950 ((uint32_t)(dev->max_mac_entries - dev->dmac_filter_count))) {
951 plt_err("No space is available to add multicast filters");
955 /* Multicast addresses are to be installed */
956 for (i = 0; i < nb_mc_addr; i++) {
957 index = roc_nix_mac_addr_add(nix, mc_addr_set[i].addr_bytes);
959 plt_err("Failed to add mcast mac address, rc=%d",
964 dev->dmac_filter_count++;
965 /* Update address in NIC data structure */
966 rte_ether_addr_copy(&mc_addr_set[i], &data->mac_addrs[index]);
969 roc_nix_npc_promisc_ena_dis(nix, true);
970 dev->dmac_filter_enable = true;
971 eth_dev->data->promiscuous = false;