1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #include <cnxk_ethdev.h>
7 #define CNXK_NIX_INL_SELFTEST "selftest"
8 #define CNXK_NIX_INL_IPSEC_IN_MIN_SPI "ipsec_in_min_spi"
9 #define CNXK_NIX_INL_IPSEC_IN_MAX_SPI "ipsec_in_max_spi"
10 #define CNXK_INL_CPT_CHANNEL "inl_cpt_channel"
12 struct inl_cpt_channel {
13 bool is_multi_channel;
18 #define CNXK_NIX_INL_DEV_NAME RTE_STR(cnxk_nix_inl_dev_)
19 #define CNXK_NIX_INL_DEV_NAME_LEN \
20 (sizeof(CNXK_NIX_INL_DEV_NAME) + PCI_PRI_STR_SIZE)
23 bitmap_ctzll(uint64_t slab)
28 return __builtin_ctzll(slab);
32 cnxk_eth_outb_sa_idx_get(struct cnxk_eth_dev *dev, uint32_t *idx_p)
38 if (!dev->outb.sa_bmap)
43 /* Scan from the beginning */
44 plt_bitmap_scan_init(dev->outb.sa_bmap);
45 /* Scan bitmap to get the free sa index */
46 rc = plt_bitmap_scan(dev->outb.sa_bmap, &pos, &slab);
49 plt_err("Outbound SA' exhausted, use 'ipsec_out_max_sa' "
50 "devargs to increase");
54 /* Get free SA index */
55 idx = pos + bitmap_ctzll(slab);
56 plt_bitmap_clear(dev->outb.sa_bmap, idx);
62 cnxk_eth_outb_sa_idx_put(struct cnxk_eth_dev *dev, uint32_t idx)
64 if (idx >= dev->outb.max_sa)
67 /* Check if it is already free */
68 if (plt_bitmap_get(dev->outb.sa_bmap, idx))
71 /* Mark index as free */
72 plt_bitmap_set(dev->outb.sa_bmap, idx);
76 struct cnxk_eth_sec_sess *
77 cnxk_eth_sec_sess_get_by_spi(struct cnxk_eth_dev *dev, uint32_t spi, bool inb)
79 struct cnxk_eth_sec_sess_list *list;
80 struct cnxk_eth_sec_sess *eth_sec;
82 list = inb ? &dev->inb.list : &dev->outb.list;
83 TAILQ_FOREACH(eth_sec, list, entry) {
84 if (eth_sec->spi == spi)
91 struct cnxk_eth_sec_sess *
92 cnxk_eth_sec_sess_get_by_sess(struct cnxk_eth_dev *dev,
93 struct rte_security_session *sess)
95 struct cnxk_eth_sec_sess *eth_sec = NULL;
97 /* Search in inbound list */
98 TAILQ_FOREACH(eth_sec, &dev->inb.list, entry) {
99 if (eth_sec->sess == sess)
103 /* Search in outbound list */
104 TAILQ_FOREACH(eth_sec, &dev->outb.list, entry) {
105 if (eth_sec->sess == sess)
113 cnxk_eth_sec_session_get_size(void *device __rte_unused)
115 return sizeof(struct cnxk_eth_sec_sess);
118 struct rte_security_ops cnxk_eth_sec_ops = {
119 .session_get_size = cnxk_eth_sec_session_get_size
123 parse_ipsec_in_spi_range(const char *key, const char *value, void *extra_args)
129 val = strtoul(value, NULL, 0);
133 *(uint32_t *)extra_args = val;
139 parse_selftest(const char *key, const char *value, void *extra_args)
146 *(uint8_t *)extra_args = !!(val == 1);
151 parse_inl_cpt_channel(const char *key, const char *value, void *extra_args)
154 uint16_t chan = 0, mask = 0;
157 /* next will point to the separator '/' */
158 chan = strtol(value, &next, 16);
159 mask = strtol(++next, 0, 16);
161 if (chan > GENMASK(12, 0) || mask > GENMASK(12, 0))
164 ((struct inl_cpt_channel *)extra_args)->channel = chan;
165 ((struct inl_cpt_channel *)extra_args)->mask = mask;
166 ((struct inl_cpt_channel *)extra_args)->is_multi_channel = true;
172 nix_inl_parse_devargs(struct rte_devargs *devargs,
173 struct roc_nix_inl_dev *inl_dev)
175 uint32_t ipsec_in_max_spi = BIT(8) - 1;
176 uint32_t ipsec_in_min_spi = 0;
177 struct inl_cpt_channel cpt_channel;
178 struct rte_kvargs *kvlist;
179 uint8_t selftest = 0;
181 memset(&cpt_channel, 0, sizeof(cpt_channel));
186 kvlist = rte_kvargs_parse(devargs->args, NULL);
190 rte_kvargs_process(kvlist, CNXK_NIX_INL_SELFTEST, &parse_selftest,
192 rte_kvargs_process(kvlist, CNXK_NIX_INL_IPSEC_IN_MIN_SPI,
193 &parse_ipsec_in_spi_range, &ipsec_in_min_spi);
194 rte_kvargs_process(kvlist, CNXK_NIX_INL_IPSEC_IN_MAX_SPI,
195 &parse_ipsec_in_spi_range, &ipsec_in_max_spi);
196 rte_kvargs_process(kvlist, CNXK_INL_CPT_CHANNEL, &parse_inl_cpt_channel,
198 rte_kvargs_free(kvlist);
201 inl_dev->ipsec_in_min_spi = ipsec_in_min_spi;
202 inl_dev->ipsec_in_max_spi = ipsec_in_max_spi;
203 inl_dev->selftest = selftest;
204 inl_dev->channel = cpt_channel.channel;
205 inl_dev->chan_mask = cpt_channel.mask;
206 inl_dev->is_multi_channel = cpt_channel.is_multi_channel;
213 nix_inl_dev_to_name(struct rte_pci_device *pci_dev, char *name)
215 snprintf(name, CNXK_NIX_INL_DEV_NAME_LEN,
216 CNXK_NIX_INL_DEV_NAME PCI_PRI_FMT, pci_dev->addr.domain,
217 pci_dev->addr.bus, pci_dev->addr.devid,
218 pci_dev->addr.function);
224 cnxk_nix_inl_dev_remove(struct rte_pci_device *pci_dev)
226 char name[CNXK_NIX_INL_DEV_NAME_LEN];
227 const struct rte_memzone *mz;
228 struct roc_nix_inl_dev *dev;
231 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
234 mz = rte_memzone_lookup(nix_inl_dev_to_name(pci_dev, name));
240 /* Cleanup inline dev */
241 rc = roc_nix_inl_dev_fini(dev);
243 plt_err("Failed to cleanup inl dev, rc=%d(%s)", rc,
244 roc_error_msg_get(rc));
248 rte_memzone_free(mz);
253 cnxk_nix_inl_dev_probe(struct rte_pci_driver *pci_drv,
254 struct rte_pci_device *pci_dev)
256 char name[CNXK_NIX_INL_DEV_NAME_LEN];
257 struct roc_nix_inl_dev *inl_dev;
258 const struct rte_memzone *mz;
261 RTE_SET_USED(pci_drv);
265 plt_err("Failed to initialize platform model, rc=%d", rc);
269 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
272 mz = rte_memzone_reserve_aligned(nix_inl_dev_to_name(pci_dev, name),
273 sizeof(*inl_dev), SOCKET_ID_ANY, 0,
274 RTE_CACHE_LINE_SIZE);
279 inl_dev->pci_dev = pci_dev;
281 /* Parse devargs string */
282 rc = nix_inl_parse_devargs(pci_dev->device.devargs, inl_dev);
284 plt_err("Failed to parse devargs rc=%d", rc);
288 inl_dev->attach_cptlf = true;
289 /* WQE skip is one for DPDK */
290 inl_dev->wqe_skip = true;
291 rc = roc_nix_inl_dev_init(inl_dev);
293 plt_err("Failed to init nix inl device, rc=%d(%s)", rc,
294 roc_error_msg_get(rc));
300 rte_memzone_free(mz);
304 static const struct rte_pci_id cnxk_nix_inl_pci_map[] = {
305 {RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNXK_RVU_NIX_INL_PF)},
306 {RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNXK_RVU_NIX_INL_VF)},
312 static struct rte_pci_driver cnxk_nix_inl_pci = {
313 .id_table = cnxk_nix_inl_pci_map,
314 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
315 .probe = cnxk_nix_inl_dev_probe,
316 .remove = cnxk_nix_inl_dev_remove,
319 RTE_PMD_REGISTER_PCI(cnxk_nix_inl, cnxk_nix_inl_pci);
320 RTE_PMD_REGISTER_PCI_TABLE(cnxk_nix_inl, cnxk_nix_inl_pci_map);
321 RTE_PMD_REGISTER_KMOD_DEP(cnxk_nix_inl, "vfio-pci");
323 RTE_PMD_REGISTER_PARAM_STRING(cnxk_nix_inl,
324 CNXK_NIX_INL_SELFTEST "=1"
325 CNXK_NIX_INL_IPSEC_IN_MAX_SPI "=<1-65535>"
326 CNXK_INL_CPT_CHANNEL "=<1-4095>/<1-4095>");