1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
6 /* This file should not be included directly. Include common.h instead. */
8 #ifndef __T4_ADAPTER_H__
9 #define __T4_ADAPTER_H__
11 #include <rte_bus_pci.h>
14 #include <rte_rwlock.h>
15 #include <rte_ethdev.h>
17 #include "../cxgbe_compat.h"
18 #include "../cxgbe_ofld.h"
19 #include "t4_regs_values.h"
22 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
29 PORT_RSS_DONE = (1 << 0),
33 struct adapter *adapter; /* adapter that this port belongs to */
34 struct rte_eth_dev *eth_dev; /* associated rte eth device */
35 struct port_stats stats_base; /* port statistics base */
36 struct link_config link_cfg; /* link configuration info */
38 unsigned long flags; /* port related flags */
39 short int xact_addr_filt; /* index of exact MAC address filter */
41 u16 viid; /* associated virtual interface id */
42 u8 port_id; /* physical port ID */
43 u8 pidx; /* port index for this PF */
44 u8 tx_chan; /* associated channel */
46 u16 n_rx_qsets; /* # of rx qsets */
47 u16 n_tx_qsets; /* # of tx qsets */
48 u16 first_rxqset; /* index of first rxqset */
49 u16 first_txqset; /* index of first txqset */
51 u16 *rss; /* rss table */
52 u8 rss_mode; /* rss mode */
53 u16 rss_size; /* size of VI's RSS table slice */
54 u64 rss_hf; /* RSS Hash Function */
56 /* viid fields either returned by fw
57 * or decoded by parsing viid by driver.
62 u8 vi_en_rx; /* Enable/disable VI Rx */
63 u8 vi_en_tx; /* Enable/disable VI Tx */
66 enum { /* adapter flags */
67 FULL_INIT_DONE = (1 << 0),
69 USING_MSIX = (1 << 2),
70 FW_QUEUE_BOUND = (1 << 3),
72 CFG_QUEUES = (1 << 5),
76 struct rx_sw_desc { /* SW state per Rx descriptor */
77 void *buf; /* struct page or mbuf */
81 struct sge_fl { /* SGE free-buffer queue state */
83 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
85 dma_addr_t addr; /* bus address of HW ring start */
86 __be64 *desc; /* address of HW Rx descriptor ring */
88 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
89 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
91 unsigned int cntxt_id; /* SGE relative QID for the free list */
92 unsigned int size; /* capacity of free list */
94 unsigned int avail; /* # of available Rx buffers */
95 unsigned int pend_cred; /* new buffers since last FL DB ring */
96 unsigned int cidx; /* consumer index */
97 unsigned int pidx; /* producer index */
99 unsigned long alloc_failed; /* # of times buffer allocation failed */
100 unsigned long low; /* # of times momentarily starving */
103 #define MAX_MBUF_FRAGS (16384 / 512 + 2)
105 /* A packet gather list */
108 struct rte_mbuf *mbufs[MAX_MBUF_FRAGS];
110 void *va; /* virtual address of first byte */
111 unsigned int nfrags; /* # of fragments */
112 unsigned int tot_len; /* total length of fragments */
113 bool usembufs; /* use mbufs for fragments */
116 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
117 const struct pkt_gl *gl);
119 struct sge_rspq { /* state for an SGE response queue */
120 struct adapter *adapter; /* adapter that this queue belongs to */
121 struct rte_eth_dev *eth_dev; /* associated rte eth device */
122 struct rte_mempool *mb_pool; /* associated mempool */
124 dma_addr_t phys_addr; /* physical address of the ring */
125 __be64 *desc; /* address of HW response ring */
126 const __be64 *cur_desc; /* current descriptor in queue */
128 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
129 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
130 struct sge_qstat *stat;
132 unsigned int cidx; /* consumer index */
133 unsigned int gts_idx; /* last gts write sent */
134 unsigned int iqe_len; /* entry size */
135 unsigned int size; /* capacity of response queue */
136 int offset; /* offset into current Rx buffer */
138 u8 gen; /* current generation bit */
139 u8 intr_params; /* interrupt holdoff parameters */
140 u8 next_intr_params; /* holdoff params for next interrupt */
141 u8 pktcnt_idx; /* interrupt packet threshold */
142 u8 port_id; /* associated port-id */
143 u8 idx; /* queue index within its group */
144 u16 cntxt_id; /* SGE relative QID for the response Q */
145 u16 abs_id; /* absolute SGE id for the response q */
147 rspq_handler_t handler; /* associated handler for this response q */
150 struct sge_eth_rx_stats { /* Ethernet rx queue statistics */
151 u64 pkts; /* # of ethernet packets */
152 u64 rx_bytes; /* # of ethernet bytes */
153 u64 rx_cso; /* # of Rx checksum offloads */
154 u64 vlan_ex; /* # of Rx VLAN extractions */
155 u64 rx_drops; /* # of packets dropped due to no mem */
158 struct sge_eth_rxq { /* a SW Ethernet Rx queue */
159 unsigned int flags; /* flags for state of the queue */
160 struct sge_rspq rspq;
162 struct sge_eth_rx_stats stats;
163 bool usembufs; /* one ingress packet per mbuf FL buffer */
164 } __rte_cache_aligned;
167 * Currently there are two types of coalesce WR. Type 0 needs 48 bytes per
168 * packet (if one sgl is present) and type 1 needs 32 bytes. This means
169 * that type 0 can fit a maximum of 10 packets per WR and type 1 can fit
170 * 15 packets. We need to keep track of the mbuf pointers in a coalesce WR
171 * to be able to free those mbufs when we get completions back from the FW.
172 * Allocating the maximum number of pointers in every tx desc is a waste
173 * of memory resources so we only store 2 pointers per tx desc which should
174 * be enough since a tx desc can only fit 2 packets in the best case
175 * scenario where a packet needs 32 bytes.
177 #define ETH_COALESCE_PKT_NUM 15
178 #define ETH_COALESCE_VF_PKT_NUM 7
179 #define ETH_COALESCE_PKT_PER_DESC 2
181 struct tx_eth_coal_desc {
182 struct rte_mbuf *mbuf[ETH_COALESCE_PKT_PER_DESC];
183 struct ulptx_sgl *sgl[ETH_COALESCE_PKT_PER_DESC];
191 struct tx_sw_desc { /* SW state per Tx descriptor */
192 struct rte_mbuf *mbuf;
193 struct ulptx_sgl *sgl;
194 struct tx_eth_coal_desc coalesce;
197 enum cxgbe_txq_state {
198 EQ_STOPPED = (1 << 0),
201 enum cxgbe_rxq_state {
202 IQ_STOPPED = (1 << 0),
205 struct eth_coalesce {
212 __u8 ethmacdst[ETHER_ADDR_LEN];
213 __u8 ethmacsrc[ETHER_ADDR_LEN];
219 struct tx_desc *desc; /* address of HW Tx descriptor ring */
220 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
221 struct sge_qstat *stat; /* queue status entry */
222 struct eth_coalesce coalesce; /* coalesce info */
224 uint64_t phys_addr; /* physical address of the ring */
226 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
227 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
229 unsigned int cntxt_id; /* SGE relative QID for the Tx Q */
230 unsigned int in_use; /* # of in-use Tx descriptors */
231 unsigned int size; /* # of descriptors */
232 unsigned int cidx; /* SW consumer index */
233 unsigned int pidx; /* producer index */
234 unsigned int dbidx; /* last idx when db ring was done */
235 unsigned int equeidx; /* last sent credit request */
236 unsigned int last_pidx; /* last pidx recorded by tx monitor */
237 unsigned int last_coal_idx;/* last coal-idx recorded by tx monitor */
240 int db_disabled; /* doorbell state */
241 unsigned short db_pidx; /* doorbell producer index */
242 unsigned short db_pidx_inc; /* doorbell producer increment */
245 struct sge_eth_tx_stats { /* Ethernet tx queue statistics */
246 u64 pkts; /* # of ethernet packets */
247 u64 tx_bytes; /* # of ethernet bytes */
248 u64 tso; /* # of TSO requests */
249 u64 tx_cso; /* # of Tx checksum offloads */
250 u64 vlan_ins; /* # of Tx VLAN insertions */
251 u64 mapping_err; /* # of I/O MMU packet mapping errors */
252 u64 coal_wr; /* # of coalesced wr */
253 u64 coal_pkts; /* # of coalesced packets */
256 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
258 struct rte_eth_dev *eth_dev; /* port that this queue belongs to */
259 struct rte_eth_dev_data *data;
260 struct sge_eth_tx_stats stats; /* queue statistics */
261 rte_spinlock_t txq_lock;
263 unsigned int flags; /* flags for state of the queue */
264 } __rte_cache_aligned;
266 struct sge_ctrl_txq { /* State for an SGE control Tx queue */
267 struct sge_txq q; /* txq */
268 struct adapter *adapter; /* adapter associated with this queue */
269 rte_spinlock_t ctrlq_lock; /* control queue lock */
270 u8 full; /* the Tx ring is full */
271 u64 txp; /* number of transmits */
272 struct rte_mempool *mb_pool; /* mempool to generate ctrl pkts */
273 } __rte_cache_aligned;
276 struct sge_eth_txq *ethtxq;
277 struct sge_eth_rxq *ethrxq;
278 struct sge_rspq fw_evtq __rte_cache_aligned;
279 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
281 u16 max_ethqsets; /* # of available Ethernet queue sets */
282 u32 stat_len; /* length of status page at ring end */
283 u32 pktshift; /* padding between CPL & packet data */
285 /* response queue interrupt parameters */
286 u16 timer_val[SGE_NTIMERS];
287 u8 counter_val[SGE_NCOUNTERS];
289 u32 fl_align; /* response queue message alignment */
290 u32 fl_pg_order; /* large page allocation size */
291 u32 fl_starve_thres; /* Free List starvation threshold */
294 #define T4_OS_NEEDS_MBOX_LOCKING 1
297 * OS Lock/List primitives for those interfaces in the Common Code which
302 TAILQ_ENTRY(mbox_entry) next;
305 TAILQ_HEAD(mbox_list, mbox_entry);
307 struct adapter_devargs {
310 bool tx_mode_latency;
316 struct rte_pci_device *pdev; /* associated rte pci device */
317 struct rte_eth_dev *eth_dev; /* first port's rte eth device */
318 struct adapter_params params; /* adapter parameters */
319 struct port_info *port[MAX_NPORTS];/* ports belonging to this adapter */
320 struct sge sge; /* associated SGE */
322 /* support for single-threading access to adapter mailbox registers */
323 struct mbox_list mbox_list;
324 rte_spinlock_t mbox_lock;
326 u8 *regs; /* pointer to registers region */
327 u8 *bar2; /* pointer to bar2 region */
328 unsigned long flags; /* adapter flags */
329 unsigned int mbox; /* associated mailbox */
330 unsigned int pf; /* associated physical function id */
332 unsigned int vpd_busy;
333 unsigned int vpd_flag;
335 int use_unpacked_mode; /* unpacked rx mode state */
336 rte_spinlock_t win0_lock;
338 rte_spinlock_t flow_lock; /* Serialize access for rte_flow ops */
340 unsigned int clipt_start; /* CLIP table start */
341 unsigned int clipt_end; /* CLIP table end */
342 unsigned int l2t_start; /* Layer 2 table start */
343 unsigned int l2t_end; /* Layer 2 table end */
344 struct clip_tbl *clipt; /* CLIP table */
345 struct l2t_data *l2t; /* Layer 2 table */
346 struct smt_data *smt; /* Source mac table */
347 struct mpstcam_table *mpstcam;
349 struct tid_info tids; /* Info used to access TID related tables */
351 struct adapter_devargs devargs;
355 * t4_os_rwlock_init - initialize rwlock
358 static inline void t4_os_rwlock_init(rte_rwlock_t *lock)
360 rte_rwlock_init(lock);
364 * t4_os_write_lock - get a write lock
367 static inline void t4_os_write_lock(rte_rwlock_t *lock)
369 rte_rwlock_write_lock(lock);
373 * t4_os_write_unlock - unlock a write lock
376 static inline void t4_os_write_unlock(rte_rwlock_t *lock)
378 rte_rwlock_write_unlock(lock);
382 * ethdev2pinfo - return the port_info structure associated with a rte_eth_dev
383 * @dev: the rte_eth_dev
385 * Return the struct port_info associated with a rte_eth_dev
387 static inline struct port_info *ethdev2pinfo(const struct rte_eth_dev *dev)
389 return dev->data->dev_private;
393 * adap2pinfo - return the port_info of a port
395 * @idx: the port index
397 * Return the port_info structure for the port of the given index.
399 static inline struct port_info *adap2pinfo(const struct adapter *adap, int idx)
401 return adap->port[idx];
405 * ethdev2adap - return the adapter structure associated with a rte_eth_dev
406 * @dev: the rte_eth_dev
408 * Return the struct adapter associated with a rte_eth_dev
410 static inline struct adapter *ethdev2adap(const struct rte_eth_dev *dev)
412 return ethdev2pinfo(dev)->adapter;
415 #define CXGBE_PCI_REG(reg) rte_read32(reg)
417 static inline uint64_t cxgbe_read_addr64(volatile void *addr)
419 uint64_t val = CXGBE_PCI_REG(addr);
420 uint64_t val2 = CXGBE_PCI_REG(((volatile uint8_t *)(addr) + 4));
422 val2 = (uint64_t)(val2 << 32);
427 static inline uint32_t cxgbe_read_addr(volatile void *addr)
429 return CXGBE_PCI_REG(addr);
432 #define CXGBE_PCI_REG_ADDR(adap, reg) \
433 ((volatile uint32_t *)((char *)(adap)->regs + (reg)))
435 #define CXGBE_READ_REG(adap, reg) \
436 cxgbe_read_addr(CXGBE_PCI_REG_ADDR((adap), (reg)))
438 #define CXGBE_READ_REG64(adap, reg) \
439 cxgbe_read_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)))
441 #define CXGBE_PCI_REG_WRITE(reg, value) rte_write32((value), (reg))
443 #define CXGBE_PCI_REG_WRITE_RELAXED(reg, value) \
444 rte_write32_relaxed((value), (reg))
446 #define CXGBE_WRITE_REG(adap, reg, value) \
447 CXGBE_PCI_REG_WRITE(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
449 #define CXGBE_WRITE_REG_RELAXED(adap, reg, value) \
450 CXGBE_PCI_REG_WRITE_RELAXED(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
452 static inline uint64_t cxgbe_write_addr64(volatile void *addr, uint64_t val)
454 CXGBE_PCI_REG_WRITE(addr, val);
455 CXGBE_PCI_REG_WRITE(((volatile uint8_t *)(addr) + 4), (val >> 32));
459 #define CXGBE_WRITE_REG64(adap, reg, value) \
460 cxgbe_write_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
463 * t4_read_reg - read a HW register
464 * @adapter: the adapter
465 * @reg_addr: the register address
467 * Returns the 32-bit value of the given HW register.
469 static inline u32 t4_read_reg(struct adapter *adapter, u32 reg_addr)
471 return CXGBE_READ_REG(adapter, reg_addr);
475 * t4_write_reg - write a HW register with barrier
476 * @adapter: the adapter
477 * @reg_addr: the register address
478 * @val: the value to write
480 * Write a 32-bit value into the given HW register.
482 static inline void t4_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
484 CXGBE_WRITE_REG(adapter, reg_addr, val);
488 * t4_write_reg_relaxed - write a HW register with no barrier
489 * @adapter: the adapter
490 * @reg_addr: the register address
491 * @val: the value to write
493 * Write a 32-bit value into the given HW register.
495 static inline void t4_write_reg_relaxed(struct adapter *adapter, u32 reg_addr,
498 CXGBE_WRITE_REG_RELAXED(adapter, reg_addr, val);
502 * t4_read_reg64 - read a 64-bit HW register
503 * @adapter: the adapter
504 * @reg_addr: the register address
506 * Returns the 64-bit value of the given HW register.
508 static inline u64 t4_read_reg64(struct adapter *adapter, u32 reg_addr)
510 return CXGBE_READ_REG64(adapter, reg_addr);
514 * t4_write_reg64 - write a 64-bit HW register
515 * @adapter: the adapter
516 * @reg_addr: the register address
517 * @val: the value to write
519 * Write a 64-bit value into the given HW register.
521 static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr,
524 CXGBE_WRITE_REG64(adapter, reg_addr, val);
527 #define PCI_STATUS 0x06 /* 16 bits */
528 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
529 #define PCI_CAPABILITY_LIST 0x34
530 /* Offset of first capability list entry */
531 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
532 #define PCI_CAP_LIST_ID 0 /* Capability ID */
533 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
534 #define PCI_EXP_DEVCTL 0x0008 /* Device control */
535 #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
536 #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
537 #define PCI_EXP_DEVCTL_PAYLOAD 0x00E0 /* Max payload */
538 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
539 #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
540 #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
541 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */
544 * t4_os_pci_write_cfg4 - 32-bit write to PCI config space
545 * @adapter: the adapter
546 * @addr: the register address
547 * @val: the value to write
549 * Write a 32-bit value into the given register in PCI config space.
551 static inline void t4_os_pci_write_cfg4(struct adapter *adapter, size_t addr,
556 if (rte_pci_write_config(adapter->pdev, &val32, sizeof(val32),
558 dev_err(adapter, "Can't write to PCI config space\n");
562 * t4_os_pci_read_cfg4 - read a 32-bit value from PCI config space
563 * @adapter: the adapter
564 * @addr: the register address
565 * @val: where to store the value read
567 * Read a 32-bit value from the given register in PCI config space.
569 static inline void t4_os_pci_read_cfg4(struct adapter *adapter, size_t addr,
572 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
574 dev_err(adapter, "Can't read from PCI config space\n");
578 * t4_os_pci_write_cfg2 - 16-bit write to PCI config space
579 * @adapter: the adapter
580 * @addr: the register address
581 * @val: the value to write
583 * Write a 16-bit value into the given register in PCI config space.
585 static inline void t4_os_pci_write_cfg2(struct adapter *adapter, size_t addr,
590 if (rte_pci_write_config(adapter->pdev, &val16, sizeof(val16),
592 dev_err(adapter, "Can't write to PCI config space\n");
596 * t4_os_pci_read_cfg2 - read a 16-bit value from PCI config space
597 * @adapter: the adapter
598 * @addr: the register address
599 * @val: where to store the value read
601 * Read a 16-bit value from the given register in PCI config space.
603 static inline void t4_os_pci_read_cfg2(struct adapter *adapter, size_t addr,
606 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
608 dev_err(adapter, "Can't read from PCI config space\n");
612 * t4_os_pci_read_cfg - read a 8-bit value from PCI config space
613 * @adapter: the adapter
614 * @addr: the register address
615 * @val: where to store the value read
617 * Read a 8-bit value from the given register in PCI config space.
619 static inline void t4_os_pci_read_cfg(struct adapter *adapter, size_t addr,
622 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
624 dev_err(adapter, "Can't read from PCI config space\n");
628 * t4_os_find_pci_capability - lookup a capability in the PCI capability list
629 * @adapter: the adapter
630 * @cap: the capability
632 * Return the address of the given capability within the PCI capability list.
634 static inline int t4_os_find_pci_capability(struct adapter *adapter, int cap)
641 t4_os_pci_read_cfg2(adapter, PCI_STATUS, &status);
642 if (!(status & PCI_STATUS_CAP_LIST)) {
643 dev_err(adapter, "PCIe capability reading failed\n");
647 t4_os_pci_read_cfg(adapter, PCI_CAPABILITY_LIST, &pos);
648 while (ttl-- && pos >= 0x40) {
650 t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_ID), &id);
658 t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_NEXT), &pos);
664 * t4_os_set_hw_addr - store a port's MAC address in SW
665 * @adapter: the adapter
666 * @port_idx: the port index
667 * @hw_addr: the Ethernet address
669 * Store the Ethernet address of the given port in SW. Called by the
670 * common code when it retrieves a port's Ethernet address from EEPROM.
672 static inline void t4_os_set_hw_addr(struct adapter *adapter, int port_idx,
675 struct port_info *pi = adap2pinfo(adapter, port_idx);
677 rte_ether_addr_copy((struct rte_ether_addr *)hw_addr,
678 &pi->eth_dev->data->mac_addrs[0]);
682 * t4_os_lock_init - initialize spinlock
683 * @lock: the spinlock
685 static inline void t4_os_lock_init(rte_spinlock_t *lock)
687 rte_spinlock_init(lock);
691 * t4_os_lock - spin until lock is acquired
692 * @lock: the spinlock
694 static inline void t4_os_lock(rte_spinlock_t *lock)
696 rte_spinlock_lock(lock);
700 * t4_os_unlock - unlock a spinlock
701 * @lock: the spinlock
703 static inline void t4_os_unlock(rte_spinlock_t *lock)
705 rte_spinlock_unlock(lock);
709 * t4_os_trylock - try to get a lock
710 * @lock: the spinlock
712 static inline int t4_os_trylock(rte_spinlock_t *lock)
714 return rte_spinlock_trylock(lock);
718 * t4_os_init_list_head - initialize
719 * @head: head of list to initialize [to empty]
721 static inline void t4_os_init_list_head(struct mbox_list *head)
726 static inline struct mbox_entry *t4_os_list_first_entry(struct mbox_list *head)
728 return TAILQ_FIRST(head);
732 * t4_os_atomic_add_tail - Enqueue list element atomically onto list
733 * @new: the entry to be addded to the queue
734 * @head: current head of the linked list
735 * @lock: lock to use to guarantee atomicity
737 static inline void t4_os_atomic_add_tail(struct mbox_entry *entry,
738 struct mbox_list *head,
739 rte_spinlock_t *lock)
742 TAILQ_INSERT_TAIL(head, entry, next);
747 * t4_os_atomic_list_del - Dequeue list element atomically from list
748 * @entry: the entry to be remove/dequeued from the list.
749 * @lock: the spinlock
751 static inline void t4_os_atomic_list_del(struct mbox_entry *entry,
752 struct mbox_list *head,
753 rte_spinlock_t *lock)
756 TAILQ_REMOVE(head, entry, next);
761 * t4_init_completion - initialize completion
762 * @c: the completion context
764 static inline void t4_init_completion(struct t4_completion *c)
767 t4_os_lock_init(&c->lock);
771 * t4_complete - set completion as done
772 * @c: the completion context
774 static inline void t4_complete(struct t4_completion *c)
776 t4_os_lock(&c->lock);
778 t4_os_unlock(&c->lock);
782 * cxgbe_port_viid - get the VI id of a port
783 * @dev: the device for the port
785 * Return the VI id of the given port.
787 static inline unsigned int cxgbe_port_viid(const struct rte_eth_dev *dev)
789 return ethdev2pinfo(dev)->viid;
792 void *t4_alloc_mem(size_t size);
793 void t4_free_mem(void *addr);
794 #define t4_os_alloc(_size) t4_alloc_mem((_size))
795 #define t4_os_free(_ptr) t4_free_mem((_ptr))
797 void t4_os_portmod_changed(const struct adapter *adap, int port_id);
798 void t4_os_link_changed(struct adapter *adap, int port_id);
800 void reclaim_completed_tx(struct sge_txq *q);
801 void t4_free_sge_resources(struct adapter *adap);
802 void t4_sge_tx_monitor_start(struct adapter *adap);
803 void t4_sge_tx_monitor_stop(struct adapter *adap);
804 int t4_eth_xmit(struct sge_eth_txq *txq, struct rte_mbuf *mbuf,
806 int t4_mgmt_tx(struct sge_ctrl_txq *txq, struct rte_mbuf *mbuf);
807 int t4_sge_init(struct adapter *adap);
808 int t4vf_sge_init(struct adapter *adap);
809 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
810 struct rte_eth_dev *eth_dev, uint16_t queue_id,
811 unsigned int iqid, int socket_id);
812 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
813 struct rte_eth_dev *eth_dev, uint16_t queue_id,
814 unsigned int iqid, int socket_id);
815 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *rspq, bool fwevtq,
816 struct rte_eth_dev *eth_dev, int intr_idx,
817 struct sge_fl *fl, rspq_handler_t handler,
818 int cong, struct rte_mempool *mp, int queue_id,
820 int t4_sge_eth_txq_start(struct sge_eth_txq *txq);
821 int t4_sge_eth_txq_stop(struct sge_eth_txq *txq);
822 void t4_sge_eth_txq_release(struct adapter *adap, struct sge_eth_txq *txq);
823 int t4_sge_eth_rxq_start(struct adapter *adap, struct sge_eth_rxq *rxq);
824 int t4_sge_eth_rxq_stop(struct adapter *adap, struct sge_eth_rxq *rxq);
825 void t4_sge_eth_rxq_release(struct adapter *adap, struct sge_eth_rxq *rxq);
826 void t4_sge_eth_clear_queues(struct port_info *pi);
827 void t4_sge_eth_release_queues(struct port_info *pi);
828 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
830 int cxgbe_poll(struct sge_rspq *q, struct rte_mbuf **rx_pkts,
831 unsigned int budget, unsigned int *work_done);
832 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues);
833 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t flags);
835 #endif /* __T4_ADAPTER_H__ */