4 * Copyright(c) 2014-2017 Chelsio Communications.
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8 * modification, are permitted provided that the following conditions
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34 /* This file should not be included directly. Include common.h instead. */
36 #ifndef __T4_ADAPTER_H__
37 #define __T4_ADAPTER_H__
39 #include <rte_bus_pci.h>
43 #include "cxgbe_compat.h"
44 #include "t4_regs_values.h"
47 MAX_ETH_QSETS = 64, /* # of Ethernet Tx/Rx queue sets */
54 PORT_RSS_DONE = (1 << 0),
58 struct adapter *adapter; /* adapter that this port belongs to */
59 struct rte_eth_dev *eth_dev; /* associated rte eth device */
60 struct port_stats stats_base; /* port statistics base */
61 struct link_config link_cfg; /* link configuration info */
63 unsigned long flags; /* port related flags */
64 short int xact_addr_filt; /* index of exact MAC address filter */
66 u16 viid; /* associated virtual interface id */
67 s8 mdio_addr; /* address of the PHY */
68 u8 port_type; /* firmware port type */
69 u8 mod_type; /* firmware module type */
70 u8 port_id; /* physical port ID */
71 u8 tx_chan; /* associated channel */
73 u8 n_rx_qsets; /* # of rx qsets */
74 u8 n_tx_qsets; /* # of tx qsets */
75 u8 first_qset; /* index of first qset */
77 u16 *rss; /* rss table */
78 u8 rss_mode; /* rss mode */
79 u16 rss_size; /* size of VI's RSS table slice */
80 u64 rss_hf; /* RSS Hash Function */
83 /* Enable or disable autonegotiation. If this is set to enable,
84 * the forced link modes above are completely ignored.
86 #define AUTONEG_DISABLE 0x00
87 #define AUTONEG_ENABLE 0x01
89 enum { /* adapter flags */
90 FULL_INIT_DONE = (1 << 0),
92 USING_MSIX = (1 << 2),
93 FW_QUEUE_BOUND = (1 << 3),
95 CFG_QUEUES = (1 << 5),
99 struct rx_sw_desc { /* SW state per Rx descriptor */
100 void *buf; /* struct page or mbuf */
104 struct sge_fl { /* SGE free-buffer queue state */
106 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
108 dma_addr_t addr; /* bus address of HW ring start */
109 __be64 *desc; /* address of HW Rx descriptor ring */
111 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
112 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
114 unsigned int cntxt_id; /* SGE relative QID for the free list */
115 unsigned int size; /* capacity of free list */
117 unsigned int avail; /* # of available Rx buffers */
118 unsigned int pend_cred; /* new buffers since last FL DB ring */
119 unsigned int cidx; /* consumer index */
120 unsigned int pidx; /* producer index */
122 unsigned long alloc_failed; /* # of times buffer allocation failed */
123 unsigned long low; /* # of times momentarily starving */
126 #define MAX_MBUF_FRAGS (16384 / 512 + 2)
128 /* A packet gather list */
131 struct rte_mbuf *mbufs[MAX_MBUF_FRAGS];
133 void *va; /* virtual address of first byte */
134 unsigned int nfrags; /* # of fragments */
135 unsigned int tot_len; /* total length of fragments */
136 bool usembufs; /* use mbufs for fragments */
139 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
140 const struct pkt_gl *gl);
142 struct sge_rspq { /* state for an SGE response queue */
143 struct adapter *adapter; /* adapter that this queue belongs to */
144 struct rte_eth_dev *eth_dev; /* associated rte eth device */
145 struct rte_mempool *mb_pool; /* associated mempool */
147 dma_addr_t phys_addr; /* physical address of the ring */
148 __be64 *desc; /* address of HW response ring */
149 const __be64 *cur_desc; /* current descriptor in queue */
151 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
152 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
153 struct sge_qstat *stat;
155 unsigned int cidx; /* consumer index */
156 unsigned int gts_idx; /* last gts write sent */
157 unsigned int iqe_len; /* entry size */
158 unsigned int size; /* capacity of response queue */
159 int offset; /* offset into current Rx buffer */
161 u8 gen; /* current generation bit */
162 u8 intr_params; /* interrupt holdoff parameters */
163 u8 next_intr_params; /* holdoff params for next interrupt */
164 u8 pktcnt_idx; /* interrupt packet threshold */
165 u8 port_id; /* associated port-id */
166 u8 idx; /* queue index within its group */
167 u16 cntxt_id; /* SGE relative QID for the response Q */
168 u16 abs_id; /* absolute SGE id for the response q */
170 rspq_handler_t handler; /* associated handler for this response q */
173 struct sge_eth_rx_stats { /* Ethernet rx queue statistics */
174 u64 pkts; /* # of ethernet packets */
175 u64 rx_bytes; /* # of ethernet bytes */
176 u64 rx_cso; /* # of Rx checksum offloads */
177 u64 vlan_ex; /* # of Rx VLAN extractions */
178 u64 rx_drops; /* # of packets dropped due to no mem */
181 struct sge_eth_rxq { /* a SW Ethernet Rx queue */
182 struct sge_rspq rspq;
184 struct sge_eth_rx_stats stats;
185 bool usembufs; /* one ingress packet per mbuf FL buffer */
186 } __rte_cache_aligned;
189 * Currently there are two types of coalesce WR. Type 0 needs 48 bytes per
190 * packet (if one sgl is present) and type 1 needs 32 bytes. This means
191 * that type 0 can fit a maximum of 10 packets per WR and type 1 can fit
192 * 15 packets. We need to keep track of the mbuf pointers in a coalesce WR
193 * to be able to free those mbufs when we get completions back from the FW.
194 * Allocating the maximum number of pointers in every tx desc is a waste
195 * of memory resources so we only store 2 pointers per tx desc which should
196 * be enough since a tx desc can only fit 2 packets in the best case
197 * scenario where a packet needs 32 bytes.
199 #define ETH_COALESCE_PKT_NUM 15
200 #define ETH_COALESCE_PKT_PER_DESC 2
202 struct tx_eth_coal_desc {
203 struct rte_mbuf *mbuf[ETH_COALESCE_PKT_PER_DESC];
204 struct ulptx_sgl *sgl[ETH_COALESCE_PKT_PER_DESC];
212 struct tx_sw_desc { /* SW state per Tx descriptor */
213 struct rte_mbuf *mbuf;
214 struct ulptx_sgl *sgl;
215 struct tx_eth_coal_desc coalesce;
219 EQ_STOPPED = (1 << 0),
222 struct eth_coalesce {
232 struct tx_desc *desc; /* address of HW Tx descriptor ring */
233 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
234 struct sge_qstat *stat; /* queue status entry */
235 struct eth_coalesce coalesce; /* coalesce info */
237 uint64_t phys_addr; /* physical address of the ring */
239 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
240 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
242 unsigned int cntxt_id; /* SGE relative QID for the Tx Q */
243 unsigned int in_use; /* # of in-use Tx descriptors */
244 unsigned int size; /* # of descriptors */
245 unsigned int cidx; /* SW consumer index */
246 unsigned int pidx; /* producer index */
247 unsigned int dbidx; /* last idx when db ring was done */
248 unsigned int equeidx; /* last sent credit request */
249 unsigned int last_pidx; /* last pidx recorded by tx monitor */
250 unsigned int last_coal_idx;/* last coal-idx recorded by tx monitor */
252 int db_disabled; /* doorbell state */
253 unsigned short db_pidx; /* doorbell producer index */
254 unsigned short db_pidx_inc; /* doorbell producer increment */
257 struct sge_eth_tx_stats { /* Ethernet tx queue statistics */
258 u64 pkts; /* # of ethernet packets */
259 u64 tx_bytes; /* # of ethernet bytes */
260 u64 tso; /* # of TSO requests */
261 u64 tx_cso; /* # of Tx checksum offloads */
262 u64 vlan_ins; /* # of Tx VLAN insertions */
263 u64 mapping_err; /* # of I/O MMU packet mapping errors */
264 u64 coal_wr; /* # of coalesced wr */
265 u64 coal_pkts; /* # of coalesced packets */
268 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
270 struct rte_eth_dev *eth_dev; /* port that this queue belongs to */
271 struct rte_eth_dev_data *data;
272 struct sge_eth_tx_stats stats; /* queue statistics */
273 rte_spinlock_t txq_lock;
275 unsigned int flags; /* flags for state of the queue */
276 } __rte_cache_aligned;
279 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
280 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
281 struct sge_rspq fw_evtq __rte_cache_aligned;
283 u16 max_ethqsets; /* # of available Ethernet queue sets */
284 u32 stat_len; /* length of status page at ring end */
285 u32 pktshift; /* padding between CPL & packet data */
287 /* response queue interrupt parameters */
288 u16 timer_val[SGE_NTIMERS];
289 u8 counter_val[SGE_NCOUNTERS];
291 u32 fl_align; /* response queue message alignment */
292 u32 fl_pg_order; /* large page allocation size */
293 u32 fl_starve_thres; /* Free List starvation threshold */
296 #define T4_OS_NEEDS_MBOX_LOCKING 1
299 * OS Lock/List primitives for those interfaces in the Common Code which
304 TAILQ_ENTRY(mbox_entry) next;
307 TAILQ_HEAD(mbox_list, mbox_entry);
310 struct rte_pci_device *pdev; /* associated rte pci device */
311 struct rte_eth_dev *eth_dev; /* first port's rte eth device */
312 struct adapter_params params; /* adapter parameters */
313 struct port_info *port[MAX_NPORTS];/* ports belonging to this adapter */
314 struct sge sge; /* associated SGE */
316 /* support for single-threading access to adapter mailbox registers */
317 struct mbox_list mbox_list;
318 rte_spinlock_t mbox_lock;
320 u8 *regs; /* pointer to registers region */
321 u8 *bar2; /* pointer to bar2 region */
322 unsigned long flags; /* adapter flags */
323 unsigned int mbox; /* associated mailbox */
324 unsigned int pf; /* associated physical function id */
326 unsigned int vpd_busy;
327 unsigned int vpd_flag;
329 int use_unpacked_mode; /* unpacked rx mode state */
333 * adap2pinfo - return the port_info of a port
335 * @idx: the port index
337 * Return the port_info structure for the port of the given index.
339 static inline struct port_info *adap2pinfo(const struct adapter *adap, int idx)
341 return adap->port[idx];
344 #define CXGBE_PCI_REG(reg) rte_read32(reg)
346 static inline uint64_t cxgbe_read_addr64(volatile void *addr)
348 uint64_t val = CXGBE_PCI_REG(addr);
349 uint64_t val2 = CXGBE_PCI_REG(((volatile uint8_t *)(addr) + 4));
351 val2 = (uint64_t)(val2 << 32);
356 static inline uint32_t cxgbe_read_addr(volatile void *addr)
358 return CXGBE_PCI_REG(addr);
361 #define CXGBE_PCI_REG_ADDR(adap, reg) \
362 ((volatile uint32_t *)((char *)(adap)->regs + (reg)))
364 #define CXGBE_READ_REG(adap, reg) \
365 cxgbe_read_addr(CXGBE_PCI_REG_ADDR((adap), (reg)))
367 #define CXGBE_READ_REG64(adap, reg) \
368 cxgbe_read_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)))
370 #define CXGBE_PCI_REG_WRITE(reg, value) rte_write32((value), (reg))
372 #define CXGBE_PCI_REG_WRITE_RELAXED(reg, value) \
373 rte_write32_relaxed((value), (reg))
375 #define CXGBE_WRITE_REG(adap, reg, value) \
376 CXGBE_PCI_REG_WRITE(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
378 #define CXGBE_WRITE_REG_RELAXED(adap, reg, value) \
379 CXGBE_PCI_REG_WRITE_RELAXED(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
381 static inline uint64_t cxgbe_write_addr64(volatile void *addr, uint64_t val)
383 CXGBE_PCI_REG_WRITE(addr, val);
384 CXGBE_PCI_REG_WRITE(((volatile uint8_t *)(addr) + 4), (val >> 32));
388 #define CXGBE_WRITE_REG64(adap, reg, value) \
389 cxgbe_write_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
392 * t4_read_reg - read a HW register
393 * @adapter: the adapter
394 * @reg_addr: the register address
396 * Returns the 32-bit value of the given HW register.
398 static inline u32 t4_read_reg(struct adapter *adapter, u32 reg_addr)
400 u32 val = CXGBE_READ_REG(adapter, reg_addr);
402 CXGBE_DEBUG_REG(adapter, "read register 0x%x value 0x%x\n", reg_addr,
408 * t4_write_reg - write a HW register with barrier
409 * @adapter: the adapter
410 * @reg_addr: the register address
411 * @val: the value to write
413 * Write a 32-bit value into the given HW register.
415 static inline void t4_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
417 CXGBE_DEBUG_REG(adapter, "setting register 0x%x to 0x%x\n", reg_addr,
419 CXGBE_WRITE_REG(adapter, reg_addr, val);
423 * t4_write_reg_relaxed - write a HW register with no barrier
424 * @adapter: the adapter
425 * @reg_addr: the register address
426 * @val: the value to write
428 * Write a 32-bit value into the given HW register.
430 static inline void t4_write_reg_relaxed(struct adapter *adapter, u32 reg_addr,
433 CXGBE_DEBUG_REG(adapter, "setting register 0x%x to 0x%x\n", reg_addr,
435 CXGBE_WRITE_REG_RELAXED(adapter, reg_addr, val);
439 * t4_read_reg64 - read a 64-bit HW register
440 * @adapter: the adapter
441 * @reg_addr: the register address
443 * Returns the 64-bit value of the given HW register.
445 static inline u64 t4_read_reg64(struct adapter *adapter, u32 reg_addr)
447 u64 val = CXGBE_READ_REG64(adapter, reg_addr);
449 CXGBE_DEBUG_REG(adapter, "64-bit read register %#x value %#llx\n",
450 reg_addr, (unsigned long long)val);
455 * t4_write_reg64 - write a 64-bit HW register
456 * @adapter: the adapter
457 * @reg_addr: the register address
458 * @val: the value to write
460 * Write a 64-bit value into the given HW register.
462 static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr,
465 CXGBE_DEBUG_REG(adapter, "setting register %#x to %#llx\n", reg_addr,
466 (unsigned long long)val);
468 CXGBE_WRITE_REG64(adapter, reg_addr, val);
471 #define PCI_STATUS 0x06 /* 16 bits */
472 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
473 #define PCI_CAPABILITY_LIST 0x34
474 /* Offset of first capability list entry */
475 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
476 #define PCI_CAP_LIST_ID 0 /* Capability ID */
477 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
478 #define PCI_EXP_DEVCTL 0x0008 /* Device control */
479 #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
480 #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
481 #define PCI_EXP_DEVCTL_PAYLOAD 0x00E0 /* Max payload */
482 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
483 #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
484 #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
485 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */
488 * t4_os_pci_write_cfg4 - 32-bit write to PCI config space
489 * @adapter: the adapter
490 * @addr: the register address
491 * @val: the value to write
493 * Write a 32-bit value into the given register in PCI config space.
495 static inline void t4_os_pci_write_cfg4(struct adapter *adapter, size_t addr,
500 if (rte_pci_write_config(adapter->pdev, &val32, sizeof(val32),
502 dev_err(adapter, "Can't write to PCI config space\n");
506 * t4_os_pci_read_cfg4 - read a 32-bit value from PCI config space
507 * @adapter: the adapter
508 * @addr: the register address
509 * @val: where to store the value read
511 * Read a 32-bit value from the given register in PCI config space.
513 static inline void t4_os_pci_read_cfg4(struct adapter *adapter, size_t addr,
516 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
518 dev_err(adapter, "Can't read from PCI config space\n");
522 * t4_os_pci_write_cfg2 - 16-bit write to PCI config space
523 * @adapter: the adapter
524 * @addr: the register address
525 * @val: the value to write
527 * Write a 16-bit value into the given register in PCI config space.
529 static inline void t4_os_pci_write_cfg2(struct adapter *adapter, size_t addr,
534 if (rte_pci_write_config(adapter->pdev, &val16, sizeof(val16),
536 dev_err(adapter, "Can't write to PCI config space\n");
540 * t4_os_pci_read_cfg2 - read a 16-bit value from PCI config space
541 * @adapter: the adapter
542 * @addr: the register address
543 * @val: where to store the value read
545 * Read a 16-bit value from the given register in PCI config space.
547 static inline void t4_os_pci_read_cfg2(struct adapter *adapter, size_t addr,
550 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
552 dev_err(adapter, "Can't read from PCI config space\n");
556 * t4_os_pci_read_cfg - read a 8-bit value from PCI config space
557 * @adapter: the adapter
558 * @addr: the register address
559 * @val: where to store the value read
561 * Read a 8-bit value from the given register in PCI config space.
563 static inline void t4_os_pci_read_cfg(struct adapter *adapter, size_t addr,
566 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
568 dev_err(adapter, "Can't read from PCI config space\n");
572 * t4_os_find_pci_capability - lookup a capability in the PCI capability list
573 * @adapter: the adapter
574 * @cap: the capability
576 * Return the address of the given capability within the PCI capability list.
578 static inline int t4_os_find_pci_capability(struct adapter *adapter, int cap)
585 t4_os_pci_read_cfg2(adapter, PCI_STATUS, &status);
586 if (!(status & PCI_STATUS_CAP_LIST)) {
587 dev_err(adapter, "PCIe capability reading failed\n");
591 t4_os_pci_read_cfg(adapter, PCI_CAPABILITY_LIST, &pos);
592 while (ttl-- && pos >= 0x40) {
594 t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_ID), &id);
602 t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_NEXT), &pos);
608 * t4_os_set_hw_addr - store a port's MAC address in SW
609 * @adapter: the adapter
610 * @port_idx: the port index
611 * @hw_addr: the Ethernet address
613 * Store the Ethernet address of the given port in SW. Called by the
614 * common code when it retrieves a port's Ethernet address from EEPROM.
616 static inline void t4_os_set_hw_addr(struct adapter *adapter, int port_idx,
619 struct port_info *pi = adap2pinfo(adapter, port_idx);
621 ether_addr_copy((struct ether_addr *)hw_addr,
622 &pi->eth_dev->data->mac_addrs[0]);
626 * t4_os_lock_init - initialize spinlock
627 * @lock: the spinlock
629 static inline void t4_os_lock_init(rte_spinlock_t *lock)
631 rte_spinlock_init(lock);
635 * t4_os_lock - spin until lock is acquired
636 * @lock: the spinlock
638 static inline void t4_os_lock(rte_spinlock_t *lock)
640 rte_spinlock_lock(lock);
644 * t4_os_unlock - unlock a spinlock
645 * @lock: the spinlock
647 static inline void t4_os_unlock(rte_spinlock_t *lock)
649 rte_spinlock_unlock(lock);
653 * t4_os_trylock - try to get a lock
654 * @lock: the spinlock
656 static inline int t4_os_trylock(rte_spinlock_t *lock)
658 return rte_spinlock_trylock(lock);
662 * t4_os_init_list_head - initialize
663 * @head: head of list to initialize [to empty]
665 static inline void t4_os_init_list_head(struct mbox_list *head)
670 static inline struct mbox_entry *t4_os_list_first_entry(struct mbox_list *head)
672 return TAILQ_FIRST(head);
676 * t4_os_atomic_add_tail - Enqueue list element atomically onto list
677 * @new: the entry to be addded to the queue
678 * @head: current head of the linked list
679 * @lock: lock to use to guarantee atomicity
681 static inline void t4_os_atomic_add_tail(struct mbox_entry *entry,
682 struct mbox_list *head,
683 rte_spinlock_t *lock)
686 TAILQ_INSERT_TAIL(head, entry, next);
691 * t4_os_atomic_list_del - Dequeue list element atomically from list
692 * @entry: the entry to be remove/dequeued from the list.
693 * @lock: the spinlock
695 static inline void t4_os_atomic_list_del(struct mbox_entry *entry,
696 struct mbox_list *head,
697 rte_spinlock_t *lock)
700 TAILQ_REMOVE(head, entry, next);
704 void *t4_alloc_mem(size_t size);
705 void t4_free_mem(void *addr);
706 #define t4_os_alloc(_size) t4_alloc_mem((_size))
707 #define t4_os_free(_ptr) t4_free_mem((_ptr))
709 void t4_os_portmod_changed(const struct adapter *adap, int port_id);
710 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
712 void reclaim_completed_tx(struct sge_txq *q);
713 void t4_free_sge_resources(struct adapter *adap);
714 void t4_sge_tx_monitor_start(struct adapter *adap);
715 void t4_sge_tx_monitor_stop(struct adapter *adap);
716 int t4_eth_xmit(struct sge_eth_txq *txq, struct rte_mbuf *mbuf,
718 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
719 const struct pkt_gl *gl);
720 int t4_sge_init(struct adapter *adap);
721 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
722 struct rte_eth_dev *eth_dev, uint16_t queue_id,
723 unsigned int iqid, int socket_id);
724 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *rspq, bool fwevtq,
725 struct rte_eth_dev *eth_dev, int intr_idx,
726 struct sge_fl *fl, rspq_handler_t handler,
727 int cong, struct rte_mempool *mp, int queue_id,
729 int t4_sge_eth_txq_start(struct sge_eth_txq *txq);
730 int t4_sge_eth_txq_stop(struct sge_eth_txq *txq);
731 void t4_sge_eth_txq_release(struct adapter *adap, struct sge_eth_txq *txq);
732 int t4_sge_eth_rxq_start(struct adapter *adap, struct sge_rspq *rq);
733 int t4_sge_eth_rxq_stop(struct adapter *adap, struct sge_rspq *rq);
734 void t4_sge_eth_rxq_release(struct adapter *adap, struct sge_eth_rxq *rxq);
735 void t4_sge_eth_clear_queues(struct port_info *pi);
736 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
738 int cxgbe_poll(struct sge_rspq *q, struct rte_mbuf **rx_pkts,
739 unsigned int budget, unsigned int *work_done);
740 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues);
741 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t flags);
743 #endif /* __T4_ADAPTER_H__ */