4 * Copyright(c) 2014-2017 Chelsio Communications.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 /* This file should not be included directly. Include common.h instead. */
36 #ifndef __T4_ADAPTER_H__
37 #define __T4_ADAPTER_H__
42 #include "cxgbe_compat.h"
43 #include "t4_regs_values.h"
46 MAX_ETH_QSETS = 64, /* # of Ethernet Tx/Rx queue sets */
53 PORT_RSS_DONE = (1 << 0),
57 struct adapter *adapter; /* adapter that this port belongs to */
58 struct rte_eth_dev *eth_dev; /* associated rte eth device */
59 struct port_stats stats_base; /* port statistics base */
60 struct link_config link_cfg; /* link configuration info */
62 unsigned long flags; /* port related flags */
63 short int xact_addr_filt; /* index of exact MAC address filter */
65 u16 viid; /* associated virtual interface id */
66 s8 mdio_addr; /* address of the PHY */
67 u8 port_type; /* firmware port type */
68 u8 mod_type; /* firmware module type */
69 u8 port_id; /* physical port ID */
70 u8 tx_chan; /* associated channel */
72 u8 n_rx_qsets; /* # of rx qsets */
73 u8 n_tx_qsets; /* # of tx qsets */
74 u8 first_qset; /* index of first qset */
76 u16 *rss; /* rss table */
77 u8 rss_mode; /* rss mode */
78 u16 rss_size; /* size of VI's RSS table slice */
81 /* Enable or disable autonegotiation. If this is set to enable,
82 * the forced link modes above are completely ignored.
84 #define AUTONEG_DISABLE 0x00
85 #define AUTONEG_ENABLE 0x01
87 enum { /* adapter flags */
88 FULL_INIT_DONE = (1 << 0),
90 USING_MSIX = (1 << 2),
91 FW_QUEUE_BOUND = (1 << 3),
93 CFG_QUEUES = (1 << 5),
97 struct rx_sw_desc { /* SW state per Rx descriptor */
98 void *buf; /* struct page or mbuf */
102 struct sge_fl { /* SGE free-buffer queue state */
104 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
106 dma_addr_t addr; /* bus address of HW ring start */
107 __be64 *desc; /* address of HW Rx descriptor ring */
109 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
110 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
112 unsigned int cntxt_id; /* SGE relative QID for the free list */
113 unsigned int size; /* capacity of free list */
115 unsigned int avail; /* # of available Rx buffers */
116 unsigned int pend_cred; /* new buffers since last FL DB ring */
117 unsigned int cidx; /* consumer index */
118 unsigned int pidx; /* producer index */
120 unsigned long alloc_failed; /* # of times buffer allocation failed */
121 unsigned long low; /* # of times momentarily starving */
124 #define MAX_MBUF_FRAGS (16384 / 512 + 2)
126 /* A packet gather list */
129 struct rte_mbuf *mbufs[MAX_MBUF_FRAGS];
131 void *va; /* virtual address of first byte */
132 unsigned int nfrags; /* # of fragments */
133 unsigned int tot_len; /* total length of fragments */
134 bool usembufs; /* use mbufs for fragments */
137 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
138 const struct pkt_gl *gl);
140 struct sge_rspq { /* state for an SGE response queue */
141 struct adapter *adapter; /* adapter that this queue belongs to */
142 struct rte_eth_dev *eth_dev; /* associated rte eth device */
143 struct rte_mempool *mb_pool; /* associated mempool */
145 dma_addr_t phys_addr; /* physical address of the ring */
146 __be64 *desc; /* address of HW response ring */
147 const __be64 *cur_desc; /* current descriptor in queue */
149 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
150 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
151 struct sge_qstat *stat;
153 unsigned int cidx; /* consumer index */
154 unsigned int gts_idx; /* last gts write sent */
155 unsigned int iqe_len; /* entry size */
156 unsigned int size; /* capacity of response queue */
157 int offset; /* offset into current Rx buffer */
159 u8 gen; /* current generation bit */
160 u8 intr_params; /* interrupt holdoff parameters */
161 u8 next_intr_params; /* holdoff params for next interrupt */
162 u8 pktcnt_idx; /* interrupt packet threshold */
163 u8 port_id; /* associated port-id */
164 u8 idx; /* queue index within its group */
165 u16 cntxt_id; /* SGE relative QID for the response Q */
166 u16 abs_id; /* absolute SGE id for the response q */
168 rspq_handler_t handler; /* associated handler for this response q */
171 struct sge_eth_rx_stats { /* Ethernet rx queue statistics */
172 u64 pkts; /* # of ethernet packets */
173 u64 rx_bytes; /* # of ethernet bytes */
174 u64 rx_cso; /* # of Rx checksum offloads */
175 u64 vlan_ex; /* # of Rx VLAN extractions */
176 u64 rx_drops; /* # of packets dropped due to no mem */
179 struct sge_eth_rxq { /* a SW Ethernet Rx queue */
180 struct sge_rspq rspq;
182 struct sge_eth_rx_stats stats;
183 bool usembufs; /* one ingress packet per mbuf FL buffer */
184 } __rte_cache_aligned;
187 * Currently there are two types of coalesce WR. Type 0 needs 48 bytes per
188 * packet (if one sgl is present) and type 1 needs 32 bytes. This means
189 * that type 0 can fit a maximum of 10 packets per WR and type 1 can fit
190 * 15 packets. We need to keep track of the mbuf pointers in a coalesce WR
191 * to be able to free those mbufs when we get completions back from the FW.
192 * Allocating the maximum number of pointers in every tx desc is a waste
193 * of memory resources so we only store 2 pointers per tx desc which should
194 * be enough since a tx desc can only fit 2 packets in the best case
195 * scenario where a packet needs 32 bytes.
197 #define ETH_COALESCE_PKT_NUM 15
198 #define ETH_COALESCE_PKT_PER_DESC 2
200 struct tx_eth_coal_desc {
201 struct rte_mbuf *mbuf[ETH_COALESCE_PKT_PER_DESC];
202 struct ulptx_sgl *sgl[ETH_COALESCE_PKT_PER_DESC];
210 struct tx_sw_desc { /* SW state per Tx descriptor */
211 struct rte_mbuf *mbuf;
212 struct ulptx_sgl *sgl;
213 struct tx_eth_coal_desc coalesce;
217 EQ_STOPPED = (1 << 0),
220 struct eth_coalesce {
230 struct tx_desc *desc; /* address of HW Tx descriptor ring */
231 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
232 struct sge_qstat *stat; /* queue status entry */
233 struct eth_coalesce coalesce; /* coalesce info */
235 uint64_t phys_addr; /* physical address of the ring */
237 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
238 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
240 unsigned int cntxt_id; /* SGE relative QID for the Tx Q */
241 unsigned int in_use; /* # of in-use Tx descriptors */
242 unsigned int size; /* # of descriptors */
243 unsigned int cidx; /* SW consumer index */
244 unsigned int pidx; /* producer index */
245 unsigned int dbidx; /* last idx when db ring was done */
246 unsigned int equeidx; /* last sent credit request */
247 unsigned int last_pidx; /* last pidx recorded by tx monitor */
248 unsigned int last_coal_idx;/* last coal-idx recorded by tx monitor */
250 int db_disabled; /* doorbell state */
251 unsigned short db_pidx; /* doorbell producer index */
252 unsigned short db_pidx_inc; /* doorbell producer increment */
255 struct sge_eth_tx_stats { /* Ethernet tx queue statistics */
256 u64 pkts; /* # of ethernet packets */
257 u64 tx_bytes; /* # of ethernet bytes */
258 u64 tso; /* # of TSO requests */
259 u64 tx_cso; /* # of Tx checksum offloads */
260 u64 vlan_ins; /* # of Tx VLAN insertions */
261 u64 mapping_err; /* # of I/O MMU packet mapping errors */
262 u64 coal_wr; /* # of coalesced wr */
263 u64 coal_pkts; /* # of coalesced packets */
266 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
268 struct rte_eth_dev *eth_dev; /* port that this queue belongs to */
269 struct sge_eth_tx_stats stats; /* queue statistics */
270 rte_spinlock_t txq_lock;
272 unsigned int flags; /* flags for state of the queue */
273 } __rte_cache_aligned;
276 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
277 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
278 struct sge_rspq fw_evtq __rte_cache_aligned;
280 u16 max_ethqsets; /* # of available Ethernet queue sets */
281 u32 stat_len; /* length of status page at ring end */
282 u32 pktshift; /* padding between CPL & packet data */
284 /* response queue interrupt parameters */
285 u16 timer_val[SGE_NTIMERS];
286 u8 counter_val[SGE_NCOUNTERS];
288 u32 fl_align; /* response queue message alignment */
289 u32 fl_pg_order; /* large page allocation size */
290 u32 fl_starve_thres; /* Free List starvation threshold */
293 #define T4_OS_NEEDS_MBOX_LOCKING 1
296 * OS Lock/List primitives for those interfaces in the Common Code which
301 TAILQ_ENTRY(mbox_entry) next;
304 TAILQ_HEAD(mbox_list, mbox_entry);
307 struct rte_pci_device *pdev; /* associated rte pci device */
308 struct rte_eth_dev *eth_dev; /* first port's rte eth device */
309 struct adapter_params params; /* adapter parameters */
310 struct port_info port[MAX_NPORTS]; /* ports belonging to this adapter */
311 struct sge sge; /* associated SGE */
313 /* support for single-threading access to adapter mailbox registers */
314 struct mbox_list mbox_list;
315 rte_spinlock_t mbox_lock;
317 u8 *regs; /* pointer to registers region */
318 u8 *bar2; /* pointer to bar2 region */
319 unsigned long flags; /* adapter flags */
320 unsigned int mbox; /* associated mailbox */
321 unsigned int pf; /* associated physical function id */
323 unsigned int vpd_busy;
324 unsigned int vpd_flag;
326 int use_unpacked_mode; /* unpacked rx mode state */
329 #define CXGBE_PCI_REG(reg) rte_read32(reg)
331 static inline uint64_t cxgbe_read_addr64(volatile void *addr)
333 uint64_t val = CXGBE_PCI_REG(addr);
334 uint64_t val2 = CXGBE_PCI_REG(((volatile uint8_t *)(addr) + 4));
336 val2 = (uint64_t)(val2 << 32);
341 static inline uint32_t cxgbe_read_addr(volatile void *addr)
343 return CXGBE_PCI_REG(addr);
346 #define CXGBE_PCI_REG_ADDR(adap, reg) \
347 ((volatile uint32_t *)((char *)(adap)->regs + (reg)))
349 #define CXGBE_READ_REG(adap, reg) \
350 cxgbe_read_addr(CXGBE_PCI_REG_ADDR((adap), (reg)))
352 #define CXGBE_READ_REG64(adap, reg) \
353 cxgbe_read_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)))
355 #define CXGBE_PCI_REG_WRITE(reg, value) rte_write32((value), (reg))
357 #define CXGBE_PCI_REG_WRITE_RELAXED(reg, value) \
358 rte_write32_relaxed((value), (reg))
360 #define CXGBE_WRITE_REG(adap, reg, value) \
361 CXGBE_PCI_REG_WRITE(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
363 #define CXGBE_WRITE_REG_RELAXED(adap, reg, value) \
364 CXGBE_PCI_REG_WRITE_RELAXED(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
366 static inline uint64_t cxgbe_write_addr64(volatile void *addr, uint64_t val)
368 CXGBE_PCI_REG_WRITE(addr, val);
369 CXGBE_PCI_REG_WRITE(((volatile uint8_t *)(addr) + 4), (val >> 32));
373 #define CXGBE_WRITE_REG64(adap, reg, value) \
374 cxgbe_write_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
377 * t4_read_reg - read a HW register
378 * @adapter: the adapter
379 * @reg_addr: the register address
381 * Returns the 32-bit value of the given HW register.
383 static inline u32 t4_read_reg(struct adapter *adapter, u32 reg_addr)
385 u32 val = CXGBE_READ_REG(adapter, reg_addr);
387 CXGBE_DEBUG_REG(adapter, "read register 0x%x value 0x%x\n", reg_addr,
393 * t4_write_reg - write a HW register with barrier
394 * @adapter: the adapter
395 * @reg_addr: the register address
396 * @val: the value to write
398 * Write a 32-bit value into the given HW register.
400 static inline void t4_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
402 CXGBE_DEBUG_REG(adapter, "setting register 0x%x to 0x%x\n", reg_addr,
404 CXGBE_WRITE_REG(adapter, reg_addr, val);
408 * t4_write_reg_relaxed - write a HW register with no barrier
409 * @adapter: the adapter
410 * @reg_addr: the register address
411 * @val: the value to write
413 * Write a 32-bit value into the given HW register.
415 static inline void t4_write_reg_relaxed(struct adapter *adapter, u32 reg_addr,
418 CXGBE_DEBUG_REG(adapter, "setting register 0x%x to 0x%x\n", reg_addr,
420 CXGBE_WRITE_REG_RELAXED(adapter, reg_addr, val);
424 * t4_read_reg64 - read a 64-bit HW register
425 * @adapter: the adapter
426 * @reg_addr: the register address
428 * Returns the 64-bit value of the given HW register.
430 static inline u64 t4_read_reg64(struct adapter *adapter, u32 reg_addr)
432 u64 val = CXGBE_READ_REG64(adapter, reg_addr);
434 CXGBE_DEBUG_REG(adapter, "64-bit read register %#x value %#llx\n",
435 reg_addr, (unsigned long long)val);
440 * t4_write_reg64 - write a 64-bit HW register
441 * @adapter: the adapter
442 * @reg_addr: the register address
443 * @val: the value to write
445 * Write a 64-bit value into the given HW register.
447 static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr,
450 CXGBE_DEBUG_REG(adapter, "setting register %#x to %#llx\n", reg_addr,
451 (unsigned long long)val);
453 CXGBE_WRITE_REG64(adapter, reg_addr, val);
456 #define PCI_STATUS 0x06 /* 16 bits */
457 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
458 #define PCI_CAPABILITY_LIST 0x34
459 /* Offset of first capability list entry */
460 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
461 #define PCI_CAP_LIST_ID 0 /* Capability ID */
462 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
463 #define PCI_EXP_DEVCTL 0x0008 /* Device control */
464 #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
465 #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
466 #define PCI_EXP_DEVCTL_PAYLOAD 0x00E0 /* Max payload */
467 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
468 #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
469 #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
470 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */
473 * t4_os_pci_write_cfg4 - 32-bit write to PCI config space
474 * @adapter: the adapter
475 * @addr: the register address
476 * @val: the value to write
478 * Write a 32-bit value into the given register in PCI config space.
480 static inline void t4_os_pci_write_cfg4(struct adapter *adapter, size_t addr,
485 if (rte_pci_write_config(adapter->pdev, &val32, sizeof(val32),
487 dev_err(adapter, "Can't write to PCI config space\n");
491 * t4_os_pci_read_cfg4 - read a 32-bit value from PCI config space
492 * @adapter: the adapter
493 * @addr: the register address
494 * @val: where to store the value read
496 * Read a 32-bit value from the given register in PCI config space.
498 static inline void t4_os_pci_read_cfg4(struct adapter *adapter, size_t addr,
501 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
503 dev_err(adapter, "Can't read from PCI config space\n");
507 * t4_os_pci_write_cfg2 - 16-bit write to PCI config space
508 * @adapter: the adapter
509 * @addr: the register address
510 * @val: the value to write
512 * Write a 16-bit value into the given register in PCI config space.
514 static inline void t4_os_pci_write_cfg2(struct adapter *adapter, size_t addr,
519 if (rte_pci_write_config(adapter->pdev, &val16, sizeof(val16),
521 dev_err(adapter, "Can't write to PCI config space\n");
525 * t4_os_pci_read_cfg2 - read a 16-bit value from PCI config space
526 * @adapter: the adapter
527 * @addr: the register address
528 * @val: where to store the value read
530 * Read a 16-bit value from the given register in PCI config space.
532 static inline void t4_os_pci_read_cfg2(struct adapter *adapter, size_t addr,
535 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
537 dev_err(adapter, "Can't read from PCI config space\n");
541 * t4_os_pci_read_cfg - read a 8-bit value from PCI config space
542 * @adapter: the adapter
543 * @addr: the register address
544 * @val: where to store the value read
546 * Read a 8-bit value from the given register in PCI config space.
548 static inline void t4_os_pci_read_cfg(struct adapter *adapter, size_t addr,
551 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
553 dev_err(adapter, "Can't read from PCI config space\n");
557 * t4_os_find_pci_capability - lookup a capability in the PCI capability list
558 * @adapter: the adapter
559 * @cap: the capability
561 * Return the address of the given capability within the PCI capability list.
563 static inline int t4_os_find_pci_capability(struct adapter *adapter, int cap)
570 t4_os_pci_read_cfg2(adapter, PCI_STATUS, &status);
571 if (!(status & PCI_STATUS_CAP_LIST)) {
572 dev_err(adapter, "PCIe capability reading failed\n");
576 t4_os_pci_read_cfg(adapter, PCI_CAPABILITY_LIST, &pos);
577 while (ttl-- && pos >= 0x40) {
579 t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_ID), &id);
587 t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_NEXT), &pos);
593 * t4_os_set_hw_addr - store a port's MAC address in SW
594 * @adapter: the adapter
595 * @port_idx: the port index
596 * @hw_addr: the Ethernet address
598 * Store the Ethernet address of the given port in SW. Called by the
599 * common code when it retrieves a port's Ethernet address from EEPROM.
601 static inline void t4_os_set_hw_addr(struct adapter *adapter, int port_idx,
604 struct port_info *pi = &adapter->port[port_idx];
606 ether_addr_copy((struct ether_addr *)hw_addr,
607 &pi->eth_dev->data->mac_addrs[0]);
611 * t4_os_lock_init - initialize spinlock
612 * @lock: the spinlock
614 static inline void t4_os_lock_init(rte_spinlock_t *lock)
616 rte_spinlock_init(lock);
620 * t4_os_lock - spin until lock is acquired
621 * @lock: the spinlock
623 static inline void t4_os_lock(rte_spinlock_t *lock)
625 rte_spinlock_lock(lock);
629 * t4_os_unlock - unlock a spinlock
630 * @lock: the spinlock
632 static inline void t4_os_unlock(rte_spinlock_t *lock)
634 rte_spinlock_unlock(lock);
638 * t4_os_trylock - try to get a lock
639 * @lock: the spinlock
641 static inline int t4_os_trylock(rte_spinlock_t *lock)
643 return rte_spinlock_trylock(lock);
647 * t4_os_init_list_head - initialize
648 * @head: head of list to initialize [to empty]
650 static inline void t4_os_init_list_head(struct mbox_list *head)
655 static inline struct mbox_entry *t4_os_list_first_entry(struct mbox_list *head)
657 return TAILQ_FIRST(head);
661 * t4_os_atomic_add_tail - Enqueue list element atomically onto list
662 * @new: the entry to be addded to the queue
663 * @head: current head of the linked list
664 * @lock: lock to use to guarantee atomicity
666 static inline void t4_os_atomic_add_tail(struct mbox_entry *entry,
667 struct mbox_list *head,
668 rte_spinlock_t *lock)
671 TAILQ_INSERT_TAIL(head, entry, next);
676 * t4_os_atomic_list_del - Dequeue list element atomically from list
677 * @entry: the entry to be remove/dequeued from the list.
678 * @lock: the spinlock
680 static inline void t4_os_atomic_list_del(struct mbox_entry *entry,
681 struct mbox_list *head,
682 rte_spinlock_t *lock)
685 TAILQ_REMOVE(head, entry, next);
690 * adap2pinfo - return the port_info of a port
692 * @idx: the port index
694 * Return the port_info structure for the port of the given index.
696 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
698 return &adap->port[idx];
701 void *t4_alloc_mem(size_t size);
702 void t4_free_mem(void *addr);
703 #define t4_os_alloc(_size) t4_alloc_mem((_size))
704 #define t4_os_free(_ptr) t4_free_mem((_ptr))
706 void t4_os_portmod_changed(const struct adapter *adap, int port_id);
707 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
709 void reclaim_completed_tx(struct sge_txq *q);
710 void t4_free_sge_resources(struct adapter *adap);
711 void t4_sge_tx_monitor_start(struct adapter *adap);
712 void t4_sge_tx_monitor_stop(struct adapter *adap);
713 int t4_eth_xmit(struct sge_eth_txq *txq, struct rte_mbuf *mbuf,
715 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
716 const struct pkt_gl *gl);
717 int t4_sge_init(struct adapter *adap);
718 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
719 struct rte_eth_dev *eth_dev, uint16_t queue_id,
720 unsigned int iqid, int socket_id);
721 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *rspq, bool fwevtq,
722 struct rte_eth_dev *eth_dev, int intr_idx,
723 struct sge_fl *fl, rspq_handler_t handler,
724 int cong, struct rte_mempool *mp, int queue_id,
726 int t4_sge_eth_txq_start(struct sge_eth_txq *txq);
727 int t4_sge_eth_txq_stop(struct sge_eth_txq *txq);
728 void t4_sge_eth_txq_release(struct adapter *adap, struct sge_eth_txq *txq);
729 int t4_sge_eth_rxq_start(struct adapter *adap, struct sge_rspq *rq);
730 int t4_sge_eth_rxq_stop(struct adapter *adap, struct sge_rspq *rq);
731 void t4_sge_eth_rxq_release(struct adapter *adap, struct sge_eth_rxq *rxq);
732 void t4_sge_eth_clear_queues(struct port_info *pi);
733 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
735 int cxgbe_poll(struct sge_rspq *q, struct rte_mbuf **rx_pkts,
736 unsigned int budget, unsigned int *work_done);
737 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
739 #endif /* __T4_ADAPTER_H__ */