4 * Copyright(c) 2014-2017 Chelsio Communications.
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8 * modification, are permitted provided that the following conditions
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34 /* This file should not be included directly. Include common.h instead. */
36 #ifndef __T4_ADAPTER_H__
37 #define __T4_ADAPTER_H__
39 #include <rte_bus_pci.h>
43 #include "cxgbe_compat.h"
44 #include "t4_regs_values.h"
47 MAX_ETH_QSETS = 64, /* # of Ethernet Tx/Rx queue sets */
54 PORT_RSS_DONE = (1 << 0),
58 struct adapter *adapter; /* adapter that this port belongs to */
59 struct rte_eth_dev *eth_dev; /* associated rte eth device */
60 struct port_stats stats_base; /* port statistics base */
61 struct link_config link_cfg; /* link configuration info */
63 unsigned long flags; /* port related flags */
64 short int xact_addr_filt; /* index of exact MAC address filter */
66 u16 viid; /* associated virtual interface id */
67 s8 mdio_addr; /* address of the PHY */
68 u8 port_type; /* firmware port type */
69 u8 mod_type; /* firmware module type */
70 u8 port_id; /* physical port ID */
71 u8 pidx; /* port index for this PF */
72 u8 tx_chan; /* associated channel */
74 u8 n_rx_qsets; /* # of rx qsets */
75 u8 n_tx_qsets; /* # of tx qsets */
76 u8 first_qset; /* index of first qset */
78 u16 *rss; /* rss table */
79 u8 rss_mode; /* rss mode */
80 u16 rss_size; /* size of VI's RSS table slice */
81 u64 rss_hf; /* RSS Hash Function */
84 /* Enable or disable autonegotiation. If this is set to enable,
85 * the forced link modes above are completely ignored.
87 #define AUTONEG_DISABLE 0x00
88 #define AUTONEG_ENABLE 0x01
90 enum { /* adapter flags */
91 FULL_INIT_DONE = (1 << 0),
93 USING_MSIX = (1 << 2),
94 FW_QUEUE_BOUND = (1 << 3),
96 CFG_QUEUES = (1 << 5),
100 struct rx_sw_desc { /* SW state per Rx descriptor */
101 void *buf; /* struct page or mbuf */
105 struct sge_fl { /* SGE free-buffer queue state */
107 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
109 dma_addr_t addr; /* bus address of HW ring start */
110 __be64 *desc; /* address of HW Rx descriptor ring */
112 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
113 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
115 unsigned int cntxt_id; /* SGE relative QID for the free list */
116 unsigned int size; /* capacity of free list */
118 unsigned int avail; /* # of available Rx buffers */
119 unsigned int pend_cred; /* new buffers since last FL DB ring */
120 unsigned int cidx; /* consumer index */
121 unsigned int pidx; /* producer index */
123 unsigned long alloc_failed; /* # of times buffer allocation failed */
124 unsigned long low; /* # of times momentarily starving */
127 #define MAX_MBUF_FRAGS (16384 / 512 + 2)
129 /* A packet gather list */
132 struct rte_mbuf *mbufs[MAX_MBUF_FRAGS];
134 void *va; /* virtual address of first byte */
135 unsigned int nfrags; /* # of fragments */
136 unsigned int tot_len; /* total length of fragments */
137 bool usembufs; /* use mbufs for fragments */
140 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
141 const struct pkt_gl *gl);
143 struct sge_rspq { /* state for an SGE response queue */
144 struct adapter *adapter; /* adapter that this queue belongs to */
145 struct rte_eth_dev *eth_dev; /* associated rte eth device */
146 struct rte_mempool *mb_pool; /* associated mempool */
148 dma_addr_t phys_addr; /* physical address of the ring */
149 __be64 *desc; /* address of HW response ring */
150 const __be64 *cur_desc; /* current descriptor in queue */
152 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
153 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
154 struct sge_qstat *stat;
156 unsigned int cidx; /* consumer index */
157 unsigned int gts_idx; /* last gts write sent */
158 unsigned int iqe_len; /* entry size */
159 unsigned int size; /* capacity of response queue */
160 int offset; /* offset into current Rx buffer */
162 u8 gen; /* current generation bit */
163 u8 intr_params; /* interrupt holdoff parameters */
164 u8 next_intr_params; /* holdoff params for next interrupt */
165 u8 pktcnt_idx; /* interrupt packet threshold */
166 u8 port_id; /* associated port-id */
167 u8 idx; /* queue index within its group */
168 u16 cntxt_id; /* SGE relative QID for the response Q */
169 u16 abs_id; /* absolute SGE id for the response q */
171 rspq_handler_t handler; /* associated handler for this response q */
174 struct sge_eth_rx_stats { /* Ethernet rx queue statistics */
175 u64 pkts; /* # of ethernet packets */
176 u64 rx_bytes; /* # of ethernet bytes */
177 u64 rx_cso; /* # of Rx checksum offloads */
178 u64 vlan_ex; /* # of Rx VLAN extractions */
179 u64 rx_drops; /* # of packets dropped due to no mem */
182 struct sge_eth_rxq { /* a SW Ethernet Rx queue */
183 struct sge_rspq rspq;
185 struct sge_eth_rx_stats stats;
186 bool usembufs; /* one ingress packet per mbuf FL buffer */
187 } __rte_cache_aligned;
190 * Currently there are two types of coalesce WR. Type 0 needs 48 bytes per
191 * packet (if one sgl is present) and type 1 needs 32 bytes. This means
192 * that type 0 can fit a maximum of 10 packets per WR and type 1 can fit
193 * 15 packets. We need to keep track of the mbuf pointers in a coalesce WR
194 * to be able to free those mbufs when we get completions back from the FW.
195 * Allocating the maximum number of pointers in every tx desc is a waste
196 * of memory resources so we only store 2 pointers per tx desc which should
197 * be enough since a tx desc can only fit 2 packets in the best case
198 * scenario where a packet needs 32 bytes.
200 #define ETH_COALESCE_PKT_NUM 15
201 #define ETH_COALESCE_PKT_PER_DESC 2
203 struct tx_eth_coal_desc {
204 struct rte_mbuf *mbuf[ETH_COALESCE_PKT_PER_DESC];
205 struct ulptx_sgl *sgl[ETH_COALESCE_PKT_PER_DESC];
213 struct tx_sw_desc { /* SW state per Tx descriptor */
214 struct rte_mbuf *mbuf;
215 struct ulptx_sgl *sgl;
216 struct tx_eth_coal_desc coalesce;
220 EQ_STOPPED = (1 << 0),
223 struct eth_coalesce {
233 struct tx_desc *desc; /* address of HW Tx descriptor ring */
234 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
235 struct sge_qstat *stat; /* queue status entry */
236 struct eth_coalesce coalesce; /* coalesce info */
238 uint64_t phys_addr; /* physical address of the ring */
240 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
241 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
243 unsigned int cntxt_id; /* SGE relative QID for the Tx Q */
244 unsigned int in_use; /* # of in-use Tx descriptors */
245 unsigned int size; /* # of descriptors */
246 unsigned int cidx; /* SW consumer index */
247 unsigned int pidx; /* producer index */
248 unsigned int dbidx; /* last idx when db ring was done */
249 unsigned int equeidx; /* last sent credit request */
250 unsigned int last_pidx; /* last pidx recorded by tx monitor */
251 unsigned int last_coal_idx;/* last coal-idx recorded by tx monitor */
254 int db_disabled; /* doorbell state */
255 unsigned short db_pidx; /* doorbell producer index */
256 unsigned short db_pidx_inc; /* doorbell producer increment */
259 struct sge_eth_tx_stats { /* Ethernet tx queue statistics */
260 u64 pkts; /* # of ethernet packets */
261 u64 tx_bytes; /* # of ethernet bytes */
262 u64 tso; /* # of TSO requests */
263 u64 tx_cso; /* # of Tx checksum offloads */
264 u64 vlan_ins; /* # of Tx VLAN insertions */
265 u64 mapping_err; /* # of I/O MMU packet mapping errors */
266 u64 coal_wr; /* # of coalesced wr */
267 u64 coal_pkts; /* # of coalesced packets */
270 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
272 struct rte_eth_dev *eth_dev; /* port that this queue belongs to */
273 struct rte_eth_dev_data *data;
274 struct sge_eth_tx_stats stats; /* queue statistics */
275 rte_spinlock_t txq_lock;
277 unsigned int flags; /* flags for state of the queue */
278 } __rte_cache_aligned;
281 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
282 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
283 struct sge_rspq fw_evtq __rte_cache_aligned;
285 u16 max_ethqsets; /* # of available Ethernet queue sets */
286 u32 stat_len; /* length of status page at ring end */
287 u32 pktshift; /* padding between CPL & packet data */
289 /* response queue interrupt parameters */
290 u16 timer_val[SGE_NTIMERS];
291 u8 counter_val[SGE_NCOUNTERS];
293 u32 fl_align; /* response queue message alignment */
294 u32 fl_pg_order; /* large page allocation size */
295 u32 fl_starve_thres; /* Free List starvation threshold */
298 #define T4_OS_NEEDS_MBOX_LOCKING 1
301 * OS Lock/List primitives for those interfaces in the Common Code which
306 TAILQ_ENTRY(mbox_entry) next;
309 TAILQ_HEAD(mbox_list, mbox_entry);
312 struct rte_pci_device *pdev; /* associated rte pci device */
313 struct rte_eth_dev *eth_dev; /* first port's rte eth device */
314 struct adapter_params params; /* adapter parameters */
315 struct port_info *port[MAX_NPORTS];/* ports belonging to this adapter */
316 struct sge sge; /* associated SGE */
318 /* support for single-threading access to adapter mailbox registers */
319 struct mbox_list mbox_list;
320 rte_spinlock_t mbox_lock;
322 u8 *regs; /* pointer to registers region */
323 u8 *bar2; /* pointer to bar2 region */
324 unsigned long flags; /* adapter flags */
325 unsigned int mbox; /* associated mailbox */
326 unsigned int pf; /* associated physical function id */
328 unsigned int vpd_busy;
329 unsigned int vpd_flag;
331 int use_unpacked_mode; /* unpacked rx mode state */
335 * adap2pinfo - return the port_info of a port
337 * @idx: the port index
339 * Return the port_info structure for the port of the given index.
341 static inline struct port_info *adap2pinfo(const struct adapter *adap, int idx)
343 return adap->port[idx];
346 #define CXGBE_PCI_REG(reg) rte_read32(reg)
348 static inline uint64_t cxgbe_read_addr64(volatile void *addr)
350 uint64_t val = CXGBE_PCI_REG(addr);
351 uint64_t val2 = CXGBE_PCI_REG(((volatile uint8_t *)(addr) + 4));
353 val2 = (uint64_t)(val2 << 32);
358 static inline uint32_t cxgbe_read_addr(volatile void *addr)
360 return CXGBE_PCI_REG(addr);
363 #define CXGBE_PCI_REG_ADDR(adap, reg) \
364 ((volatile uint32_t *)((char *)(adap)->regs + (reg)))
366 #define CXGBE_READ_REG(adap, reg) \
367 cxgbe_read_addr(CXGBE_PCI_REG_ADDR((adap), (reg)))
369 #define CXGBE_READ_REG64(adap, reg) \
370 cxgbe_read_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)))
372 #define CXGBE_PCI_REG_WRITE(reg, value) rte_write32((value), (reg))
374 #define CXGBE_PCI_REG_WRITE_RELAXED(reg, value) \
375 rte_write32_relaxed((value), (reg))
377 #define CXGBE_WRITE_REG(adap, reg, value) \
378 CXGBE_PCI_REG_WRITE(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
380 #define CXGBE_WRITE_REG_RELAXED(adap, reg, value) \
381 CXGBE_PCI_REG_WRITE_RELAXED(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
383 static inline uint64_t cxgbe_write_addr64(volatile void *addr, uint64_t val)
385 CXGBE_PCI_REG_WRITE(addr, val);
386 CXGBE_PCI_REG_WRITE(((volatile uint8_t *)(addr) + 4), (val >> 32));
390 #define CXGBE_WRITE_REG64(adap, reg, value) \
391 cxgbe_write_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
394 * t4_read_reg - read a HW register
395 * @adapter: the adapter
396 * @reg_addr: the register address
398 * Returns the 32-bit value of the given HW register.
400 static inline u32 t4_read_reg(struct adapter *adapter, u32 reg_addr)
402 u32 val = CXGBE_READ_REG(adapter, reg_addr);
404 CXGBE_DEBUG_REG(adapter, "read register 0x%x value 0x%x\n", reg_addr,
410 * t4_write_reg - write a HW register with barrier
411 * @adapter: the adapter
412 * @reg_addr: the register address
413 * @val: the value to write
415 * Write a 32-bit value into the given HW register.
417 static inline void t4_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
419 CXGBE_DEBUG_REG(adapter, "setting register 0x%x to 0x%x\n", reg_addr,
421 CXGBE_WRITE_REG(adapter, reg_addr, val);
425 * t4_write_reg_relaxed - write a HW register with no barrier
426 * @adapter: the adapter
427 * @reg_addr: the register address
428 * @val: the value to write
430 * Write a 32-bit value into the given HW register.
432 static inline void t4_write_reg_relaxed(struct adapter *adapter, u32 reg_addr,
435 CXGBE_DEBUG_REG(adapter, "setting register 0x%x to 0x%x\n", reg_addr,
437 CXGBE_WRITE_REG_RELAXED(adapter, reg_addr, val);
441 * t4_read_reg64 - read a 64-bit HW register
442 * @adapter: the adapter
443 * @reg_addr: the register address
445 * Returns the 64-bit value of the given HW register.
447 static inline u64 t4_read_reg64(struct adapter *adapter, u32 reg_addr)
449 u64 val = CXGBE_READ_REG64(adapter, reg_addr);
451 CXGBE_DEBUG_REG(adapter, "64-bit read register %#x value %#llx\n",
452 reg_addr, (unsigned long long)val);
457 * t4_write_reg64 - write a 64-bit HW register
458 * @adapter: the adapter
459 * @reg_addr: the register address
460 * @val: the value to write
462 * Write a 64-bit value into the given HW register.
464 static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr,
467 CXGBE_DEBUG_REG(adapter, "setting register %#x to %#llx\n", reg_addr,
468 (unsigned long long)val);
470 CXGBE_WRITE_REG64(adapter, reg_addr, val);
473 #define PCI_STATUS 0x06 /* 16 bits */
474 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
475 #define PCI_CAPABILITY_LIST 0x34
476 /* Offset of first capability list entry */
477 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
478 #define PCI_CAP_LIST_ID 0 /* Capability ID */
479 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
480 #define PCI_EXP_DEVCTL 0x0008 /* Device control */
481 #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
482 #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
483 #define PCI_EXP_DEVCTL_PAYLOAD 0x00E0 /* Max payload */
484 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
485 #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
486 #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
487 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */
490 * t4_os_pci_write_cfg4 - 32-bit write to PCI config space
491 * @adapter: the adapter
492 * @addr: the register address
493 * @val: the value to write
495 * Write a 32-bit value into the given register in PCI config space.
497 static inline void t4_os_pci_write_cfg4(struct adapter *adapter, size_t addr,
502 if (rte_pci_write_config(adapter->pdev, &val32, sizeof(val32),
504 dev_err(adapter, "Can't write to PCI config space\n");
508 * t4_os_pci_read_cfg4 - read a 32-bit value from PCI config space
509 * @adapter: the adapter
510 * @addr: the register address
511 * @val: where to store the value read
513 * Read a 32-bit value from the given register in PCI config space.
515 static inline void t4_os_pci_read_cfg4(struct adapter *adapter, size_t addr,
518 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
520 dev_err(adapter, "Can't read from PCI config space\n");
524 * t4_os_pci_write_cfg2 - 16-bit write to PCI config space
525 * @adapter: the adapter
526 * @addr: the register address
527 * @val: the value to write
529 * Write a 16-bit value into the given register in PCI config space.
531 static inline void t4_os_pci_write_cfg2(struct adapter *adapter, size_t addr,
536 if (rte_pci_write_config(adapter->pdev, &val16, sizeof(val16),
538 dev_err(adapter, "Can't write to PCI config space\n");
542 * t4_os_pci_read_cfg2 - read a 16-bit value from PCI config space
543 * @adapter: the adapter
544 * @addr: the register address
545 * @val: where to store the value read
547 * Read a 16-bit value from the given register in PCI config space.
549 static inline void t4_os_pci_read_cfg2(struct adapter *adapter, size_t addr,
552 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
554 dev_err(adapter, "Can't read from PCI config space\n");
558 * t4_os_pci_read_cfg - read a 8-bit value from PCI config space
559 * @adapter: the adapter
560 * @addr: the register address
561 * @val: where to store the value read
563 * Read a 8-bit value from the given register in PCI config space.
565 static inline void t4_os_pci_read_cfg(struct adapter *adapter, size_t addr,
568 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
570 dev_err(adapter, "Can't read from PCI config space\n");
574 * t4_os_find_pci_capability - lookup a capability in the PCI capability list
575 * @adapter: the adapter
576 * @cap: the capability
578 * Return the address of the given capability within the PCI capability list.
580 static inline int t4_os_find_pci_capability(struct adapter *adapter, int cap)
587 t4_os_pci_read_cfg2(adapter, PCI_STATUS, &status);
588 if (!(status & PCI_STATUS_CAP_LIST)) {
589 dev_err(adapter, "PCIe capability reading failed\n");
593 t4_os_pci_read_cfg(adapter, PCI_CAPABILITY_LIST, &pos);
594 while (ttl-- && pos >= 0x40) {
596 t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_ID), &id);
604 t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_NEXT), &pos);
610 * t4_os_set_hw_addr - store a port's MAC address in SW
611 * @adapter: the adapter
612 * @port_idx: the port index
613 * @hw_addr: the Ethernet address
615 * Store the Ethernet address of the given port in SW. Called by the
616 * common code when it retrieves a port's Ethernet address from EEPROM.
618 static inline void t4_os_set_hw_addr(struct adapter *adapter, int port_idx,
621 struct port_info *pi = adap2pinfo(adapter, port_idx);
623 ether_addr_copy((struct ether_addr *)hw_addr,
624 &pi->eth_dev->data->mac_addrs[0]);
628 * t4_os_lock_init - initialize spinlock
629 * @lock: the spinlock
631 static inline void t4_os_lock_init(rte_spinlock_t *lock)
633 rte_spinlock_init(lock);
637 * t4_os_lock - spin until lock is acquired
638 * @lock: the spinlock
640 static inline void t4_os_lock(rte_spinlock_t *lock)
642 rte_spinlock_lock(lock);
646 * t4_os_unlock - unlock a spinlock
647 * @lock: the spinlock
649 static inline void t4_os_unlock(rte_spinlock_t *lock)
651 rte_spinlock_unlock(lock);
655 * t4_os_trylock - try to get a lock
656 * @lock: the spinlock
658 static inline int t4_os_trylock(rte_spinlock_t *lock)
660 return rte_spinlock_trylock(lock);
664 * t4_os_init_list_head - initialize
665 * @head: head of list to initialize [to empty]
667 static inline void t4_os_init_list_head(struct mbox_list *head)
672 static inline struct mbox_entry *t4_os_list_first_entry(struct mbox_list *head)
674 return TAILQ_FIRST(head);
678 * t4_os_atomic_add_tail - Enqueue list element atomically onto list
679 * @new: the entry to be addded to the queue
680 * @head: current head of the linked list
681 * @lock: lock to use to guarantee atomicity
683 static inline void t4_os_atomic_add_tail(struct mbox_entry *entry,
684 struct mbox_list *head,
685 rte_spinlock_t *lock)
688 TAILQ_INSERT_TAIL(head, entry, next);
693 * t4_os_atomic_list_del - Dequeue list element atomically from list
694 * @entry: the entry to be remove/dequeued from the list.
695 * @lock: the spinlock
697 static inline void t4_os_atomic_list_del(struct mbox_entry *entry,
698 struct mbox_list *head,
699 rte_spinlock_t *lock)
702 TAILQ_REMOVE(head, entry, next);
706 void *t4_alloc_mem(size_t size);
707 void t4_free_mem(void *addr);
708 #define t4_os_alloc(_size) t4_alloc_mem((_size))
709 #define t4_os_free(_ptr) t4_free_mem((_ptr))
711 void t4_os_portmod_changed(const struct adapter *adap, int port_id);
712 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
714 void reclaim_completed_tx(struct sge_txq *q);
715 void t4_free_sge_resources(struct adapter *adap);
716 void t4_sge_tx_monitor_start(struct adapter *adap);
717 void t4_sge_tx_monitor_stop(struct adapter *adap);
718 int t4_eth_xmit(struct sge_eth_txq *txq, struct rte_mbuf *mbuf,
720 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
721 const struct pkt_gl *gl);
722 int t4_sge_init(struct adapter *adap);
723 int t4vf_sge_init(struct adapter *adap);
724 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
725 struct rte_eth_dev *eth_dev, uint16_t queue_id,
726 unsigned int iqid, int socket_id);
727 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *rspq, bool fwevtq,
728 struct rte_eth_dev *eth_dev, int intr_idx,
729 struct sge_fl *fl, rspq_handler_t handler,
730 int cong, struct rte_mempool *mp, int queue_id,
732 int t4_sge_eth_txq_start(struct sge_eth_txq *txq);
733 int t4_sge_eth_txq_stop(struct sge_eth_txq *txq);
734 void t4_sge_eth_txq_release(struct adapter *adap, struct sge_eth_txq *txq);
735 int t4_sge_eth_rxq_start(struct adapter *adap, struct sge_rspq *rq);
736 int t4_sge_eth_rxq_stop(struct adapter *adap, struct sge_rspq *rq);
737 void t4_sge_eth_rxq_release(struct adapter *adap, struct sge_eth_rxq *rxq);
738 void t4_sge_eth_clear_queues(struct port_info *pi);
739 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
741 int cxgbe_poll(struct sge_rspq *q, struct rte_mbuf **rx_pkts,
742 unsigned int budget, unsigned int *work_done);
743 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues);
744 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t flags);
746 #endif /* __T4_ADAPTER_H__ */