1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
6 /* This file should not be included directly. Include common.h instead. */
8 #ifndef __T4_ADAPTER_H__
9 #define __T4_ADAPTER_H__
11 #include <rte_bus_pci.h>
14 #include <rte_rwlock.h>
15 #include <rte_ethdev.h>
17 #include "../cxgbe_compat.h"
18 #include "../cxgbe_ofld.h"
19 #include "t4_regs_values.h"
22 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
29 PORT_RSS_DONE = (1 << 0),
33 struct adapter *adapter; /* adapter that this port belongs to */
34 struct rte_eth_dev *eth_dev; /* associated rte eth device */
35 struct port_stats stats_base; /* port statistics base */
36 struct link_config link_cfg; /* link configuration info */
38 unsigned long flags; /* port related flags */
39 short int xact_addr_filt; /* index of exact MAC address filter */
41 u16 viid; /* associated virtual interface id */
42 u8 port_id; /* physical port ID */
43 u8 pidx; /* port index for this PF */
44 u8 tx_chan; /* associated channel */
46 u16 n_rx_qsets; /* # of rx qsets */
47 u16 n_tx_qsets; /* # of tx qsets */
48 u16 first_rxqset; /* index of first rxqset */
49 u16 first_txqset; /* index of first txqset */
51 u16 *rss; /* rss table */
52 u8 rss_mode; /* rss mode */
53 u16 rss_size; /* size of VI's RSS table slice */
54 u64 rss_hf; /* RSS Hash Function */
56 /* viid fields either returned by fw
57 * or decoded by parsing viid by driver.
63 enum { /* adapter flags */
64 FULL_INIT_DONE = (1 << 0),
66 USING_MSIX = (1 << 2),
67 FW_QUEUE_BOUND = (1 << 3),
69 CFG_QUEUES = (1 << 5),
73 struct rx_sw_desc { /* SW state per Rx descriptor */
74 void *buf; /* struct page or mbuf */
78 struct sge_fl { /* SGE free-buffer queue state */
80 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
82 dma_addr_t addr; /* bus address of HW ring start */
83 __be64 *desc; /* address of HW Rx descriptor ring */
85 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
86 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
88 unsigned int cntxt_id; /* SGE relative QID for the free list */
89 unsigned int size; /* capacity of free list */
91 unsigned int avail; /* # of available Rx buffers */
92 unsigned int pend_cred; /* new buffers since last FL DB ring */
93 unsigned int cidx; /* consumer index */
94 unsigned int pidx; /* producer index */
96 unsigned long alloc_failed; /* # of times buffer allocation failed */
97 unsigned long low; /* # of times momentarily starving */
100 #define MAX_MBUF_FRAGS (16384 / 512 + 2)
102 /* A packet gather list */
105 struct rte_mbuf *mbufs[MAX_MBUF_FRAGS];
107 void *va; /* virtual address of first byte */
108 unsigned int nfrags; /* # of fragments */
109 unsigned int tot_len; /* total length of fragments */
110 bool usembufs; /* use mbufs for fragments */
113 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
114 const struct pkt_gl *gl);
116 struct sge_rspq { /* state for an SGE response queue */
117 struct adapter *adapter; /* adapter that this queue belongs to */
118 struct rte_eth_dev *eth_dev; /* associated rte eth device */
119 struct rte_mempool *mb_pool; /* associated mempool */
121 dma_addr_t phys_addr; /* physical address of the ring */
122 __be64 *desc; /* address of HW response ring */
123 const __be64 *cur_desc; /* current descriptor in queue */
125 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
126 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
127 struct sge_qstat *stat;
129 unsigned int cidx; /* consumer index */
130 unsigned int gts_idx; /* last gts write sent */
131 unsigned int iqe_len; /* entry size */
132 unsigned int size; /* capacity of response queue */
133 int offset; /* offset into current Rx buffer */
135 u8 gen; /* current generation bit */
136 u8 intr_params; /* interrupt holdoff parameters */
137 u8 next_intr_params; /* holdoff params for next interrupt */
138 u8 pktcnt_idx; /* interrupt packet threshold */
139 u8 port_id; /* associated port-id */
140 u8 idx; /* queue index within its group */
141 u16 cntxt_id; /* SGE relative QID for the response Q */
142 u16 abs_id; /* absolute SGE id for the response q */
144 rspq_handler_t handler; /* associated handler for this response q */
147 struct sge_eth_rx_stats { /* Ethernet rx queue statistics */
148 u64 pkts; /* # of ethernet packets */
149 u64 rx_bytes; /* # of ethernet bytes */
150 u64 rx_cso; /* # of Rx checksum offloads */
151 u64 vlan_ex; /* # of Rx VLAN extractions */
152 u64 rx_drops; /* # of packets dropped due to no mem */
155 struct sge_eth_rxq { /* a SW Ethernet Rx queue */
156 unsigned int flags; /* flags for state of the queue */
157 struct sge_rspq rspq;
159 struct sge_eth_rx_stats stats;
160 bool usembufs; /* one ingress packet per mbuf FL buffer */
161 } __rte_cache_aligned;
164 * Currently there are two types of coalesce WR. Type 0 needs 48 bytes per
165 * packet (if one sgl is present) and type 1 needs 32 bytes. This means
166 * that type 0 can fit a maximum of 10 packets per WR and type 1 can fit
167 * 15 packets. We need to keep track of the mbuf pointers in a coalesce WR
168 * to be able to free those mbufs when we get completions back from the FW.
169 * Allocating the maximum number of pointers in every tx desc is a waste
170 * of memory resources so we only store 2 pointers per tx desc which should
171 * be enough since a tx desc can only fit 2 packets in the best case
172 * scenario where a packet needs 32 bytes.
174 #define ETH_COALESCE_PKT_NUM 15
175 #define ETH_COALESCE_VF_PKT_NUM 7
176 #define ETH_COALESCE_PKT_PER_DESC 2
178 struct tx_eth_coal_desc {
179 struct rte_mbuf *mbuf[ETH_COALESCE_PKT_PER_DESC];
180 struct ulptx_sgl *sgl[ETH_COALESCE_PKT_PER_DESC];
188 struct tx_sw_desc { /* SW state per Tx descriptor */
189 struct rte_mbuf *mbuf;
190 struct ulptx_sgl *sgl;
191 struct tx_eth_coal_desc coalesce;
194 enum cxgbe_txq_state {
195 EQ_STOPPED = (1 << 0),
198 enum cxgbe_rxq_state {
199 IQ_STOPPED = (1 << 0),
202 struct eth_coalesce {
209 __u8 ethmacdst[ETHER_ADDR_LEN];
210 __u8 ethmacsrc[ETHER_ADDR_LEN];
216 struct tx_desc *desc; /* address of HW Tx descriptor ring */
217 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
218 struct sge_qstat *stat; /* queue status entry */
219 struct eth_coalesce coalesce; /* coalesce info */
221 uint64_t phys_addr; /* physical address of the ring */
223 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
224 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
226 unsigned int cntxt_id; /* SGE relative QID for the Tx Q */
227 unsigned int in_use; /* # of in-use Tx descriptors */
228 unsigned int size; /* # of descriptors */
229 unsigned int cidx; /* SW consumer index */
230 unsigned int pidx; /* producer index */
231 unsigned int dbidx; /* last idx when db ring was done */
232 unsigned int equeidx; /* last sent credit request */
233 unsigned int last_pidx; /* last pidx recorded by tx monitor */
234 unsigned int last_coal_idx;/* last coal-idx recorded by tx monitor */
237 int db_disabled; /* doorbell state */
238 unsigned short db_pidx; /* doorbell producer index */
239 unsigned short db_pidx_inc; /* doorbell producer increment */
242 struct sge_eth_tx_stats { /* Ethernet tx queue statistics */
243 u64 pkts; /* # of ethernet packets */
244 u64 tx_bytes; /* # of ethernet bytes */
245 u64 tso; /* # of TSO requests */
246 u64 tx_cso; /* # of Tx checksum offloads */
247 u64 vlan_ins; /* # of Tx VLAN insertions */
248 u64 mapping_err; /* # of I/O MMU packet mapping errors */
249 u64 coal_wr; /* # of coalesced wr */
250 u64 coal_pkts; /* # of coalesced packets */
253 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
255 struct rte_eth_dev *eth_dev; /* port that this queue belongs to */
256 struct rte_eth_dev_data *data;
257 struct sge_eth_tx_stats stats; /* queue statistics */
258 rte_spinlock_t txq_lock;
260 unsigned int flags; /* flags for state of the queue */
261 } __rte_cache_aligned;
263 struct sge_ctrl_txq { /* State for an SGE control Tx queue */
264 struct sge_txq q; /* txq */
265 struct adapter *adapter; /* adapter associated with this queue */
266 rte_spinlock_t ctrlq_lock; /* control queue lock */
267 u8 full; /* the Tx ring is full */
268 u64 txp; /* number of transmits */
269 struct rte_mempool *mb_pool; /* mempool to generate ctrl pkts */
270 } __rte_cache_aligned;
273 struct sge_eth_txq *ethtxq;
274 struct sge_eth_rxq *ethrxq;
275 struct sge_rspq fw_evtq __rte_cache_aligned;
276 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
278 u16 max_ethqsets; /* # of available Ethernet queue sets */
279 u32 stat_len; /* length of status page at ring end */
280 u32 pktshift; /* padding between CPL & packet data */
282 /* response queue interrupt parameters */
283 u16 timer_val[SGE_NTIMERS];
284 u8 counter_val[SGE_NCOUNTERS];
286 u32 fl_align; /* response queue message alignment */
287 u32 fl_pg_order; /* large page allocation size */
288 u32 fl_starve_thres; /* Free List starvation threshold */
291 #define T4_OS_NEEDS_MBOX_LOCKING 1
294 * OS Lock/List primitives for those interfaces in the Common Code which
299 TAILQ_ENTRY(mbox_entry) next;
302 TAILQ_HEAD(mbox_list, mbox_entry);
304 struct adapter_devargs {
307 bool tx_mode_latency;
313 struct rte_pci_device *pdev; /* associated rte pci device */
314 struct rte_eth_dev *eth_dev; /* first port's rte eth device */
315 struct adapter_params params; /* adapter parameters */
316 struct port_info *port[MAX_NPORTS];/* ports belonging to this adapter */
317 struct sge sge; /* associated SGE */
319 /* support for single-threading access to adapter mailbox registers */
320 struct mbox_list mbox_list;
321 rte_spinlock_t mbox_lock;
323 u8 *regs; /* pointer to registers region */
324 u8 *bar2; /* pointer to bar2 region */
325 unsigned long flags; /* adapter flags */
326 unsigned int mbox; /* associated mailbox */
327 unsigned int pf; /* associated physical function id */
329 unsigned int vpd_busy;
330 unsigned int vpd_flag;
332 int use_unpacked_mode; /* unpacked rx mode state */
333 rte_spinlock_t win0_lock;
335 rte_spinlock_t flow_lock; /* Serialize access for rte_flow ops */
337 unsigned int clipt_start; /* CLIP table start */
338 unsigned int clipt_end; /* CLIP table end */
339 unsigned int l2t_start; /* Layer 2 table start */
340 unsigned int l2t_end; /* Layer 2 table end */
341 struct clip_tbl *clipt; /* CLIP table */
342 struct l2t_data *l2t; /* Layer 2 table */
343 struct smt_data *smt; /* Source mac table */
344 struct mpstcam_table *mpstcam;
346 struct tid_info tids; /* Info used to access TID related tables */
348 struct adapter_devargs devargs;
352 * t4_os_rwlock_init - initialize rwlock
355 static inline void t4_os_rwlock_init(rte_rwlock_t *lock)
357 rte_rwlock_init(lock);
361 * t4_os_write_lock - get a write lock
364 static inline void t4_os_write_lock(rte_rwlock_t *lock)
366 rte_rwlock_write_lock(lock);
370 * t4_os_write_unlock - unlock a write lock
373 static inline void t4_os_write_unlock(rte_rwlock_t *lock)
375 rte_rwlock_write_unlock(lock);
379 * ethdev2pinfo - return the port_info structure associated with a rte_eth_dev
380 * @dev: the rte_eth_dev
382 * Return the struct port_info associated with a rte_eth_dev
384 static inline struct port_info *ethdev2pinfo(const struct rte_eth_dev *dev)
386 return dev->data->dev_private;
390 * adap2pinfo - return the port_info of a port
392 * @idx: the port index
394 * Return the port_info structure for the port of the given index.
396 static inline struct port_info *adap2pinfo(const struct adapter *adap, int idx)
398 return adap->port[idx];
402 * ethdev2adap - return the adapter structure associated with a rte_eth_dev
403 * @dev: the rte_eth_dev
405 * Return the struct adapter associated with a rte_eth_dev
407 static inline struct adapter *ethdev2adap(const struct rte_eth_dev *dev)
409 return ethdev2pinfo(dev)->adapter;
412 #define CXGBE_PCI_REG(reg) rte_read32(reg)
414 static inline uint64_t cxgbe_read_addr64(volatile void *addr)
416 uint64_t val = CXGBE_PCI_REG(addr);
417 uint64_t val2 = CXGBE_PCI_REG(((volatile uint8_t *)(addr) + 4));
419 val2 = (uint64_t)(val2 << 32);
424 static inline uint32_t cxgbe_read_addr(volatile void *addr)
426 return CXGBE_PCI_REG(addr);
429 #define CXGBE_PCI_REG_ADDR(adap, reg) \
430 ((volatile uint32_t *)((char *)(adap)->regs + (reg)))
432 #define CXGBE_READ_REG(adap, reg) \
433 cxgbe_read_addr(CXGBE_PCI_REG_ADDR((adap), (reg)))
435 #define CXGBE_READ_REG64(adap, reg) \
436 cxgbe_read_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)))
438 #define CXGBE_PCI_REG_WRITE(reg, value) rte_write32((value), (reg))
440 #define CXGBE_PCI_REG_WRITE_RELAXED(reg, value) \
441 rte_write32_relaxed((value), (reg))
443 #define CXGBE_WRITE_REG(adap, reg, value) \
444 CXGBE_PCI_REG_WRITE(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
446 #define CXGBE_WRITE_REG_RELAXED(adap, reg, value) \
447 CXGBE_PCI_REG_WRITE_RELAXED(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
449 static inline uint64_t cxgbe_write_addr64(volatile void *addr, uint64_t val)
451 CXGBE_PCI_REG_WRITE(addr, val);
452 CXGBE_PCI_REG_WRITE(((volatile uint8_t *)(addr) + 4), (val >> 32));
456 #define CXGBE_WRITE_REG64(adap, reg, value) \
457 cxgbe_write_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
460 * t4_read_reg - read a HW register
461 * @adapter: the adapter
462 * @reg_addr: the register address
464 * Returns the 32-bit value of the given HW register.
466 static inline u32 t4_read_reg(struct adapter *adapter, u32 reg_addr)
468 return CXGBE_READ_REG(adapter, reg_addr);
472 * t4_write_reg - write a HW register with barrier
473 * @adapter: the adapter
474 * @reg_addr: the register address
475 * @val: the value to write
477 * Write a 32-bit value into the given HW register.
479 static inline void t4_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
481 CXGBE_WRITE_REG(adapter, reg_addr, val);
485 * t4_write_reg_relaxed - write a HW register with no barrier
486 * @adapter: the adapter
487 * @reg_addr: the register address
488 * @val: the value to write
490 * Write a 32-bit value into the given HW register.
492 static inline void t4_write_reg_relaxed(struct adapter *adapter, u32 reg_addr,
495 CXGBE_WRITE_REG_RELAXED(adapter, reg_addr, val);
499 * t4_read_reg64 - read a 64-bit HW register
500 * @adapter: the adapter
501 * @reg_addr: the register address
503 * Returns the 64-bit value of the given HW register.
505 static inline u64 t4_read_reg64(struct adapter *adapter, u32 reg_addr)
507 return CXGBE_READ_REG64(adapter, reg_addr);
511 * t4_write_reg64 - write a 64-bit HW register
512 * @adapter: the adapter
513 * @reg_addr: the register address
514 * @val: the value to write
516 * Write a 64-bit value into the given HW register.
518 static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr,
521 CXGBE_WRITE_REG64(adapter, reg_addr, val);
524 #define PCI_STATUS 0x06 /* 16 bits */
525 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
526 #define PCI_CAPABILITY_LIST 0x34
527 /* Offset of first capability list entry */
528 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
529 #define PCI_CAP_LIST_ID 0 /* Capability ID */
530 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
531 #define PCI_EXP_DEVCTL 0x0008 /* Device control */
532 #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
533 #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
534 #define PCI_EXP_DEVCTL_PAYLOAD 0x00E0 /* Max payload */
535 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
536 #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
537 #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
538 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */
541 * t4_os_pci_write_cfg4 - 32-bit write to PCI config space
542 * @adapter: the adapter
543 * @addr: the register address
544 * @val: the value to write
546 * Write a 32-bit value into the given register in PCI config space.
548 static inline void t4_os_pci_write_cfg4(struct adapter *adapter, size_t addr,
553 if (rte_pci_write_config(adapter->pdev, &val32, sizeof(val32),
555 dev_err(adapter, "Can't write to PCI config space\n");
559 * t4_os_pci_read_cfg4 - read a 32-bit value from PCI config space
560 * @adapter: the adapter
561 * @addr: the register address
562 * @val: where to store the value read
564 * Read a 32-bit value from the given register in PCI config space.
566 static inline void t4_os_pci_read_cfg4(struct adapter *adapter, size_t addr,
569 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
571 dev_err(adapter, "Can't read from PCI config space\n");
575 * t4_os_pci_write_cfg2 - 16-bit write to PCI config space
576 * @adapter: the adapter
577 * @addr: the register address
578 * @val: the value to write
580 * Write a 16-bit value into the given register in PCI config space.
582 static inline void t4_os_pci_write_cfg2(struct adapter *adapter, size_t addr,
587 if (rte_pci_write_config(adapter->pdev, &val16, sizeof(val16),
589 dev_err(adapter, "Can't write to PCI config space\n");
593 * t4_os_pci_read_cfg2 - read a 16-bit value from PCI config space
594 * @adapter: the adapter
595 * @addr: the register address
596 * @val: where to store the value read
598 * Read a 16-bit value from the given register in PCI config space.
600 static inline void t4_os_pci_read_cfg2(struct adapter *adapter, size_t addr,
603 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
605 dev_err(adapter, "Can't read from PCI config space\n");
609 * t4_os_pci_read_cfg - read a 8-bit value from PCI config space
610 * @adapter: the adapter
611 * @addr: the register address
612 * @val: where to store the value read
614 * Read a 8-bit value from the given register in PCI config space.
616 static inline void t4_os_pci_read_cfg(struct adapter *adapter, size_t addr,
619 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
621 dev_err(adapter, "Can't read from PCI config space\n");
625 * t4_os_find_pci_capability - lookup a capability in the PCI capability list
626 * @adapter: the adapter
627 * @cap: the capability
629 * Return the address of the given capability within the PCI capability list.
631 static inline int t4_os_find_pci_capability(struct adapter *adapter, int cap)
638 t4_os_pci_read_cfg2(adapter, PCI_STATUS, &status);
639 if (!(status & PCI_STATUS_CAP_LIST)) {
640 dev_err(adapter, "PCIe capability reading failed\n");
644 t4_os_pci_read_cfg(adapter, PCI_CAPABILITY_LIST, &pos);
645 while (ttl-- && pos >= 0x40) {
647 t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_ID), &id);
655 t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_NEXT), &pos);
661 * t4_os_set_hw_addr - store a port's MAC address in SW
662 * @adapter: the adapter
663 * @port_idx: the port index
664 * @hw_addr: the Ethernet address
666 * Store the Ethernet address of the given port in SW. Called by the
667 * common code when it retrieves a port's Ethernet address from EEPROM.
669 static inline void t4_os_set_hw_addr(struct adapter *adapter, int port_idx,
672 struct port_info *pi = adap2pinfo(adapter, port_idx);
674 rte_ether_addr_copy((struct rte_ether_addr *)hw_addr,
675 &pi->eth_dev->data->mac_addrs[0]);
679 * t4_os_lock_init - initialize spinlock
680 * @lock: the spinlock
682 static inline void t4_os_lock_init(rte_spinlock_t *lock)
684 rte_spinlock_init(lock);
688 * t4_os_lock - spin until lock is acquired
689 * @lock: the spinlock
691 static inline void t4_os_lock(rte_spinlock_t *lock)
693 rte_spinlock_lock(lock);
697 * t4_os_unlock - unlock a spinlock
698 * @lock: the spinlock
700 static inline void t4_os_unlock(rte_spinlock_t *lock)
702 rte_spinlock_unlock(lock);
706 * t4_os_trylock - try to get a lock
707 * @lock: the spinlock
709 static inline int t4_os_trylock(rte_spinlock_t *lock)
711 return rte_spinlock_trylock(lock);
715 * t4_os_init_list_head - initialize
716 * @head: head of list to initialize [to empty]
718 static inline void t4_os_init_list_head(struct mbox_list *head)
723 static inline struct mbox_entry *t4_os_list_first_entry(struct mbox_list *head)
725 return TAILQ_FIRST(head);
729 * t4_os_atomic_add_tail - Enqueue list element atomically onto list
730 * @new: the entry to be addded to the queue
731 * @head: current head of the linked list
732 * @lock: lock to use to guarantee atomicity
734 static inline void t4_os_atomic_add_tail(struct mbox_entry *entry,
735 struct mbox_list *head,
736 rte_spinlock_t *lock)
739 TAILQ_INSERT_TAIL(head, entry, next);
744 * t4_os_atomic_list_del - Dequeue list element atomically from list
745 * @entry: the entry to be remove/dequeued from the list.
746 * @lock: the spinlock
748 static inline void t4_os_atomic_list_del(struct mbox_entry *entry,
749 struct mbox_list *head,
750 rte_spinlock_t *lock)
753 TAILQ_REMOVE(head, entry, next);
758 * t4_init_completion - initialize completion
759 * @c: the completion context
761 static inline void t4_init_completion(struct t4_completion *c)
764 t4_os_lock_init(&c->lock);
768 * t4_complete - set completion as done
769 * @c: the completion context
771 static inline void t4_complete(struct t4_completion *c)
773 t4_os_lock(&c->lock);
775 t4_os_unlock(&c->lock);
779 * cxgbe_port_viid - get the VI id of a port
780 * @dev: the device for the port
782 * Return the VI id of the given port.
784 static inline unsigned int cxgbe_port_viid(const struct rte_eth_dev *dev)
786 return ethdev2pinfo(dev)->viid;
789 void *t4_alloc_mem(size_t size);
790 void t4_free_mem(void *addr);
791 #define t4_os_alloc(_size) t4_alloc_mem((_size))
792 #define t4_os_free(_ptr) t4_free_mem((_ptr))
794 void t4_os_portmod_changed(const struct adapter *adap, int port_id);
796 void reclaim_completed_tx(struct sge_txq *q);
797 void t4_free_sge_resources(struct adapter *adap);
798 void t4_sge_tx_monitor_start(struct adapter *adap);
799 void t4_sge_tx_monitor_stop(struct adapter *adap);
800 int t4_eth_xmit(struct sge_eth_txq *txq, struct rte_mbuf *mbuf,
802 int t4_mgmt_tx(struct sge_ctrl_txq *txq, struct rte_mbuf *mbuf);
803 int t4_sge_init(struct adapter *adap);
804 int t4vf_sge_init(struct adapter *adap);
805 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
806 struct rte_eth_dev *eth_dev, uint16_t queue_id,
807 unsigned int iqid, int socket_id);
808 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
809 struct rte_eth_dev *eth_dev, uint16_t queue_id,
810 unsigned int iqid, int socket_id);
811 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *rspq, bool fwevtq,
812 struct rte_eth_dev *eth_dev, int intr_idx,
813 struct sge_fl *fl, rspq_handler_t handler,
814 int cong, struct rte_mempool *mp, int queue_id,
816 int t4_sge_eth_txq_start(struct sge_eth_txq *txq);
817 int t4_sge_eth_txq_stop(struct sge_eth_txq *txq);
818 void t4_sge_eth_txq_release(struct adapter *adap, struct sge_eth_txq *txq);
819 int t4_sge_eth_rxq_start(struct adapter *adap, struct sge_eth_rxq *rxq);
820 int t4_sge_eth_rxq_stop(struct adapter *adap, struct sge_eth_rxq *rxq);
821 void t4_sge_eth_rxq_release(struct adapter *adap, struct sge_eth_rxq *rxq);
822 void t4_sge_eth_clear_queues(struct port_info *pi);
823 void t4_sge_eth_release_queues(struct port_info *pi);
824 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
826 int cxgbe_poll(struct sge_rspq *q, struct rte_mbuf **rx_pkts,
827 unsigned int budget, unsigned int *work_done);
828 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues);
829 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t flags);
831 #endif /* __T4_ADAPTER_H__ */