1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
6 /* This file should not be included directly. Include common.h instead. */
8 #ifndef __T4_ADAPTER_H__
9 #define __T4_ADAPTER_H__
11 #include <rte_bus_pci.h>
14 #include <rte_rwlock.h>
15 #include <rte_ethdev.h>
17 #include "../cxgbe_compat.h"
18 #include "../cxgbe_ofld.h"
19 #include "t4_regs_values.h"
22 MAX_ETH_QSETS = 64, /* # of Ethernet Tx/Rx queue sets */
23 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
30 PORT_RSS_DONE = (1 << 0),
34 struct adapter *adapter; /* adapter that this port belongs to */
35 struct rte_eth_dev *eth_dev; /* associated rte eth device */
36 struct port_stats stats_base; /* port statistics base */
37 struct link_config link_cfg; /* link configuration info */
39 unsigned long flags; /* port related flags */
40 short int xact_addr_filt; /* index of exact MAC address filter */
42 u16 viid; /* associated virtual interface id */
43 s8 mdio_addr; /* address of the PHY */
44 u8 port_type; /* firmware port type */
45 u8 mod_type; /* firmware module type */
46 u8 port_id; /* physical port ID */
47 u8 pidx; /* port index for this PF */
48 u8 tx_chan; /* associated channel */
50 u8 n_rx_qsets; /* # of rx qsets */
51 u8 n_tx_qsets; /* # of tx qsets */
52 u8 first_qset; /* index of first qset */
54 u16 *rss; /* rss table */
55 u8 rss_mode; /* rss mode */
56 u16 rss_size; /* size of VI's RSS table slice */
57 u64 rss_hf; /* RSS Hash Function */
59 /* viid fields either returned by fw
60 * or decoded by parsing viid by driver.
66 /* Enable or disable autonegotiation. If this is set to enable,
67 * the forced link modes above are completely ignored.
69 #define AUTONEG_DISABLE 0x00
70 #define AUTONEG_ENABLE 0x01
72 enum { /* adapter flags */
73 FULL_INIT_DONE = (1 << 0),
75 USING_MSIX = (1 << 2),
76 FW_QUEUE_BOUND = (1 << 3),
78 CFG_QUEUES = (1 << 5),
82 struct rx_sw_desc { /* SW state per Rx descriptor */
83 void *buf; /* struct page or mbuf */
87 struct sge_fl { /* SGE free-buffer queue state */
89 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
91 dma_addr_t addr; /* bus address of HW ring start */
92 __be64 *desc; /* address of HW Rx descriptor ring */
94 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
95 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
97 unsigned int cntxt_id; /* SGE relative QID for the free list */
98 unsigned int size; /* capacity of free list */
100 unsigned int avail; /* # of available Rx buffers */
101 unsigned int pend_cred; /* new buffers since last FL DB ring */
102 unsigned int cidx; /* consumer index */
103 unsigned int pidx; /* producer index */
105 unsigned long alloc_failed; /* # of times buffer allocation failed */
106 unsigned long low; /* # of times momentarily starving */
109 #define MAX_MBUF_FRAGS (16384 / 512 + 2)
111 /* A packet gather list */
114 struct rte_mbuf *mbufs[MAX_MBUF_FRAGS];
116 void *va; /* virtual address of first byte */
117 unsigned int nfrags; /* # of fragments */
118 unsigned int tot_len; /* total length of fragments */
119 bool usembufs; /* use mbufs for fragments */
122 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
123 const struct pkt_gl *gl);
125 struct sge_rspq { /* state for an SGE response queue */
126 struct adapter *adapter; /* adapter that this queue belongs to */
127 struct rte_eth_dev *eth_dev; /* associated rte eth device */
128 struct rte_mempool *mb_pool; /* associated mempool */
130 dma_addr_t phys_addr; /* physical address of the ring */
131 __be64 *desc; /* address of HW response ring */
132 const __be64 *cur_desc; /* current descriptor in queue */
134 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
135 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
136 struct sge_qstat *stat;
138 unsigned int cidx; /* consumer index */
139 unsigned int gts_idx; /* last gts write sent */
140 unsigned int iqe_len; /* entry size */
141 unsigned int size; /* capacity of response queue */
142 int offset; /* offset into current Rx buffer */
144 u8 gen; /* current generation bit */
145 u8 intr_params; /* interrupt holdoff parameters */
146 u8 next_intr_params; /* holdoff params for next interrupt */
147 u8 pktcnt_idx; /* interrupt packet threshold */
148 u8 port_id; /* associated port-id */
149 u8 idx; /* queue index within its group */
150 u16 cntxt_id; /* SGE relative QID for the response Q */
151 u16 abs_id; /* absolute SGE id for the response q */
153 rspq_handler_t handler; /* associated handler for this response q */
156 struct sge_eth_rx_stats { /* Ethernet rx queue statistics */
157 u64 pkts; /* # of ethernet packets */
158 u64 rx_bytes; /* # of ethernet bytes */
159 u64 rx_cso; /* # of Rx checksum offloads */
160 u64 vlan_ex; /* # of Rx VLAN extractions */
161 u64 rx_drops; /* # of packets dropped due to no mem */
164 struct sge_eth_rxq { /* a SW Ethernet Rx queue */
165 struct sge_rspq rspq;
167 struct sge_eth_rx_stats stats;
168 bool usembufs; /* one ingress packet per mbuf FL buffer */
169 } __rte_cache_aligned;
172 * Currently there are two types of coalesce WR. Type 0 needs 48 bytes per
173 * packet (if one sgl is present) and type 1 needs 32 bytes. This means
174 * that type 0 can fit a maximum of 10 packets per WR and type 1 can fit
175 * 15 packets. We need to keep track of the mbuf pointers in a coalesce WR
176 * to be able to free those mbufs when we get completions back from the FW.
177 * Allocating the maximum number of pointers in every tx desc is a waste
178 * of memory resources so we only store 2 pointers per tx desc which should
179 * be enough since a tx desc can only fit 2 packets in the best case
180 * scenario where a packet needs 32 bytes.
182 #define ETH_COALESCE_PKT_NUM 15
183 #define ETH_COALESCE_VF_PKT_NUM 7
184 #define ETH_COALESCE_PKT_PER_DESC 2
186 struct tx_eth_coal_desc {
187 struct rte_mbuf *mbuf[ETH_COALESCE_PKT_PER_DESC];
188 struct ulptx_sgl *sgl[ETH_COALESCE_PKT_PER_DESC];
196 struct tx_sw_desc { /* SW state per Tx descriptor */
197 struct rte_mbuf *mbuf;
198 struct ulptx_sgl *sgl;
199 struct tx_eth_coal_desc coalesce;
203 EQ_STOPPED = (1 << 0),
206 struct eth_coalesce {
213 __u8 ethmacdst[ETHER_ADDR_LEN];
214 __u8 ethmacsrc[ETHER_ADDR_LEN];
220 struct tx_desc *desc; /* address of HW Tx descriptor ring */
221 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
222 struct sge_qstat *stat; /* queue status entry */
223 struct eth_coalesce coalesce; /* coalesce info */
225 uint64_t phys_addr; /* physical address of the ring */
227 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
228 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
230 unsigned int cntxt_id; /* SGE relative QID for the Tx Q */
231 unsigned int in_use; /* # of in-use Tx descriptors */
232 unsigned int size; /* # of descriptors */
233 unsigned int cidx; /* SW consumer index */
234 unsigned int pidx; /* producer index */
235 unsigned int dbidx; /* last idx when db ring was done */
236 unsigned int equeidx; /* last sent credit request */
237 unsigned int last_pidx; /* last pidx recorded by tx monitor */
238 unsigned int last_coal_idx;/* last coal-idx recorded by tx monitor */
241 int db_disabled; /* doorbell state */
242 unsigned short db_pidx; /* doorbell producer index */
243 unsigned short db_pidx_inc; /* doorbell producer increment */
246 struct sge_eth_tx_stats { /* Ethernet tx queue statistics */
247 u64 pkts; /* # of ethernet packets */
248 u64 tx_bytes; /* # of ethernet bytes */
249 u64 tso; /* # of TSO requests */
250 u64 tx_cso; /* # of Tx checksum offloads */
251 u64 vlan_ins; /* # of Tx VLAN insertions */
252 u64 mapping_err; /* # of I/O MMU packet mapping errors */
253 u64 coal_wr; /* # of coalesced wr */
254 u64 coal_pkts; /* # of coalesced packets */
257 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
259 struct rte_eth_dev *eth_dev; /* port that this queue belongs to */
260 struct rte_eth_dev_data *data;
261 struct sge_eth_tx_stats stats; /* queue statistics */
262 rte_spinlock_t txq_lock;
264 unsigned int flags; /* flags for state of the queue */
265 } __rte_cache_aligned;
267 struct sge_ctrl_txq { /* State for an SGE control Tx queue */
268 struct sge_txq q; /* txq */
269 struct adapter *adapter; /* adapter associated with this queue */
270 rte_spinlock_t ctrlq_lock; /* control queue lock */
271 u8 full; /* the Tx ring is full */
272 u64 txp; /* number of transmits */
273 struct rte_mempool *mb_pool; /* mempool to generate ctrl pkts */
274 } __rte_cache_aligned;
277 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
278 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
279 struct sge_rspq fw_evtq __rte_cache_aligned;
280 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
282 u16 max_ethqsets; /* # of available Ethernet queue sets */
283 u32 stat_len; /* length of status page at ring end */
284 u32 pktshift; /* padding between CPL & packet data */
286 /* response queue interrupt parameters */
287 u16 timer_val[SGE_NTIMERS];
288 u8 counter_val[SGE_NCOUNTERS];
290 u32 fl_align; /* response queue message alignment */
291 u32 fl_pg_order; /* large page allocation size */
292 u32 fl_starve_thres; /* Free List starvation threshold */
295 #define T4_OS_NEEDS_MBOX_LOCKING 1
298 * OS Lock/List primitives for those interfaces in the Common Code which
303 TAILQ_ENTRY(mbox_entry) next;
306 TAILQ_HEAD(mbox_list, mbox_entry);
308 struct adapter_devargs {
311 bool tx_mode_latency;
315 struct rte_pci_device *pdev; /* associated rte pci device */
316 struct rte_eth_dev *eth_dev; /* first port's rte eth device */
317 struct adapter_params params; /* adapter parameters */
318 struct port_info *port[MAX_NPORTS];/* ports belonging to this adapter */
319 struct sge sge; /* associated SGE */
321 /* support for single-threading access to adapter mailbox registers */
322 struct mbox_list mbox_list;
323 rte_spinlock_t mbox_lock;
325 u8 *regs; /* pointer to registers region */
326 u8 *bar2; /* pointer to bar2 region */
327 unsigned long flags; /* adapter flags */
328 unsigned int mbox; /* associated mailbox */
329 unsigned int pf; /* associated physical function id */
331 unsigned int vpd_busy;
332 unsigned int vpd_flag;
334 int use_unpacked_mode; /* unpacked rx mode state */
335 rte_spinlock_t win0_lock;
337 rte_spinlock_t flow_lock; /* Serialize access for rte_flow ops */
339 unsigned int clipt_start; /* CLIP table start */
340 unsigned int clipt_end; /* CLIP table end */
341 unsigned int l2t_start; /* Layer 2 table start */
342 unsigned int l2t_end; /* Layer 2 table end */
343 struct clip_tbl *clipt; /* CLIP table */
344 struct l2t_data *l2t; /* Layer 2 table */
345 struct smt_data *smt; /* Source mac table */
346 struct mpstcam_table *mpstcam;
348 struct tid_info tids; /* Info used to access TID related tables */
350 struct adapter_devargs devargs;
354 * t4_os_rwlock_init - initialize rwlock
357 static inline void t4_os_rwlock_init(rte_rwlock_t *lock)
359 rte_rwlock_init(lock);
363 * t4_os_write_lock - get a write lock
366 static inline void t4_os_write_lock(rte_rwlock_t *lock)
368 rte_rwlock_write_lock(lock);
372 * t4_os_write_unlock - unlock a write lock
375 static inline void t4_os_write_unlock(rte_rwlock_t *lock)
377 rte_rwlock_write_unlock(lock);
381 * ethdev2pinfo - return the port_info structure associated with a rte_eth_dev
382 * @dev: the rte_eth_dev
384 * Return the struct port_info associated with a rte_eth_dev
386 static inline struct port_info *ethdev2pinfo(const struct rte_eth_dev *dev)
388 return dev->data->dev_private;
392 * adap2pinfo - return the port_info of a port
394 * @idx: the port index
396 * Return the port_info structure for the port of the given index.
398 static inline struct port_info *adap2pinfo(const struct adapter *adap, int idx)
400 return adap->port[idx];
404 * ethdev2adap - return the adapter structure associated with a rte_eth_dev
405 * @dev: the rte_eth_dev
407 * Return the struct adapter associated with a rte_eth_dev
409 static inline struct adapter *ethdev2adap(const struct rte_eth_dev *dev)
411 return ethdev2pinfo(dev)->adapter;
414 #define CXGBE_PCI_REG(reg) rte_read32(reg)
416 static inline uint64_t cxgbe_read_addr64(volatile void *addr)
418 uint64_t val = CXGBE_PCI_REG(addr);
419 uint64_t val2 = CXGBE_PCI_REG(((volatile uint8_t *)(addr) + 4));
421 val2 = (uint64_t)(val2 << 32);
426 static inline uint32_t cxgbe_read_addr(volatile void *addr)
428 return CXGBE_PCI_REG(addr);
431 #define CXGBE_PCI_REG_ADDR(adap, reg) \
432 ((volatile uint32_t *)((char *)(adap)->regs + (reg)))
434 #define CXGBE_READ_REG(adap, reg) \
435 cxgbe_read_addr(CXGBE_PCI_REG_ADDR((adap), (reg)))
437 #define CXGBE_READ_REG64(adap, reg) \
438 cxgbe_read_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)))
440 #define CXGBE_PCI_REG_WRITE(reg, value) rte_write32((value), (reg))
442 #define CXGBE_PCI_REG_WRITE_RELAXED(reg, value) \
443 rte_write32_relaxed((value), (reg))
445 #define CXGBE_WRITE_REG(adap, reg, value) \
446 CXGBE_PCI_REG_WRITE(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
448 #define CXGBE_WRITE_REG_RELAXED(adap, reg, value) \
449 CXGBE_PCI_REG_WRITE_RELAXED(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
451 static inline uint64_t cxgbe_write_addr64(volatile void *addr, uint64_t val)
453 CXGBE_PCI_REG_WRITE(addr, val);
454 CXGBE_PCI_REG_WRITE(((volatile uint8_t *)(addr) + 4), (val >> 32));
458 #define CXGBE_WRITE_REG64(adap, reg, value) \
459 cxgbe_write_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
462 * t4_read_reg - read a HW register
463 * @adapter: the adapter
464 * @reg_addr: the register address
466 * Returns the 32-bit value of the given HW register.
468 static inline u32 t4_read_reg(struct adapter *adapter, u32 reg_addr)
470 return CXGBE_READ_REG(adapter, reg_addr);
474 * t4_write_reg - write a HW register with barrier
475 * @adapter: the adapter
476 * @reg_addr: the register address
477 * @val: the value to write
479 * Write a 32-bit value into the given HW register.
481 static inline void t4_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
483 CXGBE_WRITE_REG(adapter, reg_addr, val);
487 * t4_write_reg_relaxed - write a HW register with no barrier
488 * @adapter: the adapter
489 * @reg_addr: the register address
490 * @val: the value to write
492 * Write a 32-bit value into the given HW register.
494 static inline void t4_write_reg_relaxed(struct adapter *adapter, u32 reg_addr,
497 CXGBE_WRITE_REG_RELAXED(adapter, reg_addr, val);
501 * t4_read_reg64 - read a 64-bit HW register
502 * @adapter: the adapter
503 * @reg_addr: the register address
505 * Returns the 64-bit value of the given HW register.
507 static inline u64 t4_read_reg64(struct adapter *adapter, u32 reg_addr)
509 return CXGBE_READ_REG64(adapter, reg_addr);
513 * t4_write_reg64 - write a 64-bit HW register
514 * @adapter: the adapter
515 * @reg_addr: the register address
516 * @val: the value to write
518 * Write a 64-bit value into the given HW register.
520 static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr,
523 CXGBE_WRITE_REG64(adapter, reg_addr, val);
526 #define PCI_STATUS 0x06 /* 16 bits */
527 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
528 #define PCI_CAPABILITY_LIST 0x34
529 /* Offset of first capability list entry */
530 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
531 #define PCI_CAP_LIST_ID 0 /* Capability ID */
532 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
533 #define PCI_EXP_DEVCTL 0x0008 /* Device control */
534 #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
535 #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
536 #define PCI_EXP_DEVCTL_PAYLOAD 0x00E0 /* Max payload */
537 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
538 #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
539 #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
540 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */
543 * t4_os_pci_write_cfg4 - 32-bit write to PCI config space
544 * @adapter: the adapter
545 * @addr: the register address
546 * @val: the value to write
548 * Write a 32-bit value into the given register in PCI config space.
550 static inline void t4_os_pci_write_cfg4(struct adapter *adapter, size_t addr,
555 if (rte_pci_write_config(adapter->pdev, &val32, sizeof(val32),
557 dev_err(adapter, "Can't write to PCI config space\n");
561 * t4_os_pci_read_cfg4 - read a 32-bit value from PCI config space
562 * @adapter: the adapter
563 * @addr: the register address
564 * @val: where to store the value read
566 * Read a 32-bit value from the given register in PCI config space.
568 static inline void t4_os_pci_read_cfg4(struct adapter *adapter, size_t addr,
571 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
573 dev_err(adapter, "Can't read from PCI config space\n");
577 * t4_os_pci_write_cfg2 - 16-bit write to PCI config space
578 * @adapter: the adapter
579 * @addr: the register address
580 * @val: the value to write
582 * Write a 16-bit value into the given register in PCI config space.
584 static inline void t4_os_pci_write_cfg2(struct adapter *adapter, size_t addr,
589 if (rte_pci_write_config(adapter->pdev, &val16, sizeof(val16),
591 dev_err(adapter, "Can't write to PCI config space\n");
595 * t4_os_pci_read_cfg2 - read a 16-bit value from PCI config space
596 * @adapter: the adapter
597 * @addr: the register address
598 * @val: where to store the value read
600 * Read a 16-bit value from the given register in PCI config space.
602 static inline void t4_os_pci_read_cfg2(struct adapter *adapter, size_t addr,
605 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
607 dev_err(adapter, "Can't read from PCI config space\n");
611 * t4_os_pci_read_cfg - read a 8-bit value from PCI config space
612 * @adapter: the adapter
613 * @addr: the register address
614 * @val: where to store the value read
616 * Read a 8-bit value from the given register in PCI config space.
618 static inline void t4_os_pci_read_cfg(struct adapter *adapter, size_t addr,
621 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
623 dev_err(adapter, "Can't read from PCI config space\n");
627 * t4_os_find_pci_capability - lookup a capability in the PCI capability list
628 * @adapter: the adapter
629 * @cap: the capability
631 * Return the address of the given capability within the PCI capability list.
633 static inline int t4_os_find_pci_capability(struct adapter *adapter, int cap)
640 t4_os_pci_read_cfg2(adapter, PCI_STATUS, &status);
641 if (!(status & PCI_STATUS_CAP_LIST)) {
642 dev_err(adapter, "PCIe capability reading failed\n");
646 t4_os_pci_read_cfg(adapter, PCI_CAPABILITY_LIST, &pos);
647 while (ttl-- && pos >= 0x40) {
649 t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_ID), &id);
657 t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_NEXT), &pos);
663 * t4_os_set_hw_addr - store a port's MAC address in SW
664 * @adapter: the adapter
665 * @port_idx: the port index
666 * @hw_addr: the Ethernet address
668 * Store the Ethernet address of the given port in SW. Called by the
669 * common code when it retrieves a port's Ethernet address from EEPROM.
671 static inline void t4_os_set_hw_addr(struct adapter *adapter, int port_idx,
674 struct port_info *pi = adap2pinfo(adapter, port_idx);
676 rte_ether_addr_copy((struct rte_ether_addr *)hw_addr,
677 &pi->eth_dev->data->mac_addrs[0]);
681 * t4_os_lock_init - initialize spinlock
682 * @lock: the spinlock
684 static inline void t4_os_lock_init(rte_spinlock_t *lock)
686 rte_spinlock_init(lock);
690 * t4_os_lock - spin until lock is acquired
691 * @lock: the spinlock
693 static inline void t4_os_lock(rte_spinlock_t *lock)
695 rte_spinlock_lock(lock);
699 * t4_os_unlock - unlock a spinlock
700 * @lock: the spinlock
702 static inline void t4_os_unlock(rte_spinlock_t *lock)
704 rte_spinlock_unlock(lock);
708 * t4_os_trylock - try to get a lock
709 * @lock: the spinlock
711 static inline int t4_os_trylock(rte_spinlock_t *lock)
713 return rte_spinlock_trylock(lock);
717 * t4_os_init_list_head - initialize
718 * @head: head of list to initialize [to empty]
720 static inline void t4_os_init_list_head(struct mbox_list *head)
725 static inline struct mbox_entry *t4_os_list_first_entry(struct mbox_list *head)
727 return TAILQ_FIRST(head);
731 * t4_os_atomic_add_tail - Enqueue list element atomically onto list
732 * @new: the entry to be addded to the queue
733 * @head: current head of the linked list
734 * @lock: lock to use to guarantee atomicity
736 static inline void t4_os_atomic_add_tail(struct mbox_entry *entry,
737 struct mbox_list *head,
738 rte_spinlock_t *lock)
741 TAILQ_INSERT_TAIL(head, entry, next);
746 * t4_os_atomic_list_del - Dequeue list element atomically from list
747 * @entry: the entry to be remove/dequeued from the list.
748 * @lock: the spinlock
750 static inline void t4_os_atomic_list_del(struct mbox_entry *entry,
751 struct mbox_list *head,
752 rte_spinlock_t *lock)
755 TAILQ_REMOVE(head, entry, next);
760 * t4_init_completion - initialize completion
761 * @c: the completion context
763 static inline void t4_init_completion(struct t4_completion *c)
766 t4_os_lock_init(&c->lock);
770 * t4_complete - set completion as done
771 * @c: the completion context
773 static inline void t4_complete(struct t4_completion *c)
775 t4_os_lock(&c->lock);
777 t4_os_unlock(&c->lock);
781 * cxgbe_port_viid - get the VI id of a port
782 * @dev: the device for the port
784 * Return the VI id of the given port.
786 static inline unsigned int cxgbe_port_viid(const struct rte_eth_dev *dev)
788 return ethdev2pinfo(dev)->viid;
791 void *t4_alloc_mem(size_t size);
792 void t4_free_mem(void *addr);
793 #define t4_os_alloc(_size) t4_alloc_mem((_size))
794 #define t4_os_free(_ptr) t4_free_mem((_ptr))
796 void t4_os_portmod_changed(const struct adapter *adap, int port_id);
797 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
799 void reclaim_completed_tx(struct sge_txq *q);
800 void t4_free_sge_resources(struct adapter *adap);
801 void t4_sge_tx_monitor_start(struct adapter *adap);
802 void t4_sge_tx_monitor_stop(struct adapter *adap);
803 int t4_eth_xmit(struct sge_eth_txq *txq, struct rte_mbuf *mbuf,
805 int t4_mgmt_tx(struct sge_ctrl_txq *txq, struct rte_mbuf *mbuf);
806 int t4_sge_init(struct adapter *adap);
807 int t4vf_sge_init(struct adapter *adap);
808 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
809 struct rte_eth_dev *eth_dev, uint16_t queue_id,
810 unsigned int iqid, int socket_id);
811 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
812 struct rte_eth_dev *eth_dev, uint16_t queue_id,
813 unsigned int iqid, int socket_id);
814 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *rspq, bool fwevtq,
815 struct rte_eth_dev *eth_dev, int intr_idx,
816 struct sge_fl *fl, rspq_handler_t handler,
817 int cong, struct rte_mempool *mp, int queue_id,
819 int t4_sge_eth_txq_start(struct sge_eth_txq *txq);
820 int t4_sge_eth_txq_stop(struct sge_eth_txq *txq);
821 void t4_sge_eth_txq_release(struct adapter *adap, struct sge_eth_txq *txq);
822 int t4_sge_eth_rxq_start(struct adapter *adap, struct sge_rspq *rq);
823 int t4_sge_eth_rxq_stop(struct adapter *adap, struct sge_rspq *rq);
824 void t4_sge_eth_rxq_release(struct adapter *adap, struct sge_eth_rxq *rxq);
825 void t4_sge_eth_clear_queues(struct port_info *pi);
826 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
828 int cxgbe_poll(struct sge_rspq *q, struct rte_mbuf **rx_pkts,
829 unsigned int budget, unsigned int *work_done);
830 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues);
831 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t flags);
833 #endif /* __T4_ADAPTER_H__ */