1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
6 /* This file should not be included directly. Include common.h instead. */
8 #ifndef __T4_ADAPTER_H__
9 #define __T4_ADAPTER_H__
11 #include <rte_bus_pci.h>
14 #include <rte_rwlock.h>
15 #include <rte_ethdev.h>
17 #include "../cxgbe_compat.h"
18 #include "../cxgbe_ofld.h"
19 #include "t4_regs_values.h"
22 MAX_ETH_QSETS = 64, /* # of Ethernet Tx/Rx queue sets */
23 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
30 PORT_RSS_DONE = (1 << 0),
34 struct adapter *adapter; /* adapter that this port belongs to */
35 struct rte_eth_dev *eth_dev; /* associated rte eth device */
36 struct port_stats stats_base; /* port statistics base */
37 struct link_config link_cfg; /* link configuration info */
39 unsigned long flags; /* port related flags */
40 short int xact_addr_filt; /* index of exact MAC address filter */
42 u16 viid; /* associated virtual interface id */
43 s8 mdio_addr; /* address of the PHY */
44 u8 port_type; /* firmware port type */
45 u8 mod_type; /* firmware module type */
46 u8 port_id; /* physical port ID */
47 u8 pidx; /* port index for this PF */
48 u8 tx_chan; /* associated channel */
50 u8 n_rx_qsets; /* # of rx qsets */
51 u8 n_tx_qsets; /* # of tx qsets */
52 u8 first_qset; /* index of first qset */
54 u16 *rss; /* rss table */
55 u8 rss_mode; /* rss mode */
56 u16 rss_size; /* size of VI's RSS table slice */
57 u64 rss_hf; /* RSS Hash Function */
60 /* Enable or disable autonegotiation. If this is set to enable,
61 * the forced link modes above are completely ignored.
63 #define AUTONEG_DISABLE 0x00
64 #define AUTONEG_ENABLE 0x01
66 enum { /* adapter flags */
67 FULL_INIT_DONE = (1 << 0),
69 USING_MSIX = (1 << 2),
70 FW_QUEUE_BOUND = (1 << 3),
72 CFG_QUEUES = (1 << 5),
76 struct rx_sw_desc { /* SW state per Rx descriptor */
77 void *buf; /* struct page or mbuf */
81 struct sge_fl { /* SGE free-buffer queue state */
83 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
85 dma_addr_t addr; /* bus address of HW ring start */
86 __be64 *desc; /* address of HW Rx descriptor ring */
88 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
89 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
91 unsigned int cntxt_id; /* SGE relative QID for the free list */
92 unsigned int size; /* capacity of free list */
94 unsigned int avail; /* # of available Rx buffers */
95 unsigned int pend_cred; /* new buffers since last FL DB ring */
96 unsigned int cidx; /* consumer index */
97 unsigned int pidx; /* producer index */
99 unsigned long alloc_failed; /* # of times buffer allocation failed */
100 unsigned long low; /* # of times momentarily starving */
103 #define MAX_MBUF_FRAGS (16384 / 512 + 2)
105 /* A packet gather list */
108 struct rte_mbuf *mbufs[MAX_MBUF_FRAGS];
110 void *va; /* virtual address of first byte */
111 unsigned int nfrags; /* # of fragments */
112 unsigned int tot_len; /* total length of fragments */
113 bool usembufs; /* use mbufs for fragments */
116 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
117 const struct pkt_gl *gl);
119 struct sge_rspq { /* state for an SGE response queue */
120 struct adapter *adapter; /* adapter that this queue belongs to */
121 struct rte_eth_dev *eth_dev; /* associated rte eth device */
122 struct rte_mempool *mb_pool; /* associated mempool */
124 dma_addr_t phys_addr; /* physical address of the ring */
125 __be64 *desc; /* address of HW response ring */
126 const __be64 *cur_desc; /* current descriptor in queue */
128 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
129 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
130 struct sge_qstat *stat;
132 unsigned int cidx; /* consumer index */
133 unsigned int gts_idx; /* last gts write sent */
134 unsigned int iqe_len; /* entry size */
135 unsigned int size; /* capacity of response queue */
136 int offset; /* offset into current Rx buffer */
138 u8 gen; /* current generation bit */
139 u8 intr_params; /* interrupt holdoff parameters */
140 u8 next_intr_params; /* holdoff params for next interrupt */
141 u8 pktcnt_idx; /* interrupt packet threshold */
142 u8 port_id; /* associated port-id */
143 u8 idx; /* queue index within its group */
144 u16 cntxt_id; /* SGE relative QID for the response Q */
145 u16 abs_id; /* absolute SGE id for the response q */
147 rspq_handler_t handler; /* associated handler for this response q */
150 struct sge_eth_rx_stats { /* Ethernet rx queue statistics */
151 u64 pkts; /* # of ethernet packets */
152 u64 rx_bytes; /* # of ethernet bytes */
153 u64 rx_cso; /* # of Rx checksum offloads */
154 u64 vlan_ex; /* # of Rx VLAN extractions */
155 u64 rx_drops; /* # of packets dropped due to no mem */
158 struct sge_eth_rxq { /* a SW Ethernet Rx queue */
159 struct sge_rspq rspq;
161 struct sge_eth_rx_stats stats;
162 bool usembufs; /* one ingress packet per mbuf FL buffer */
163 } __rte_cache_aligned;
166 * Currently there are two types of coalesce WR. Type 0 needs 48 bytes per
167 * packet (if one sgl is present) and type 1 needs 32 bytes. This means
168 * that type 0 can fit a maximum of 10 packets per WR and type 1 can fit
169 * 15 packets. We need to keep track of the mbuf pointers in a coalesce WR
170 * to be able to free those mbufs when we get completions back from the FW.
171 * Allocating the maximum number of pointers in every tx desc is a waste
172 * of memory resources so we only store 2 pointers per tx desc which should
173 * be enough since a tx desc can only fit 2 packets in the best case
174 * scenario where a packet needs 32 bytes.
176 #define ETH_COALESCE_PKT_NUM 15
177 #define ETH_COALESCE_VF_PKT_NUM 7
178 #define ETH_COALESCE_PKT_PER_DESC 2
180 struct tx_eth_coal_desc {
181 struct rte_mbuf *mbuf[ETH_COALESCE_PKT_PER_DESC];
182 struct ulptx_sgl *sgl[ETH_COALESCE_PKT_PER_DESC];
190 struct tx_sw_desc { /* SW state per Tx descriptor */
191 struct rte_mbuf *mbuf;
192 struct ulptx_sgl *sgl;
193 struct tx_eth_coal_desc coalesce;
197 EQ_STOPPED = (1 << 0),
200 struct eth_coalesce {
207 __u8 ethmacdst[ETHER_ADDR_LEN];
208 __u8 ethmacsrc[ETHER_ADDR_LEN];
214 struct tx_desc *desc; /* address of HW Tx descriptor ring */
215 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
216 struct sge_qstat *stat; /* queue status entry */
217 struct eth_coalesce coalesce; /* coalesce info */
219 uint64_t phys_addr; /* physical address of the ring */
221 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
222 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
224 unsigned int cntxt_id; /* SGE relative QID for the Tx Q */
225 unsigned int in_use; /* # of in-use Tx descriptors */
226 unsigned int size; /* # of descriptors */
227 unsigned int cidx; /* SW consumer index */
228 unsigned int pidx; /* producer index */
229 unsigned int dbidx; /* last idx when db ring was done */
230 unsigned int equeidx; /* last sent credit request */
231 unsigned int last_pidx; /* last pidx recorded by tx monitor */
232 unsigned int last_coal_idx;/* last coal-idx recorded by tx monitor */
235 int db_disabled; /* doorbell state */
236 unsigned short db_pidx; /* doorbell producer index */
237 unsigned short db_pidx_inc; /* doorbell producer increment */
240 struct sge_eth_tx_stats { /* Ethernet tx queue statistics */
241 u64 pkts; /* # of ethernet packets */
242 u64 tx_bytes; /* # of ethernet bytes */
243 u64 tso; /* # of TSO requests */
244 u64 tx_cso; /* # of Tx checksum offloads */
245 u64 vlan_ins; /* # of Tx VLAN insertions */
246 u64 mapping_err; /* # of I/O MMU packet mapping errors */
247 u64 coal_wr; /* # of coalesced wr */
248 u64 coal_pkts; /* # of coalesced packets */
251 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
253 struct rte_eth_dev *eth_dev; /* port that this queue belongs to */
254 struct rte_eth_dev_data *data;
255 struct sge_eth_tx_stats stats; /* queue statistics */
256 rte_spinlock_t txq_lock;
258 unsigned int flags; /* flags for state of the queue */
259 } __rte_cache_aligned;
261 struct sge_ctrl_txq { /* State for an SGE control Tx queue */
262 struct sge_txq q; /* txq */
263 struct adapter *adapter; /* adapter associated with this queue */
264 rte_spinlock_t ctrlq_lock; /* control queue lock */
265 u8 full; /* the Tx ring is full */
266 u64 txp; /* number of transmits */
267 struct rte_mempool *mb_pool; /* mempool to generate ctrl pkts */
268 } __rte_cache_aligned;
271 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
272 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
273 struct sge_rspq fw_evtq __rte_cache_aligned;
274 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
276 u16 max_ethqsets; /* # of available Ethernet queue sets */
277 u32 stat_len; /* length of status page at ring end */
278 u32 pktshift; /* padding between CPL & packet data */
280 /* response queue interrupt parameters */
281 u16 timer_val[SGE_NTIMERS];
282 u8 counter_val[SGE_NCOUNTERS];
284 u32 fl_align; /* response queue message alignment */
285 u32 fl_pg_order; /* large page allocation size */
286 u32 fl_starve_thres; /* Free List starvation threshold */
289 #define T4_OS_NEEDS_MBOX_LOCKING 1
292 * OS Lock/List primitives for those interfaces in the Common Code which
297 TAILQ_ENTRY(mbox_entry) next;
300 TAILQ_HEAD(mbox_list, mbox_entry);
302 struct adapter_devargs {
305 bool tx_mode_latency;
309 struct rte_pci_device *pdev; /* associated rte pci device */
310 struct rte_eth_dev *eth_dev; /* first port's rte eth device */
311 struct adapter_params params; /* adapter parameters */
312 struct port_info *port[MAX_NPORTS];/* ports belonging to this adapter */
313 struct sge sge; /* associated SGE */
315 /* support for single-threading access to adapter mailbox registers */
316 struct mbox_list mbox_list;
317 rte_spinlock_t mbox_lock;
319 u8 *regs; /* pointer to registers region */
320 u8 *bar2; /* pointer to bar2 region */
321 unsigned long flags; /* adapter flags */
322 unsigned int mbox; /* associated mailbox */
323 unsigned int pf; /* associated physical function id */
325 unsigned int vpd_busy;
326 unsigned int vpd_flag;
328 int use_unpacked_mode; /* unpacked rx mode state */
329 rte_spinlock_t win0_lock;
331 rte_spinlock_t flow_lock; /* Serialize access for rte_flow ops */
333 unsigned int clipt_start; /* CLIP table start */
334 unsigned int clipt_end; /* CLIP table end */
335 unsigned int l2t_start; /* Layer 2 table start */
336 unsigned int l2t_end; /* Layer 2 table end */
337 struct clip_tbl *clipt; /* CLIP table */
338 struct l2t_data *l2t; /* Layer 2 table */
339 struct mpstcam_table *mpstcam;
341 struct tid_info tids; /* Info used to access TID related tables */
343 struct adapter_devargs devargs;
347 * t4_os_rwlock_init - initialize rwlock
350 static inline void t4_os_rwlock_init(rte_rwlock_t *lock)
352 rte_rwlock_init(lock);
356 * t4_os_write_lock - get a write lock
359 static inline void t4_os_write_lock(rte_rwlock_t *lock)
361 rte_rwlock_write_lock(lock);
365 * t4_os_write_unlock - unlock a write lock
368 static inline void t4_os_write_unlock(rte_rwlock_t *lock)
370 rte_rwlock_write_unlock(lock);
374 * ethdev2pinfo - return the port_info structure associated with a rte_eth_dev
375 * @dev: the rte_eth_dev
377 * Return the struct port_info associated with a rte_eth_dev
379 static inline struct port_info *ethdev2pinfo(const struct rte_eth_dev *dev)
381 return dev->data->dev_private;
385 * adap2pinfo - return the port_info of a port
387 * @idx: the port index
389 * Return the port_info structure for the port of the given index.
391 static inline struct port_info *adap2pinfo(const struct adapter *adap, int idx)
393 return adap->port[idx];
397 * ethdev2adap - return the adapter structure associated with a rte_eth_dev
398 * @dev: the rte_eth_dev
400 * Return the struct adapter associated with a rte_eth_dev
402 static inline struct adapter *ethdev2adap(const struct rte_eth_dev *dev)
404 return ethdev2pinfo(dev)->adapter;
407 #define CXGBE_PCI_REG(reg) rte_read32(reg)
409 static inline uint64_t cxgbe_read_addr64(volatile void *addr)
411 uint64_t val = CXGBE_PCI_REG(addr);
412 uint64_t val2 = CXGBE_PCI_REG(((volatile uint8_t *)(addr) + 4));
414 val2 = (uint64_t)(val2 << 32);
419 static inline uint32_t cxgbe_read_addr(volatile void *addr)
421 return CXGBE_PCI_REG(addr);
424 #define CXGBE_PCI_REG_ADDR(adap, reg) \
425 ((volatile uint32_t *)((char *)(adap)->regs + (reg)))
427 #define CXGBE_READ_REG(adap, reg) \
428 cxgbe_read_addr(CXGBE_PCI_REG_ADDR((adap), (reg)))
430 #define CXGBE_READ_REG64(adap, reg) \
431 cxgbe_read_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)))
433 #define CXGBE_PCI_REG_WRITE(reg, value) rte_write32((value), (reg))
435 #define CXGBE_PCI_REG_WRITE_RELAXED(reg, value) \
436 rte_write32_relaxed((value), (reg))
438 #define CXGBE_WRITE_REG(adap, reg, value) \
439 CXGBE_PCI_REG_WRITE(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
441 #define CXGBE_WRITE_REG_RELAXED(adap, reg, value) \
442 CXGBE_PCI_REG_WRITE_RELAXED(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
444 static inline uint64_t cxgbe_write_addr64(volatile void *addr, uint64_t val)
446 CXGBE_PCI_REG_WRITE(addr, val);
447 CXGBE_PCI_REG_WRITE(((volatile uint8_t *)(addr) + 4), (val >> 32));
451 #define CXGBE_WRITE_REG64(adap, reg, value) \
452 cxgbe_write_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
455 * t4_read_reg - read a HW register
456 * @adapter: the adapter
457 * @reg_addr: the register address
459 * Returns the 32-bit value of the given HW register.
461 static inline u32 t4_read_reg(struct adapter *adapter, u32 reg_addr)
463 return CXGBE_READ_REG(adapter, reg_addr);
467 * t4_write_reg - write a HW register with barrier
468 * @adapter: the adapter
469 * @reg_addr: the register address
470 * @val: the value to write
472 * Write a 32-bit value into the given HW register.
474 static inline void t4_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
476 CXGBE_WRITE_REG(adapter, reg_addr, val);
480 * t4_write_reg_relaxed - write a HW register with no barrier
481 * @adapter: the adapter
482 * @reg_addr: the register address
483 * @val: the value to write
485 * Write a 32-bit value into the given HW register.
487 static inline void t4_write_reg_relaxed(struct adapter *adapter, u32 reg_addr,
490 CXGBE_WRITE_REG_RELAXED(adapter, reg_addr, val);
494 * t4_read_reg64 - read a 64-bit HW register
495 * @adapter: the adapter
496 * @reg_addr: the register address
498 * Returns the 64-bit value of the given HW register.
500 static inline u64 t4_read_reg64(struct adapter *adapter, u32 reg_addr)
502 return CXGBE_READ_REG64(adapter, reg_addr);
506 * t4_write_reg64 - write a 64-bit HW register
507 * @adapter: the adapter
508 * @reg_addr: the register address
509 * @val: the value to write
511 * Write a 64-bit value into the given HW register.
513 static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr,
516 CXGBE_WRITE_REG64(adapter, reg_addr, val);
519 #define PCI_STATUS 0x06 /* 16 bits */
520 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
521 #define PCI_CAPABILITY_LIST 0x34
522 /* Offset of first capability list entry */
523 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
524 #define PCI_CAP_LIST_ID 0 /* Capability ID */
525 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
526 #define PCI_EXP_DEVCTL 0x0008 /* Device control */
527 #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
528 #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
529 #define PCI_EXP_DEVCTL_PAYLOAD 0x00E0 /* Max payload */
530 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
531 #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
532 #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
533 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */
536 * t4_os_pci_write_cfg4 - 32-bit write to PCI config space
537 * @adapter: the adapter
538 * @addr: the register address
539 * @val: the value to write
541 * Write a 32-bit value into the given register in PCI config space.
543 static inline void t4_os_pci_write_cfg4(struct adapter *adapter, size_t addr,
548 if (rte_pci_write_config(adapter->pdev, &val32, sizeof(val32),
550 dev_err(adapter, "Can't write to PCI config space\n");
554 * t4_os_pci_read_cfg4 - read a 32-bit value from PCI config space
555 * @adapter: the adapter
556 * @addr: the register address
557 * @val: where to store the value read
559 * Read a 32-bit value from the given register in PCI config space.
561 static inline void t4_os_pci_read_cfg4(struct adapter *adapter, size_t addr,
564 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
566 dev_err(adapter, "Can't read from PCI config space\n");
570 * t4_os_pci_write_cfg2 - 16-bit write to PCI config space
571 * @adapter: the adapter
572 * @addr: the register address
573 * @val: the value to write
575 * Write a 16-bit value into the given register in PCI config space.
577 static inline void t4_os_pci_write_cfg2(struct adapter *adapter, size_t addr,
582 if (rte_pci_write_config(adapter->pdev, &val16, sizeof(val16),
584 dev_err(adapter, "Can't write to PCI config space\n");
588 * t4_os_pci_read_cfg2 - read a 16-bit value from PCI config space
589 * @adapter: the adapter
590 * @addr: the register address
591 * @val: where to store the value read
593 * Read a 16-bit value from the given register in PCI config space.
595 static inline void t4_os_pci_read_cfg2(struct adapter *adapter, size_t addr,
598 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
600 dev_err(adapter, "Can't read from PCI config space\n");
604 * t4_os_pci_read_cfg - read a 8-bit value from PCI config space
605 * @adapter: the adapter
606 * @addr: the register address
607 * @val: where to store the value read
609 * Read a 8-bit value from the given register in PCI config space.
611 static inline void t4_os_pci_read_cfg(struct adapter *adapter, size_t addr,
614 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
616 dev_err(adapter, "Can't read from PCI config space\n");
620 * t4_os_find_pci_capability - lookup a capability in the PCI capability list
621 * @adapter: the adapter
622 * @cap: the capability
624 * Return the address of the given capability within the PCI capability list.
626 static inline int t4_os_find_pci_capability(struct adapter *adapter, int cap)
633 t4_os_pci_read_cfg2(adapter, PCI_STATUS, &status);
634 if (!(status & PCI_STATUS_CAP_LIST)) {
635 dev_err(adapter, "PCIe capability reading failed\n");
639 t4_os_pci_read_cfg(adapter, PCI_CAPABILITY_LIST, &pos);
640 while (ttl-- && pos >= 0x40) {
642 t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_ID), &id);
650 t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_NEXT), &pos);
656 * t4_os_set_hw_addr - store a port's MAC address in SW
657 * @adapter: the adapter
658 * @port_idx: the port index
659 * @hw_addr: the Ethernet address
661 * Store the Ethernet address of the given port in SW. Called by the
662 * common code when it retrieves a port's Ethernet address from EEPROM.
664 static inline void t4_os_set_hw_addr(struct adapter *adapter, int port_idx,
667 struct port_info *pi = adap2pinfo(adapter, port_idx);
669 rte_ether_addr_copy((struct rte_ether_addr *)hw_addr,
670 &pi->eth_dev->data->mac_addrs[0]);
674 * t4_os_lock_init - initialize spinlock
675 * @lock: the spinlock
677 static inline void t4_os_lock_init(rte_spinlock_t *lock)
679 rte_spinlock_init(lock);
683 * t4_os_lock - spin until lock is acquired
684 * @lock: the spinlock
686 static inline void t4_os_lock(rte_spinlock_t *lock)
688 rte_spinlock_lock(lock);
692 * t4_os_unlock - unlock a spinlock
693 * @lock: the spinlock
695 static inline void t4_os_unlock(rte_spinlock_t *lock)
697 rte_spinlock_unlock(lock);
701 * t4_os_trylock - try to get a lock
702 * @lock: the spinlock
704 static inline int t4_os_trylock(rte_spinlock_t *lock)
706 return rte_spinlock_trylock(lock);
710 * t4_os_init_list_head - initialize
711 * @head: head of list to initialize [to empty]
713 static inline void t4_os_init_list_head(struct mbox_list *head)
718 static inline struct mbox_entry *t4_os_list_first_entry(struct mbox_list *head)
720 return TAILQ_FIRST(head);
724 * t4_os_atomic_add_tail - Enqueue list element atomically onto list
725 * @new: the entry to be addded to the queue
726 * @head: current head of the linked list
727 * @lock: lock to use to guarantee atomicity
729 static inline void t4_os_atomic_add_tail(struct mbox_entry *entry,
730 struct mbox_list *head,
731 rte_spinlock_t *lock)
734 TAILQ_INSERT_TAIL(head, entry, next);
739 * t4_os_atomic_list_del - Dequeue list element atomically from list
740 * @entry: the entry to be remove/dequeued from the list.
741 * @lock: the spinlock
743 static inline void t4_os_atomic_list_del(struct mbox_entry *entry,
744 struct mbox_list *head,
745 rte_spinlock_t *lock)
748 TAILQ_REMOVE(head, entry, next);
753 * t4_init_completion - initialize completion
754 * @c: the completion context
756 static inline void t4_init_completion(struct t4_completion *c)
759 t4_os_lock_init(&c->lock);
763 * t4_complete - set completion as done
764 * @c: the completion context
766 static inline void t4_complete(struct t4_completion *c)
768 t4_os_lock(&c->lock);
770 t4_os_unlock(&c->lock);
774 * cxgbe_port_viid - get the VI id of a port
775 * @dev: the device for the port
777 * Return the VI id of the given port.
779 static inline unsigned int cxgbe_port_viid(const struct rte_eth_dev *dev)
781 return ethdev2pinfo(dev)->viid;
784 void *t4_alloc_mem(size_t size);
785 void t4_free_mem(void *addr);
786 #define t4_os_alloc(_size) t4_alloc_mem((_size))
787 #define t4_os_free(_ptr) t4_free_mem((_ptr))
789 void t4_os_portmod_changed(const struct adapter *adap, int port_id);
790 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
792 void reclaim_completed_tx(struct sge_txq *q);
793 void t4_free_sge_resources(struct adapter *adap);
794 void t4_sge_tx_monitor_start(struct adapter *adap);
795 void t4_sge_tx_monitor_stop(struct adapter *adap);
796 int t4_eth_xmit(struct sge_eth_txq *txq, struct rte_mbuf *mbuf,
798 int t4_mgmt_tx(struct sge_ctrl_txq *txq, struct rte_mbuf *mbuf);
799 int t4_sge_init(struct adapter *adap);
800 int t4vf_sge_init(struct adapter *adap);
801 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
802 struct rte_eth_dev *eth_dev, uint16_t queue_id,
803 unsigned int iqid, int socket_id);
804 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
805 struct rte_eth_dev *eth_dev, uint16_t queue_id,
806 unsigned int iqid, int socket_id);
807 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *rspq, bool fwevtq,
808 struct rte_eth_dev *eth_dev, int intr_idx,
809 struct sge_fl *fl, rspq_handler_t handler,
810 int cong, struct rte_mempool *mp, int queue_id,
812 int t4_sge_eth_txq_start(struct sge_eth_txq *txq);
813 int t4_sge_eth_txq_stop(struct sge_eth_txq *txq);
814 void t4_sge_eth_txq_release(struct adapter *adap, struct sge_eth_txq *txq);
815 int t4_sge_eth_rxq_start(struct adapter *adap, struct sge_rspq *rq);
816 int t4_sge_eth_rxq_stop(struct adapter *adap, struct sge_rspq *rq);
817 void t4_sge_eth_rxq_release(struct adapter *adap, struct sge_eth_rxq *rxq);
818 void t4_sge_eth_clear_queues(struct port_info *pi);
819 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
821 int cxgbe_poll(struct sge_rspq *q, struct rte_mbuf **rx_pkts,
822 unsigned int budget, unsigned int *work_done);
823 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues);
824 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t flags);
826 #endif /* __T4_ADAPTER_H__ */