1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
6 /* This file should not be included directly. Include common.h instead. */
8 #ifndef __T4_ADAPTER_H__
9 #define __T4_ADAPTER_H__
11 #include <rte_bus_pci.h>
14 #include <rte_ethdev.h>
16 #include "cxgbe_compat.h"
17 #include "t4_regs_values.h"
18 #include "cxgbe_ofld.h"
21 MAX_ETH_QSETS = 64, /* # of Ethernet Tx/Rx queue sets */
22 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
29 PORT_RSS_DONE = (1 << 0),
33 struct adapter *adapter; /* adapter that this port belongs to */
34 struct rte_eth_dev *eth_dev; /* associated rte eth device */
35 struct port_stats stats_base; /* port statistics base */
36 struct link_config link_cfg; /* link configuration info */
38 unsigned long flags; /* port related flags */
39 short int xact_addr_filt; /* index of exact MAC address filter */
41 u16 viid; /* associated virtual interface id */
42 s8 mdio_addr; /* address of the PHY */
43 u8 port_type; /* firmware port type */
44 u8 mod_type; /* firmware module type */
45 u8 port_id; /* physical port ID */
46 u8 pidx; /* port index for this PF */
47 u8 tx_chan; /* associated channel */
49 u8 n_rx_qsets; /* # of rx qsets */
50 u8 n_tx_qsets; /* # of tx qsets */
51 u8 first_qset; /* index of first qset */
53 u16 *rss; /* rss table */
54 u8 rss_mode; /* rss mode */
55 u16 rss_size; /* size of VI's RSS table slice */
56 u64 rss_hf; /* RSS Hash Function */
59 /* Enable or disable autonegotiation. If this is set to enable,
60 * the forced link modes above are completely ignored.
62 #define AUTONEG_DISABLE 0x00
63 #define AUTONEG_ENABLE 0x01
65 enum { /* adapter flags */
66 FULL_INIT_DONE = (1 << 0),
68 USING_MSIX = (1 << 2),
69 FW_QUEUE_BOUND = (1 << 3),
71 CFG_QUEUES = (1 << 5),
75 struct rx_sw_desc { /* SW state per Rx descriptor */
76 void *buf; /* struct page or mbuf */
80 struct sge_fl { /* SGE free-buffer queue state */
82 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
84 dma_addr_t addr; /* bus address of HW ring start */
85 __be64 *desc; /* address of HW Rx descriptor ring */
87 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
88 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
90 unsigned int cntxt_id; /* SGE relative QID for the free list */
91 unsigned int size; /* capacity of free list */
93 unsigned int avail; /* # of available Rx buffers */
94 unsigned int pend_cred; /* new buffers since last FL DB ring */
95 unsigned int cidx; /* consumer index */
96 unsigned int pidx; /* producer index */
98 unsigned long alloc_failed; /* # of times buffer allocation failed */
99 unsigned long low; /* # of times momentarily starving */
102 #define MAX_MBUF_FRAGS (16384 / 512 + 2)
104 /* A packet gather list */
107 struct rte_mbuf *mbufs[MAX_MBUF_FRAGS];
109 void *va; /* virtual address of first byte */
110 unsigned int nfrags; /* # of fragments */
111 unsigned int tot_len; /* total length of fragments */
112 bool usembufs; /* use mbufs for fragments */
115 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
116 const struct pkt_gl *gl);
118 struct sge_rspq { /* state for an SGE response queue */
119 struct adapter *adapter; /* adapter that this queue belongs to */
120 struct rte_eth_dev *eth_dev; /* associated rte eth device */
121 struct rte_mempool *mb_pool; /* associated mempool */
123 dma_addr_t phys_addr; /* physical address of the ring */
124 __be64 *desc; /* address of HW response ring */
125 const __be64 *cur_desc; /* current descriptor in queue */
127 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
128 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
129 struct sge_qstat *stat;
131 unsigned int cidx; /* consumer index */
132 unsigned int gts_idx; /* last gts write sent */
133 unsigned int iqe_len; /* entry size */
134 unsigned int size; /* capacity of response queue */
135 int offset; /* offset into current Rx buffer */
137 u8 gen; /* current generation bit */
138 u8 intr_params; /* interrupt holdoff parameters */
139 u8 next_intr_params; /* holdoff params for next interrupt */
140 u8 pktcnt_idx; /* interrupt packet threshold */
141 u8 port_id; /* associated port-id */
142 u8 idx; /* queue index within its group */
143 u16 cntxt_id; /* SGE relative QID for the response Q */
144 u16 abs_id; /* absolute SGE id for the response q */
146 rspq_handler_t handler; /* associated handler for this response q */
149 struct sge_eth_rx_stats { /* Ethernet rx queue statistics */
150 u64 pkts; /* # of ethernet packets */
151 u64 rx_bytes; /* # of ethernet bytes */
152 u64 rx_cso; /* # of Rx checksum offloads */
153 u64 vlan_ex; /* # of Rx VLAN extractions */
154 u64 rx_drops; /* # of packets dropped due to no mem */
157 struct sge_eth_rxq { /* a SW Ethernet Rx queue */
158 struct sge_rspq rspq;
160 struct sge_eth_rx_stats stats;
161 bool usembufs; /* one ingress packet per mbuf FL buffer */
162 } __rte_cache_aligned;
165 * Currently there are two types of coalesce WR. Type 0 needs 48 bytes per
166 * packet (if one sgl is present) and type 1 needs 32 bytes. This means
167 * that type 0 can fit a maximum of 10 packets per WR and type 1 can fit
168 * 15 packets. We need to keep track of the mbuf pointers in a coalesce WR
169 * to be able to free those mbufs when we get completions back from the FW.
170 * Allocating the maximum number of pointers in every tx desc is a waste
171 * of memory resources so we only store 2 pointers per tx desc which should
172 * be enough since a tx desc can only fit 2 packets in the best case
173 * scenario where a packet needs 32 bytes.
175 #define ETH_COALESCE_PKT_NUM 15
176 #define ETH_COALESCE_VF_PKT_NUM 7
177 #define ETH_COALESCE_PKT_PER_DESC 2
179 struct tx_eth_coal_desc {
180 struct rte_mbuf *mbuf[ETH_COALESCE_PKT_PER_DESC];
181 struct ulptx_sgl *sgl[ETH_COALESCE_PKT_PER_DESC];
189 struct tx_sw_desc { /* SW state per Tx descriptor */
190 struct rte_mbuf *mbuf;
191 struct ulptx_sgl *sgl;
192 struct tx_eth_coal_desc coalesce;
196 EQ_STOPPED = (1 << 0),
199 struct eth_coalesce {
206 __u8 ethmacdst[ETHER_ADDR_LEN];
207 __u8 ethmacsrc[ETHER_ADDR_LEN];
213 struct tx_desc *desc; /* address of HW Tx descriptor ring */
214 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
215 struct sge_qstat *stat; /* queue status entry */
216 struct eth_coalesce coalesce; /* coalesce info */
218 uint64_t phys_addr; /* physical address of the ring */
220 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
221 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
223 unsigned int cntxt_id; /* SGE relative QID for the Tx Q */
224 unsigned int in_use; /* # of in-use Tx descriptors */
225 unsigned int size; /* # of descriptors */
226 unsigned int cidx; /* SW consumer index */
227 unsigned int pidx; /* producer index */
228 unsigned int dbidx; /* last idx when db ring was done */
229 unsigned int equeidx; /* last sent credit request */
230 unsigned int last_pidx; /* last pidx recorded by tx monitor */
231 unsigned int last_coal_idx;/* last coal-idx recorded by tx monitor */
234 int db_disabled; /* doorbell state */
235 unsigned short db_pidx; /* doorbell producer index */
236 unsigned short db_pidx_inc; /* doorbell producer increment */
239 struct sge_eth_tx_stats { /* Ethernet tx queue statistics */
240 u64 pkts; /* # of ethernet packets */
241 u64 tx_bytes; /* # of ethernet bytes */
242 u64 tso; /* # of TSO requests */
243 u64 tx_cso; /* # of Tx checksum offloads */
244 u64 vlan_ins; /* # of Tx VLAN insertions */
245 u64 mapping_err; /* # of I/O MMU packet mapping errors */
246 u64 coal_wr; /* # of coalesced wr */
247 u64 coal_pkts; /* # of coalesced packets */
250 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
252 struct rte_eth_dev *eth_dev; /* port that this queue belongs to */
253 struct rte_eth_dev_data *data;
254 struct sge_eth_tx_stats stats; /* queue statistics */
255 rte_spinlock_t txq_lock;
257 unsigned int flags; /* flags for state of the queue */
258 } __rte_cache_aligned;
260 struct sge_ctrl_txq { /* State for an SGE control Tx queue */
261 struct sge_txq q; /* txq */
262 struct adapter *adapter; /* adapter associated with this queue */
263 rte_spinlock_t ctrlq_lock; /* control queue lock */
264 u8 full; /* the Tx ring is full */
265 u64 txp; /* number of transmits */
266 struct rte_mempool *mb_pool; /* mempool to generate ctrl pkts */
267 } __rte_cache_aligned;
270 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
271 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
272 struct sge_rspq fw_evtq __rte_cache_aligned;
273 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
275 u16 max_ethqsets; /* # of available Ethernet queue sets */
276 u32 stat_len; /* length of status page at ring end */
277 u32 pktshift; /* padding between CPL & packet data */
279 /* response queue interrupt parameters */
280 u16 timer_val[SGE_NTIMERS];
281 u8 counter_val[SGE_NCOUNTERS];
283 u32 fl_align; /* response queue message alignment */
284 u32 fl_pg_order; /* large page allocation size */
285 u32 fl_starve_thres; /* Free List starvation threshold */
288 #define T4_OS_NEEDS_MBOX_LOCKING 1
291 * OS Lock/List primitives for those interfaces in the Common Code which
296 TAILQ_ENTRY(mbox_entry) next;
299 TAILQ_HEAD(mbox_list, mbox_entry);
302 struct rte_pci_device *pdev; /* associated rte pci device */
303 struct rte_eth_dev *eth_dev; /* first port's rte eth device */
304 struct adapter_params params; /* adapter parameters */
305 struct port_info *port[MAX_NPORTS];/* ports belonging to this adapter */
306 struct sge sge; /* associated SGE */
308 /* support for single-threading access to adapter mailbox registers */
309 struct mbox_list mbox_list;
310 rte_spinlock_t mbox_lock;
312 u8 *regs; /* pointer to registers region */
313 u8 *bar2; /* pointer to bar2 region */
314 unsigned long flags; /* adapter flags */
315 unsigned int mbox; /* associated mailbox */
316 unsigned int pf; /* associated physical function id */
318 unsigned int vpd_busy;
319 unsigned int vpd_flag;
321 int use_unpacked_mode; /* unpacked rx mode state */
322 rte_spinlock_t win0_lock;
324 struct tid_info tids; /* Info used to access TID related tables */
328 * ethdev2pinfo - return the port_info structure associated with a rte_eth_dev
329 * @dev: the rte_eth_dev
331 * Return the struct port_info associated with a rte_eth_dev
333 static inline struct port_info *ethdev2pinfo(const struct rte_eth_dev *dev)
335 return (struct port_info *)dev->data->dev_private;
339 * adap2pinfo - return the port_info of a port
341 * @idx: the port index
343 * Return the port_info structure for the port of the given index.
345 static inline struct port_info *adap2pinfo(const struct adapter *adap, int idx)
347 return adap->port[idx];
351 * ethdev2adap - return the adapter structure associated with a rte_eth_dev
352 * @dev: the rte_eth_dev
354 * Return the struct adapter associated with a rte_eth_dev
356 static inline struct adapter *ethdev2adap(const struct rte_eth_dev *dev)
358 return ethdev2pinfo(dev)->adapter;
361 #define CXGBE_PCI_REG(reg) rte_read32(reg)
363 static inline uint64_t cxgbe_read_addr64(volatile void *addr)
365 uint64_t val = CXGBE_PCI_REG(addr);
366 uint64_t val2 = CXGBE_PCI_REG(((volatile uint8_t *)(addr) + 4));
368 val2 = (uint64_t)(val2 << 32);
373 static inline uint32_t cxgbe_read_addr(volatile void *addr)
375 return CXGBE_PCI_REG(addr);
378 #define CXGBE_PCI_REG_ADDR(adap, reg) \
379 ((volatile uint32_t *)((char *)(adap)->regs + (reg)))
381 #define CXGBE_READ_REG(adap, reg) \
382 cxgbe_read_addr(CXGBE_PCI_REG_ADDR((adap), (reg)))
384 #define CXGBE_READ_REG64(adap, reg) \
385 cxgbe_read_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)))
387 #define CXGBE_PCI_REG_WRITE(reg, value) rte_write32((value), (reg))
389 #define CXGBE_PCI_REG_WRITE_RELAXED(reg, value) \
390 rte_write32_relaxed((value), (reg))
392 #define CXGBE_WRITE_REG(adap, reg, value) \
393 CXGBE_PCI_REG_WRITE(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
395 #define CXGBE_WRITE_REG_RELAXED(adap, reg, value) \
396 CXGBE_PCI_REG_WRITE_RELAXED(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
398 static inline uint64_t cxgbe_write_addr64(volatile void *addr, uint64_t val)
400 CXGBE_PCI_REG_WRITE(addr, val);
401 CXGBE_PCI_REG_WRITE(((volatile uint8_t *)(addr) + 4), (val >> 32));
405 #define CXGBE_WRITE_REG64(adap, reg, value) \
406 cxgbe_write_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
409 * t4_read_reg - read a HW register
410 * @adapter: the adapter
411 * @reg_addr: the register address
413 * Returns the 32-bit value of the given HW register.
415 static inline u32 t4_read_reg(struct adapter *adapter, u32 reg_addr)
417 u32 val = CXGBE_READ_REG(adapter, reg_addr);
419 CXGBE_DEBUG_REG(adapter, "read register 0x%x value 0x%x\n", reg_addr,
425 * t4_write_reg - write a HW register with barrier
426 * @adapter: the adapter
427 * @reg_addr: the register address
428 * @val: the value to write
430 * Write a 32-bit value into the given HW register.
432 static inline void t4_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
434 CXGBE_DEBUG_REG(adapter, "setting register 0x%x to 0x%x\n", reg_addr,
436 CXGBE_WRITE_REG(adapter, reg_addr, val);
440 * t4_write_reg_relaxed - write a HW register with no barrier
441 * @adapter: the adapter
442 * @reg_addr: the register address
443 * @val: the value to write
445 * Write a 32-bit value into the given HW register.
447 static inline void t4_write_reg_relaxed(struct adapter *adapter, u32 reg_addr,
450 CXGBE_DEBUG_REG(adapter, "setting register 0x%x to 0x%x\n", reg_addr,
452 CXGBE_WRITE_REG_RELAXED(adapter, reg_addr, val);
456 * t4_read_reg64 - read a 64-bit HW register
457 * @adapter: the adapter
458 * @reg_addr: the register address
460 * Returns the 64-bit value of the given HW register.
462 static inline u64 t4_read_reg64(struct adapter *adapter, u32 reg_addr)
464 u64 val = CXGBE_READ_REG64(adapter, reg_addr);
466 CXGBE_DEBUG_REG(adapter, "64-bit read register %#x value %#llx\n",
467 reg_addr, (unsigned long long)val);
472 * t4_write_reg64 - write a 64-bit HW register
473 * @adapter: the adapter
474 * @reg_addr: the register address
475 * @val: the value to write
477 * Write a 64-bit value into the given HW register.
479 static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr,
482 CXGBE_DEBUG_REG(adapter, "setting register %#x to %#llx\n", reg_addr,
483 (unsigned long long)val);
485 CXGBE_WRITE_REG64(adapter, reg_addr, val);
488 #define PCI_STATUS 0x06 /* 16 bits */
489 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
490 #define PCI_CAPABILITY_LIST 0x34
491 /* Offset of first capability list entry */
492 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
493 #define PCI_CAP_LIST_ID 0 /* Capability ID */
494 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
495 #define PCI_EXP_DEVCTL 0x0008 /* Device control */
496 #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
497 #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
498 #define PCI_EXP_DEVCTL_PAYLOAD 0x00E0 /* Max payload */
499 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
500 #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
501 #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
502 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */
505 * t4_os_pci_write_cfg4 - 32-bit write to PCI config space
506 * @adapter: the adapter
507 * @addr: the register address
508 * @val: the value to write
510 * Write a 32-bit value into the given register in PCI config space.
512 static inline void t4_os_pci_write_cfg4(struct adapter *adapter, size_t addr,
517 if (rte_pci_write_config(adapter->pdev, &val32, sizeof(val32),
519 dev_err(adapter, "Can't write to PCI config space\n");
523 * t4_os_pci_read_cfg4 - read a 32-bit value from PCI config space
524 * @adapter: the adapter
525 * @addr: the register address
526 * @val: where to store the value read
528 * Read a 32-bit value from the given register in PCI config space.
530 static inline void t4_os_pci_read_cfg4(struct adapter *adapter, size_t addr,
533 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
535 dev_err(adapter, "Can't read from PCI config space\n");
539 * t4_os_pci_write_cfg2 - 16-bit write to PCI config space
540 * @adapter: the adapter
541 * @addr: the register address
542 * @val: the value to write
544 * Write a 16-bit value into the given register in PCI config space.
546 static inline void t4_os_pci_write_cfg2(struct adapter *adapter, size_t addr,
551 if (rte_pci_write_config(adapter->pdev, &val16, sizeof(val16),
553 dev_err(adapter, "Can't write to PCI config space\n");
557 * t4_os_pci_read_cfg2 - read a 16-bit value from PCI config space
558 * @adapter: the adapter
559 * @addr: the register address
560 * @val: where to store the value read
562 * Read a 16-bit value from the given register in PCI config space.
564 static inline void t4_os_pci_read_cfg2(struct adapter *adapter, size_t addr,
567 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
569 dev_err(adapter, "Can't read from PCI config space\n");
573 * t4_os_pci_read_cfg - read a 8-bit value from PCI config space
574 * @adapter: the adapter
575 * @addr: the register address
576 * @val: where to store the value read
578 * Read a 8-bit value from the given register in PCI config space.
580 static inline void t4_os_pci_read_cfg(struct adapter *adapter, size_t addr,
583 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
585 dev_err(adapter, "Can't read from PCI config space\n");
589 * t4_os_find_pci_capability - lookup a capability in the PCI capability list
590 * @adapter: the adapter
591 * @cap: the capability
593 * Return the address of the given capability within the PCI capability list.
595 static inline int t4_os_find_pci_capability(struct adapter *adapter, int cap)
602 t4_os_pci_read_cfg2(adapter, PCI_STATUS, &status);
603 if (!(status & PCI_STATUS_CAP_LIST)) {
604 dev_err(adapter, "PCIe capability reading failed\n");
608 t4_os_pci_read_cfg(adapter, PCI_CAPABILITY_LIST, &pos);
609 while (ttl-- && pos >= 0x40) {
611 t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_ID), &id);
619 t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_NEXT), &pos);
625 * t4_os_set_hw_addr - store a port's MAC address in SW
626 * @adapter: the adapter
627 * @port_idx: the port index
628 * @hw_addr: the Ethernet address
630 * Store the Ethernet address of the given port in SW. Called by the
631 * common code when it retrieves a port's Ethernet address from EEPROM.
633 static inline void t4_os_set_hw_addr(struct adapter *adapter, int port_idx,
636 struct port_info *pi = adap2pinfo(adapter, port_idx);
638 ether_addr_copy((struct ether_addr *)hw_addr,
639 &pi->eth_dev->data->mac_addrs[0]);
643 * t4_os_lock_init - initialize spinlock
644 * @lock: the spinlock
646 static inline void t4_os_lock_init(rte_spinlock_t *lock)
648 rte_spinlock_init(lock);
652 * t4_os_lock - spin until lock is acquired
653 * @lock: the spinlock
655 static inline void t4_os_lock(rte_spinlock_t *lock)
657 rte_spinlock_lock(lock);
661 * t4_os_unlock - unlock a spinlock
662 * @lock: the spinlock
664 static inline void t4_os_unlock(rte_spinlock_t *lock)
666 rte_spinlock_unlock(lock);
670 * t4_os_trylock - try to get a lock
671 * @lock: the spinlock
673 static inline int t4_os_trylock(rte_spinlock_t *lock)
675 return rte_spinlock_trylock(lock);
679 * t4_os_init_list_head - initialize
680 * @head: head of list to initialize [to empty]
682 static inline void t4_os_init_list_head(struct mbox_list *head)
687 static inline struct mbox_entry *t4_os_list_first_entry(struct mbox_list *head)
689 return TAILQ_FIRST(head);
693 * t4_os_atomic_add_tail - Enqueue list element atomically onto list
694 * @new: the entry to be addded to the queue
695 * @head: current head of the linked list
696 * @lock: lock to use to guarantee atomicity
698 static inline void t4_os_atomic_add_tail(struct mbox_entry *entry,
699 struct mbox_list *head,
700 rte_spinlock_t *lock)
703 TAILQ_INSERT_TAIL(head, entry, next);
708 * t4_os_atomic_list_del - Dequeue list element atomically from list
709 * @entry: the entry to be remove/dequeued from the list.
710 * @lock: the spinlock
712 static inline void t4_os_atomic_list_del(struct mbox_entry *entry,
713 struct mbox_list *head,
714 rte_spinlock_t *lock)
717 TAILQ_REMOVE(head, entry, next);
722 * t4_init_completion - initialize completion
723 * @c: the completion context
725 static inline void t4_init_completion(struct t4_completion *c)
728 t4_os_lock_init(&c->lock);
732 * t4_complete - set completion as done
733 * @c: the completion context
735 static inline void t4_complete(struct t4_completion *c)
737 t4_os_lock(&c->lock);
739 t4_os_unlock(&c->lock);
742 void *t4_alloc_mem(size_t size);
743 void t4_free_mem(void *addr);
744 #define t4_os_alloc(_size) t4_alloc_mem((_size))
745 #define t4_os_free(_ptr) t4_free_mem((_ptr))
747 void t4_os_portmod_changed(const struct adapter *adap, int port_id);
748 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
750 void reclaim_completed_tx(struct sge_txq *q);
751 void t4_free_sge_resources(struct adapter *adap);
752 void t4_sge_tx_monitor_start(struct adapter *adap);
753 void t4_sge_tx_monitor_stop(struct adapter *adap);
754 int t4_eth_xmit(struct sge_eth_txq *txq, struct rte_mbuf *mbuf,
756 int t4_mgmt_tx(struct sge_ctrl_txq *txq, struct rte_mbuf *mbuf);
757 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
758 const struct pkt_gl *gl);
759 int t4_sge_init(struct adapter *adap);
760 int t4vf_sge_init(struct adapter *adap);
761 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
762 struct rte_eth_dev *eth_dev, uint16_t queue_id,
763 unsigned int iqid, int socket_id);
764 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
765 struct rte_eth_dev *eth_dev, uint16_t queue_id,
766 unsigned int iqid, int socket_id);
767 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *rspq, bool fwevtq,
768 struct rte_eth_dev *eth_dev, int intr_idx,
769 struct sge_fl *fl, rspq_handler_t handler,
770 int cong, struct rte_mempool *mp, int queue_id,
772 int t4_sge_eth_txq_start(struct sge_eth_txq *txq);
773 int t4_sge_eth_txq_stop(struct sge_eth_txq *txq);
774 void t4_sge_eth_txq_release(struct adapter *adap, struct sge_eth_txq *txq);
775 int t4_sge_eth_rxq_start(struct adapter *adap, struct sge_rspq *rq);
776 int t4_sge_eth_rxq_stop(struct adapter *adap, struct sge_rspq *rq);
777 void t4_sge_eth_rxq_release(struct adapter *adap, struct sge_eth_rxq *rxq);
778 void t4_sge_eth_clear_queues(struct port_info *pi);
779 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
781 int cxgbe_poll(struct sge_rspq *q, struct rte_mbuf **rx_pkts,
782 unsigned int budget, unsigned int *work_done);
783 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues);
784 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t flags);
786 #endif /* __T4_ADAPTER_H__ */